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[PATCH 00/10] Introduce eSPI support


  • To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>
  • Date: Thu, 24 Jul 2025 14:57:24 +0000
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  • Cc: Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
  • Delivery-date: Thu, 24 Jul 2025 15:01:21 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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  • Thread-topic: [PATCH 00/10] Introduce eSPI support

Hello everyone!

### Background
Unlike the Linux kernel, which has supported extended shared peripheral
interrupts (eSPIs) since 2019 [1], Xen currently lacks support for this
interrupt range. For SoCs with GICv3.1+, this feature may be essential
because critical devices, such as consoles required for booting Xen
itself, may rely on eSPIs. Additionally, these platforms require eSPI
support for fully functional domains, as any device using eSPIs cannot
currently be used with Xen setups. Without eSPI support, Xen cannot run
properly on these platforms, significantly limiting its usability on
modern ARM hardware.

This patch series adds support for the extended shared peripheral
interrupt (eSPI) range (INTIDs 4096-5119 [2](ranges of INTIDs)) for Xen
and guest domains. The implementation uses a generic approach to handle
eSPIs, similar to regular SPIs, while maintaining compatibility with the
existing SPI range. Functionality remains unchanged for setups that do
not require eSPIs.

The series includes:
1) General refactoring of common IRQ operations with GIC registers to
improve code readability, simplify further maintenance and prepare the
key functions for eSPI implementation.
2) Introducing a new Kconfig option (default y) to enable or disable
eSPI support. Disabling this option prevents unnecessary resource
allocation for setups that do not require eSPIs.
3) Adding additional resources to store required information and operate
with up to 1024 interrupts from eSPI range.
4) Adjusting assertions and checks to pass verification for INTIDs in
the eSPI range.
5) Configuration of eSPI-specific registers during GIC initialization
for systems with GICv3.1+ hardware.
6) Enables eSPI MMIO emulation for vGIC, allowing guest domains to
access and operate within the eSPI's INTIDs.

[1] 
https://github.com/torvalds/linux/commit/211bddd210a6746e4fdfa9b6cdfbdb15026530a7
[2] 
https://developer.arm.com/documentation/198123/0302/Arm-GIC-fundamentals?lang=en

Leonid Komarianskyi (10):
  xen/arm: gicv3: refactor obtaining GIC addresses for common operations
  xen/arm/irq: add handling for IRQs in the eSPI range
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
  xen/arm/irq: allow assignment/releasing of eSPI interrupts
  xen/arm: gic/irq: permit routing of eSPI interrupts to Xen and domains
  xen/arm/irq: allow eSPI processing in the do_IRQ function
  xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
  xen/arm: vgic: add resource management for extended SPIs
  xen/arm: domain_build: adjust Dom0 IRQ handling to support eSPIs
  xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers

 xen/arch/arm/Kconfig                   |   9 +
 xen/arch/arm/domain_build.c            |  10 +
 xen/arch/arm/gic-v3.c                  | 172 +++++++++++++----
 xen/arch/arm/gic.c                     |   6 +-
 xen/arch/arm/include/asm/gic.h         |   7 +
 xen/arch/arm/include/asm/gic_v3_defs.h |  37 ++++
 xen/arch/arm/include/asm/irq.h         |  26 +++
 xen/arch/arm/include/asm/vgic.h        |  39 ++++
 xen/arch/arm/irq.c                     |  42 ++++-
 xen/arch/arm/vgic-v3.c                 | 248 ++++++++++++++++++++++++-
 xen/arch/arm/vgic.c                    | 133 ++++++++++++-
 11 files changed, 682 insertions(+), 47 deletions(-)

-- 
2.34.1



 


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