[00:05.0] xen_pt_realize: Assigning real physical device 02:00.0 to devfn 0x28
[00:05.0] xen_pt_register_regions: IO region 0 registered (size=0x00000100 base_addr=0x0000e000 type: 0x1)
[00:05.0] xen_pt_register_regions: IO region 1 registered (size=0x00004000 base_addr=0xdf2c0000 type: 0x4)
[00:05.0] xen_pt_register_regions: IO region 3 registered (size=0x00040000 base_addr=0xdf280000 type: 0x4)
[00:05.0] xen_pt_register_regions: Expansion ROM registered (size=0x00080000 base_addr=0xdf200000)
[00:05.0] xen_pt_config_reg_init: Offset 0x000e mismatch! Emulated=0x0080, host=0x0000, syncing to 0x0080.
[00:05.0] xen_pt_config_reg_init: Offset 0x0010 mismatch! Emulated=0x0000, host=0xe001, syncing to 0xe001.
[00:05.0] xen_pt_config_reg_init: Offset 0x0014 mismatch! Emulated=0x0000, host=0xdf2c0004, syncing to 0xdf2c0004.
[00:05.0] xen_pt_config_reg_init: Offset 0x001c mismatch! Emulated=0x0000, host=0xdf280004, syncing to 0xdf280004.
[00:05.0] xen_pt_config_reg_init: Offset 0x0052 mismatch! Emulated=0x0000, host=0x0603, syncing to 0x0603.
[00:05.0] xen_pt_config_reg_init: Offset 0x00aa mismatch! Emulated=0x0000, host=0x0080, syncing to 0x0080.
[00:05.0] xen_pt_config_reg_init: Offset 0x006c mismatch! Emulated=0x0000, host=0x10008025, syncing to 0x8025.
[00:05.0] xen_pt_config_reg_init: Offset 0x007a mismatch! Emulated=0x0000, host=0x1042, syncing to 0x1042.
[00:05.0] xen_pt_msix_init: get MSI-X table BAR base 0xdf2c0000
[00:05.0] xen_pt_msix_init: table_off = 0x2000, total_entries = 15
[00:05.0] xen_pt_msix_init: mapping physical MSI-X table to 0x7f8444534000
[00:05.0] xen_pt_config_reg_init: Offset 0x00c2 mismatch! Emulated=0x0000, host=0x000e, syncing to 0x000e.
[00:05.0] xen_pt_pci_intx: intx=1
[00:05.0] xen_pt_realize: Real physical device 02:00.0 registered successfully
[00:05.0] pci_msix_write: Write to MSIX table entry 0 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 1 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 2 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 3 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 4 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 5 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 6 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 7 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 8 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 9 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 10 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 11 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 12 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 13 CTRL, masked: 0
[00:05.0] pci_msix_write: Write to MSIX table entry 14 CTRL, masked: 0
[00:05.0] xen_pt_msixctrl_reg_write: Enabling MSIX, setting up entries
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 0 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 0
[00:05.0] msi_msix_update: Updating MSI-X with pirq 55 gvec 0x81 gflags 0x1301 (entry: 0)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 1 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 1
[00:05.0] msi_msix_update: Updating MSI-X with pirq 54 gvec 0xb1 gflags 0x1302 (entry: 0x1)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 2 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 2
[00:05.0] msi_msix_update: Updating MSI-X with pirq 53 gvec 0xb1 gflags 0x1304 (entry: 0x2)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 3 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 3
[00:05.0] msi_msix_update: Updating MSI-X with pirq 52 gvec 0xb1 gflags 0x1308 (entry: 0x3)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 4 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 4
[00:05.0] msi_msix_update: Updating MSI-X with pirq 51 gvec 0x71 gflags 0x1301 (entry: 0x4)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 5 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 5
[00:05.0] msi_msix_update: Updating MSI-X with pirq 50 gvec 0x81 gflags 0x1302 (entry: 0x5)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 6 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 6
[00:05.0] msi_msix_update: Updating MSI-X with pirq 49 gvec 0x81 gflags 0x1304 (entry: 0x6)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 7 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 7
[00:05.0] msi_msix_update: Updating MSI-X with pirq 48 gvec 0x81 gflags 0x1308 (entry: 0x7)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 8 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 8
[00:05.0] msi_msix_update: Updating MSI-X with pirq 47 gvec 0x61 gflags 0x1301 (entry: 0x8)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 9 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 9
[00:05.0] msi_msix_update: Updating MSI-X with pirq 46 gvec 0x71 gflags 0x1302 (entry: 0x9)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 10 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 10
[00:05.0] msi_msix_update: Updating MSI-X with pirq 45 gvec 0x71 gflags 0x1304 (entry: 0xa)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 11 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 11
[00:05.0] msi_msix_update: Updating MSI-X with pirq 44 gvec 0x71 gflags 0x1308 (entry: 0xb)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 12 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 12
[00:05.0] msi_msix_update: Updating MSI-X with pirq 43 gvec 0x51 gflags 0x1301 (entry: 0xc)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 13 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 13
[00:05.0] msi_msix_update: Updating MSI-X with pirq 42 gvec 0x61 gflags 0x1302 (entry: 0xd)
[00:05.0] xen_pt_msix_update_one: Setting up MSIX vector 14 PIRQ: -1 Masked: 0
[00:05.0] msi_msix_setup: Mapping PIRQ for MSIX entry 14
[00:05.0] msi_msix_update: Updating MSI-X with pirq 41 gvec 0x61 gflags 0x1304 (entry: 0xe)
[00:05.0] xen_pt_msixctrl_reg_write: enable MSI-X
