[Xen-devel] [PATCH] x86: MISALIGNSSE feature depends on SSE

["Jan Beulich" <JBeulich@xxxxxxxx>]

Suggested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -196,8 +196,9 @@ def crunch_numbers(state):
 
         # SSE is taken to mean support for the %XMM registers as well as the
         # instructions.  Several futher instruction sets are built on core
-        # %XMM support, without specific inter-dependencies.
-        SSE: [SSE2, SSE3, SSSE3, SSE4A,
+        # %XMM support, without specific inter-dependencies.  Additionally
+        # AMD has a special mis-alignment sub-mode.
+        SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
               AESNI, SHA],
 
         # SSE2 was re-specified as core instructions for 64bit.

Attachment: x86-misalignsse-dep.patch
Description: Text document

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