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RE: [Xen-devel] [PATCH 4] MCA physical address check when calculate domain

Jan Beulich wrote:
>>>> On 10.05.11 at 12:46, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx> wrote:
>> Jan Beulich wrote:
>>>>>> On 10.05.11 at 08:38, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx>
>>>>>> wrote: 
>>>> As for physical addr, the addr in MCi_ADDR reg may be linear add/
>>>> physical add/ setment offset. according to Intel SDM, the addr in
>>>> MCi_ADDR reg is physical addr only when: 1). MISCV bit of
>>>> MCi_STATUS set; 2). ADDRV bit of MCi_STATUS set;
>>>> 3). address mode of MCi_MISC (bit 6~8) = 010;
>>> I realize this is what's being documented currently. Going back to
>>> the newest hard copy manual I still have (PentiumPro, which luckily
>>> is the first one where the banked implementation is described),
>>> there's no MCi_MISC (it's documented, but said to not be
>>> implemented on these old CPUs), and the description for the address
>>> reads "The address returned is either 32-bit virtual, 32-bit
>>> linear, or 36-bit physical". Now I certainly don't care much about
>>> PPro anymore, but I wonder when MCi_MISC was first implemented in
>>> the way your patch is using it. 
>> Seems needn't care about when MCi_MISC first implemented.
>> MCi_STATUS_MISCV check can make sure accessing MCi_MISC safely.
> That wasn't my point. The question is whether there's a way to tell
> the address format when there's no MCi_MISC implemented (or whether
> all but *very* old CPUs have these registers for *all* their banks).
> Jan

CC Tony, our RAS expert.

For the case MCi_MISC not implemented, I don't know exactly. 
no MCi_MISC implemented only occur at very old Intel cpu. More exactly, it's 
only for P5 processors. After P6, all processors has MCi_MISC as far as we 
check till now.
For P5 processors, s/w make no sense to figure out address format --> the basic 
action is to show the error at console and then aborting execution, according 
to Intel SDM.

And, according to Intel SDM, for Machine check MSRs in the Pentium 4, Intel 
Xeon, and P6 family processors, they have these MSRs for all their banks.
However, I think SDM didn't guarantee so in all future processor, so s/w much 
check MISCV/ADDRV strictly abide by SDM, and handle different cases correctly 
at MCE handler and GP handler.

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