CPUIDLE: Handle C2 LAPIC timer & TSC stop

ACPI C2 is quite possible mapped to CPU C3 or deeper state, so thinking from worst cases, enable C3 like entry/exit handling for C2 by default. Option 'lapic_timer_c2_ok' can be used to select simple C2 entry/exit only if the user make sure that LAPIC tmr & TSC will not be stop during C2.

Signed-off-by: Wei Gang <gang.wei@intel.com>

diff -r f38addf8a900 xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c	Fri Sep 19 18:10:38 2008 +0800
+++ b/xen/arch/x86/acpi/cpu_idle.c	Fri Sep 19 18:10:54 2008 +0800
@@ -63,6 +63,8 @@ static void (*pm_idle_save) (void) __rea
 static void (*pm_idle_save) (void) __read_mostly;
 unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER - 1;
 integer_param("max_cstate", max_cstate);
+int local_apic_timer_c2_ok __read_mostly = 0;
+boolean_param("lapic_timer_c2_ok", local_apic_timer_c2_ok);
 
 static struct acpi_processor_power processor_powers[NR_CPUS];
 
@@ -268,18 +270,21 @@ static void acpi_processor_idle(void)
         break;
 
     case ACPI_STATE_C2:
-        /* Get start time (ticks) */
-        t1 = inl(pmtmr_ioport);
-        /* Invoke C2 */
-        acpi_idle_do_entry(cx);
-        /* Get end time (ticks) */
-        t2 = inl(pmtmr_ioport);
+        if ( local_apic_timer_c2_ok )
+        {
+            /* Get start time (ticks) */
+            t1 = inl(pmtmr_ioport);
+            /* Invoke C2 */
+            acpi_idle_do_entry(cx);
+            /* Get end time (ticks) */
+            t2 = inl(pmtmr_ioport);
 
-        /* Re-enable interrupts */
-        local_irq_enable();
-        /* Compute time (ticks) that we were actually asleep */
-        sleep_ticks = ticks_elapsed(t1, t2);
-        break;
+            /* Re-enable interrupts */
+            local_irq_enable();
+            /* Compute time (ticks) that we were actually asleep */
+            sleep_ticks = ticks_elapsed(t1, t2);
+            break;
+        }
 
     case ACPI_STATE_C3:
         /*