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[Xen-devel] irr_xen in CSET:11673

  • To: <xen-devel@xxxxxxxxxxxxxxxxxxx>
  • From: "Dong, Eddie" <eddie.dong@xxxxxxxxx>
  • Date: Thu, 12 Oct 2006 22:15:57 +0800
  • Delivery-date: Thu, 12 Oct 2006 07:17:54 -0700
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: AcbtrxjfbYLuSD+XQzqLZ2zGdQFMjQAGB7vQAAYlAbA=
  • Thread-topic: irr_xen in CSET:11673

        In CSET 11673, I noticed that you add another set of irr
        The comments say:
[XEN][HVM] Make sure that the interrupt which event channel events come
on is level triggered rather than edge triggered, since it's a PCI
This is complicated by the possibility that another PCI device could be
on the same interrupt; the workaround is to have two irr registers
for the PIC and APIC, and have qemu and Xen generated interrupts go
into different ones.

        In previous model (before CSET 11673), the correctness is
guaranateed in guest platform where the IRQ # used for this pseudo IRQ
(xen event channel) is exclusively occupied by the xen event channel. It
looks like you want to share this IRQ # with other platform IRQ. I am
not sure if this is necessary rather than the complexity.

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