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Re: [Xen-devel] RE: [Xen-changelog] [xen-unstable] [HVM][SVM] Obtaining instruction address needs to mask to 32 bits

  • To: "Petersson, Mats" <Mats.Petersson@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx>
  • From: Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>
  • Date: Mon, 02 Oct 2006 14:06:20 +0100
  • Delivery-date: Mon, 02 Oct 2006 06:05:22 -0700
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: Acbkj2Ycm+fX3Gs5TrexzyyKH0xy7gBfZ8EgAAKtui4AAAQ+oAAC8CS0
  • Thread-topic: [Xen-devel] RE: [Xen-changelog] [xen-unstable] [HVM][SVM] Obtaining instruction address needs to mask to 32 bits

On 2/10/06 12:56, "Petersson, Mats" <Mats.Petersson@xxxxxxx> wrote:

> Where we're adding to EIP we probably should take this into acocunt -
> although most code wouldn't naturally wrap the IP (in fact, I think it's
> a fault to do so - but I can't confirm that from any of my books), so
> it's probably a very obscure corner-case - but it's probably a bit
> nightmarish to debug so it's possibly better to have code that deals
> with it correctly. I'll figure out if it's a fault or "wrap" that is the
> correct operation first...

I think it faults on AMD and silently wraps on Intel. One of the Xbox hacks
relies on this 'feature' to break into the secure bootstrap sequence. I
doubt anyone legitimately relies on it so I'm not too concerned about this

Also, back to my original point, it's probably a good idea to mask the high
bits of RIP when in 16-bit mode. I doubt that the switch from 32- to 16-bit
mode guarantees to clear those high bits. Or does it?

 -- Keir

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