Hi Tristan,
When `xm trigger domain init' is called, the guest domain panics on
current OpenGFW.
The following patch enables to send INIT to guest and to call INIT
handlers(monarch and slave).
Thanks,
KAZ
Signed-off-by: Kazuhiro Suzuki <kaz@xxxxxxxxxxxxxx>
diff -r 9e4b5bb76049 edk2-sparse/EdkXenPkg/Dxe/XenSal/Sal.c
--- a/edk2-sparse/EdkXenPkg/Dxe/XenSal/Sal.c Wed Feb 20 16:26:26 2008 +0900
+++ b/edk2-sparse/EdkXenPkg/Dxe/XenSal/Sal.c Fri Mar 07 09:28:05 2008 +0900
@@ -3,10 +3,13 @@
#define BUILD_CMD(addr) ((0x80000000 | (addr)) & ~3)
#define REG_OFFSET(addr) (0x00000000000000FF & (addr))
-struct {
+struct Fptr {
UINT64 Ip;
UINT64 Gp;
} SalRendezVector;
+
+struct Fptr *SalMonarchInitVector = (struct Fptr *)0x80000000ffffff80;
+struct Fptr *SalSlaveInitVector = (struct Fptr *)0x80000000ffffff90 ;
STATIC
EFI_SAL_STATUS
@@ -108,11 +111,26 @@ SalProc
return (SAL_RETURN_REGS) {EFI_SAL_INVALID_ARGUMENT, r9, r10, r11};
}
status = EFI_SAL_SUCCESS;
- } else if (FunctionId == EFI_SAL_SET_VECTORS
- && Arg2 == EFI_SAL_SET_BOOT_RENDEZ_VECTOR) {
- SalRendezVector.Ip = Arg3;
- SalRendezVector.Gp = Arg4;
- status = EFI_SAL_SUCCESS;
+ } else if (FunctionId == EFI_SAL_SET_VECTORS) {
+ switch (Arg2) {
+ case EFI_SAL_SET_MCA_VECTOR:
+ return SalEmulator (FunctionId, Arg2, Arg3, Arg4, Arg5, Arg6, Arg7,
Arg8);
+ case EFI_SAL_SET_INIT_VECTOR:
+ SalMonarchInitVector->Ip = Arg3;
+ SalMonarchInitVector->Gp = Arg4;
+ SalSlaveInitVector->Ip = Arg6;
+ SalSlaveInitVector->Gp = Arg7;
+
+ status = EFI_SAL_SUCCESS;
+ return SalEmulator (FunctionId, Arg2, Arg3, Arg4, Arg5, Arg6, Arg7,
Arg8);
+ case EFI_SAL_SET_BOOT_RENDEZ_VECTOR:
+ SalRendezVector.Ip = Arg3;
+ SalRendezVector.Gp = Arg4;
+ status = EFI_SAL_SUCCESS;
+ break;
+ default:
+ return (SAL_RETURN_REGS) {EFI_SAL_INVALID_ARGUMENT, r9, r10, r11};
+ }
} else {
return SalEmulator (FunctionId, Arg2, Arg3, Arg4, Arg5, Arg6, Arg7, Arg8);
}
diff -r 9e4b5bb76049 edk2-sparse/EdkXenPkg/SecMain/Ipf/startup.s
--- a/edk2-sparse/EdkXenPkg/SecMain/Ipf/startup.s Wed Feb 20 16:26:26
2008 +0900
+++ b/edk2-sparse/EdkXenPkg/SecMain/Ipf/startup.s Wed Mar 12 14:31:06
2008 +0900
@@ -12,6 +12,26 @@
#define SCRATCH_REG5 r28
#define SCRATCH_REG6 r29
#define PR_REG r30
+
+#define UC_BIT (1<<63)
+#define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000
+#define IA64_IPI_DM_INIT 0x5
+
+/*
+ * Calculates percpu minstate address like `min_state + cpu_id * 0x200'.
+ * cr.lid is defined as follows.
+ * cr.lid = (id << 24) | (eid << 16)
+ * id and eid is set in EdkXenPkg/Dxe/XenAcpi/build.c.
+ * id = cpu_id
+ * eid = 0
+ */
+#define MINSTATE(reg,tmp) \
+ mov tmp=cr.lid;; \
+ extr tmp=tmp,24,8; \
+ movl reg=min_state;; \
+ ld8 reg=[reg]; \
+ dep.z tmp=tmp,9,8;; \
+ add reg=tmp,reg
#define VECTOR(offset) \
.org base + offset ; \
@@ -943,6 +963,346 @@ 1: break 0
.endp _start
+ .align 16
+ .globl _init
+ .proc _init
+_init:
+ MINSTATE(r2,r3);;
+ mov r17=r2 // min_state
+ add r20=16,r2
+ mov r19=ar.unat
+ ;;
+ st8.spill [r20]=r19,8 // @0
+ ;;
+ st8.spill [r20]=r1,8 // @8
+ ;;
+ st8.spill [r20]=r2,8 // @10
+ ;;
+ st8.spill [r20]=r3,8 // @18
+ ;;
+ st8.spill [r20]=r4,8 // @20
+ ;;
+ st8.spill [r20]=r5,8 // @28
+ ;;
+ st8.spill [r20]=r6,8 // @30
+ ;;
+ st8.spill [r20]=r7,8 // @38
+ ;;
+ st8.spill [r20]=r8,8 // @40
+ ;;
+ st8.spill [r20]=r9,8 // @48
+ ;;
+ st8.spill [r20]=r10,8 // @50
+ ;;
+ st8.spill [r20]=r11,8 // @58
+ ;;
+ st8.spill [r20]=r12,8 // @60
+ ;;
+ st8.spill [r20]=r13,8 // @68
+ ;;
+ st8.spill [r20]=r14,8 // @70
+ ;;
+ add r9=8,r20
+ st8.spill [r20]=r15 // @78
+ ;;
+ bsw.0;;
+ srlz.d
+
+ st8.spill [r9]=r16,8 // @80
+ ;;
+ st8.spill [r9]=r17,8 // @88
+ ;;
+ st8.spill [r9]=r18,8 // @90
+ ;;
+ st8.spill [r9]=r19,8 // @98
+ ;;
+ st8.spill [r9]=r20,8 // @a0
+ ;;
+ st8.spill [r9]=r21,8 // @a8
+ ;;
+ st8.spill [r9]=r22,8 // @b0
+ ;;
+ st8.spill [r9]=r23,8 // @b8
+ ;;
+ st8.spill [r9]=r24,8 // @c0
+ ;;
+ st8.spill [r9]=r25,8 // @c8
+ ;;
+ st8.spill [r9]=r26,8 // @d0
+ ;;
+ st8.spill [r9]=r27,8 // @d8
+ ;;
+ st8.spill [r9]=r28,8 // @e0
+ ;;
+ st8.spill [r9]=r29,8 // @e8
+ ;;
+ st8.spill [r9]=r30,8 // @f0
+ ;;
+ st8.spill [r9]=r31,8 // @f8
+ ;;
+ bsw.1;;
+ srlz.d
+
+ st8.spill [r9]=r16,8 // @100
+ ;;
+ st8.spill [r9]=r17,8 // @108
+ ;;
+ st8.spill [r9]=r18,8 // @110
+ ;;
+ st8.spill [r9]=r19,8 // @118
+ ;;
+ st8.spill [r9]=r20,8 // @120
+ ;;
+ st8.spill [r9]=r21,8 // @128
+ ;;
+ st8.spill [r9]=r22,8 // @130
+ ;;
+ st8.spill [r9]=r23,8 // @138
+ ;;
+ st8.spill [r9]=r24,8 // @140
+ ;;
+ st8.spill [r9]=r25,8 // @148
+ ;;
+ st8.spill [r9]=r26,8 // @150
+ ;;
+ st8.spill [r9]=r27,8 // @158
+ ;;
+ st8.spill [r9]=r28,8 // @160
+ ;;
+ st8.spill [r9]=r29,8 // @168
+ ;;
+ st8.spill [r9]=r30,8 // @170
+ ;;
+ st8.spill [r9]=r31,8 // @178
+
+ mov r30=pr
+ ;;
+ st8 [r9]=r30,8 // @180: pr
+ ;;
+ mov r30=b0
+ ;;
+ st8 [r9]=r30,8 // @188: b0
+ mov r30=ar.rsc
+ ;;
+ st8 [r9]=r30,8 // @190: rsc
+ mov r10=cr.iip
+ ;;
+ st8 [r9]=r10,8 // @198: cr.iip
+ mov r30=cr.ipsr
+ ;;
+ st8 [r9]=r30,8 // @1a0: cr.ipsr
+ mov r30=cr.ifs
+ ;;
+ st8 [r9]=r30,8 // @1a8: ar.ifs
+ ;;
+ st8 [r9]=r0,8 // @1b0: (xip)
+ ;;
+ st8 [r9]=r0,8 // @1b8: (xpsr)
+ ;;
+ st8 [r9]=r0,8 // @1c0: (xfs)
+
+ mov r30=b1
+ ;;
+ st8 [r9]=r30,8 // @1c8: b1
+ ;;
+
+ mov r3=cr.lid
+ ;;
+ cmp.eq p6,p7=r3,r0 // vcpu[0] is always monarch in Xen.
+ ;;
+(p7) br.sptk.many load_slave_entry_point
+ ;;
+clear_uc_bit_start:
+ mov r2=ip
+ ;;
+ add r2=clear_uc_bit_end-clear_uc_bit_start,r2
+ ;;
+ dep r2=0,r2,63,1
+ ;;
+ mov b1=r2
+ ;;
+ br.sptk.many b1
+ ;;
+clear_uc_bit_end:
+ movl r2=nr_vcpus
+ ;;
+ ld8 r2=[r2]
+ mov r4=0
+ ;;
+loop:
+ add r4=1,r4
+ ;;
+ cmp.eq p6,p7=r4,r2
+ ;;
+(p6) br load_monarch_entry_point
+ ;;
+ // Send IPI to other cpus.
+ mov r20=IA64_IPI_DM_INIT<<8
+ movl r21=UC_BIT|IA64_IPI_DEFAULT_BASE_ADDR
+ dep.z r22=r4,12,8
+ ;;
+ add r21=r21,r22
+ ;;
+ st8.rel [r21]=r20
+ ;;
+ br loop
+ ;;
+load_monarch_entry_point:
+ movl r2=monarch_init_handler
+ br 1f
+load_slave_entry_point:
+ movl r2=slave_init_handler
+1:
+ movl r12=_init_return // Set return address
+ ;;
+ ld8 r3=[r2],8 // Load init handler entry point
+ ;;
+ mov b1=r3
+ ld8 r1=[r2] // Load GP
+ ;;
+ br.call.sptk.many rp=b1
+
+_init_return:
+ MINSTATE(r2,r3);;
+ add r9=0x1c8+16,r2
+ ;;
+ ld8 r3=[r9],-8 // @1c8
+ ;;
+ mov b1=r3
+ ld8 r3=[r9],-8 // @1c0
+ ;;
+ ld8 r3=[r9],-8 // @1b8
+ ;;
+ ld8 r3=[r9],-8 // @1b0
+ ;;
+ ld8 r3=[r9],-8 // @1a8
+ ;;
+ mov cr.ifs=r3
+ ld8 r3=[r9],-8 // @1a0
+ ;;
+ mov cr.ipsr=r3
+ ld8 r3=[r9],-8 // @198
+ ;;
+ mov cr.iip=r3
+ ld8 r3=[r9],-8 // @190
+ ;;
+ mov ar.rsc=r3
+ ;;
+ ld8 r3=[r9],-8 // @188
+ ;;
+ mov b0=r3
+ ;;
+ ld8 r3=[r9],-8 // @180
+ ;;
+ mov pr=r3
+ ;;
+ bsw.1;;
+ srlz.d
+ ;;
+ ld8 r31=[r9],-8 // @178
+ ;;
+ ld8 r30=[r9],-8 // @170
+ ;;
+ ld8 r29=[r9],-8 // @168
+ ;;
+ ld8 r28=[r9],-8 // @160
+ ;;
+ ld8 r27=[r9],-8 // @158
+ ;;
+ ld8 r26=[r9],-8 // @150
+ ;;
+ ld8 r25=[r9],-8 // @148
+ ;;
+ ld8 r24=[r9],-8 // @140
+ ;;
+ ld8 r23=[r9],-8 // @138
+ ;;
+ ld8 r22=[r9],-8 // @130
+ ;;
+ ld8 r21=[r9],-8 // @128
+ ;;
+ ld8 r20=[r9],-8 // @120
+ ;;
+ ld8 r19=[r9],-8 // @118
+ ;;
+ ld8 r18=[r9],-8 // @110
+ ;;
+ ld8 r17=[r9],-8 // @108
+ ;;
+ ld8 r16=[r9],-8 // @100
+ ;;
+ bsw.0;;
+ srlz.d
+ ;;
+ ld8 r31=[r9],-8 // @f8
+ ;;
+ ld8 r30=[r9],-8 // @f0
+ ;;
+ ld8 r29=[r9],-8 // @e8
+ ;;
+ ld8 r28=[r9],-8 // @e0
+ ;;
+ ld8 r27=[r9],-8 // @d8
+ ;;
+ ld8 r26=[r9],-8 // @d0
+ ;;
+ ld8 r25=[r9],-8 // @c8
+ ;;
+ ld8 r24=[r9],-8 // @c0
+ ;;
+ ld8 r23=[r9],-8 // @b8
+ ;;
+ ld8 r22=[r9],-8 // @b0
+ ;;
+ ld8 r21=[r9],-8 // @a8
+ ;;
+ ld8 r20=[r9],-8 // @a0
+ ;;
+ ld8 r19=[r9],-8 // @98
+ ;;
+ ld8 r18=[r9],-8 // @90
+ ;;
+ ld8 r17=[r9],-8 // @88
+ ;;
+ ld8 r16=[r9],-8 // @80
+ ;;
+ ld8 r15=[r9] // @78
+ add r17=-8,r9
+ ;;
+ ld8 r14=[r17],-8 // @70
+ ;;
+ ld8 r13=[r17],-8 // @68
+ ;;
+ ld8 r12=[r17],-8 // @60
+ ;;
+ ld8 r11=[r17],-8 // @58
+ ;;
+ ld8 r10=[r17],-8 // @50
+ ;;
+ ld8 r9=[r17],-8 // @48
+ ;;
+ ld8 r8=[r17],-8 // @40
+ ;;
+ ld8 r7=[r17],-8 // @38
+ ;;
+ ld8 r6=[r17],-8 // @30
+ ;;
+ ld8 r5=[r17],-8 // @28
+ ;;
+ ld8 r4=[r17],-8 // @20
+ ;;
+ ld8 r3=[r17],-8 // @18
+ ;;
+ ld8 r2=[r17],-8 // @10
+ ;;
+ ld8 r1=[r17],-8 // @8
+ ;;
+ ld8 r17=[r17] // @0
+ ;;
+ mov ar.unat=r17
+ ;;
+ rfi
+.endp _init
/* Pal. */
.proc pal_proc
@@ -996,6 +1356,27 @@ fit_peicore:
data1 0
fit_end:
+ .org base + 0xff60
+min_state:
+ data8 0
+
+ .org base + 0xff70
+nr_vcpus::
+ data8 0
+
+ .org base + 0xff80
+monarch_init_handler:
+ data8 0
+ data8 0
+ .org base + 0xff90
+slave_init_handler:
+ data8 0
+ data8 0
+
+ .org base + 0xffa0
+pal_init_entry::
+ br.sptk.many _init
+
.org base + 0xffb0
cpu_reset: // 0xb0
br _start
diff -r 9e4b5bb76049 edk2-sparse/EdkXenPkg/SecMain/SecMain.c
--- a/edk2-sparse/EdkXenPkg/SecMain/SecMain.c Wed Feb 20 16:26:26 2008 +0900
+++ b/edk2-sparse/EdkXenPkg/SecMain/SecMain.c Tue Mar 11 10:03:27 2008 +0900
@@ -21,6 +21,9 @@ typedef struct {
} FIT_TABLE;
UINT64 iobase = 0;
+
+#define NR_CPUS 64
+static UINT8 min_state_area[NR_CPUS * 0x200];
#define IO_SPACE_ENCODE(p) ((((p) >> 2) << 12) | (p & 0xfff))
@@ -253,6 +256,36 @@ disp_hobs (void)
while (hdr->type != HOB_TYPE_TERMINAL);
}
+static int
+get_vcpu_nr (void)
+{
+ UINT8 *hob = (UINT8 *)GFW_HOB_START;
+ struct XenHobHeader *hdr;
+
+ do
+ {
+ int data_len;
+ UINT64 *data;
+
+ hdr = (struct XenHobHeader *)hob;
+ data = (UINT64 *)(hdr + 1);
+ data_len = hdr->length - sizeof (struct XenHobHeader);
+ switch (hdr->type)
+ {
+ case HOB_TYPE_NR_VCPU:
+ if (data_len != 8)
+ break;
+ return data[0];
+ default:
+ break;
+ }
+ hob += hdr->length;
+ }
+ while (hdr->type != HOB_TYPE_TERMINAL);
+
+ /* Only one vcpu by default. */
+ return 1;
+}
static volatile int val = 1234;
@@ -347,6 +380,8 @@ _ModuleEntryPoint (
UINT16 fit_len;
EFI_PEI_STARTUP_DESCRIPTOR Desc;
PeiCoreEntryType *entry;
+ UINT64 *min_state_addr = (UINT64*)0xffffff60;
+ UINT64 *nr_vcpus_addr = (UINT64*)0xffffff70;
/* Setup IO base (Kr0). */
iobase = ReadKr0 ();
@@ -422,6 +457,10 @@ _ModuleEntryPoint (
}
#endif
+ // Set reserved min state area and nr_vcpus for init handler.
+ *min_state_addr = &min_state_area;
+ *nr_vcpus_addr = get_vcpu_nr();
+
// Enable interrupt collect.
asm volatile ("ssm psr.ic");
asm volatile ("srlz.d");
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