# HG changeset patch # User yamahata@xxxxxxxxxxxxx # Date 1196062052 -32400 # Node ID 5cad3e2ecec07be552ad1fbed28b18abb9f11bd3 # Parent b771d4cc5bf79473c2b99a2215f9114f37f9085a clean up of vti external interrupt handler. consolidate vmx_interrupt handler. PATCHNAME: vmx_interrupt_clean_up Signed-off-by: Isaku Yamahata diff -r b771d4cc5bf7 -r 5cad3e2ecec0 xen/arch/ia64/vmx/vmx_ivt.S --- a/xen/arch/ia64/vmx/vmx_ivt.S Thu Nov 22 12:38:07 2007 +0900 +++ b/xen/arch/ia64/vmx/vmx_ivt.S Mon Nov 26 16:27:32 2007 +0900 @@ -608,153 +608,27 @@ END(vmx_break_fault) // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) ENTRY(vmx_interrupt) // VMX_DBG_FAULT(12) - mov r31=pr // prepare to save predicates + mov r31=pr // prepare to save predicates mov r19=12 - mov r29=cr.ipsr - ;; - tbit.z p6,p7=r29,IA64_PSR_VM_BIT - tbit.z p0,p15=r29,IA64_PSR_I_BIT - ;; -(p7) br.sptk vmx_dispatch_interrupt - ;; - mov r27=ar.rsc /* M */ - mov r20=r1 /* A */ - mov r25=ar.unat /* M */ - mov r26=ar.pfs /* I */ - mov r28=cr.iip /* M */ - cover /* B (or nothing) */ - ;; - mov r1=sp - ;; - invala /* M */ - mov r30=cr.ifs - ;; - addl r1=-IA64_PT_REGS_SIZE,r1 - ;; - adds r17=2*L1_CACHE_BYTES,r1 /* really: biggest cache-line size */ - adds r16=PT(CR_IPSR),r1 - ;; - lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES - st8 [r16]=r29 /* save cr.ipsr */ - ;; - lfetch.fault.excl.nt1 [r17] - mov r29=b0 - ;; - adds r16=PT(R8),r1 /* initialize first base pointer */ - adds r17=PT(R9),r1 /* initialize second base pointer */ - mov r18=r0 /* make sure r18 isn't NaT */ - ;; -.mem.offset 0,0; st8.spill [r16]=r8,16 -.mem.offset 8,0; st8.spill [r17]=r9,16 - ;; -.mem.offset 0,0; st8.spill [r16]=r10,24 -.mem.offset 8,0; st8.spill [r17]=r11,24 - ;; - st8 [r16]=r28,16 /* save cr.iip */ - st8 [r17]=r30,16 /* save cr.ifs */ - mov r8=ar.fpsr /* M */ - mov r9=ar.csd - mov r10=ar.ssd - movl r11=FPSR_DEFAULT /* L-unit */ - ;; - st8 [r16]=r25,16 /* save ar.unat */ - st8 [r17]=r26,16 /* save ar.pfs */ - shl r18=r18,16 /* compute ar.rsc to be used for "loadrs" */ - ;; - st8 [r16]=r27,16 /* save ar.rsc */ - adds r17=16,r17 /* skip over ar_rnat field */ - ;; - st8 [r17]=r31,16 /* save predicates */ - adds r16=16,r16 /* skip over ar_bspstore field */ - ;; - st8 [r16]=r29,16 /* save b0 */ - st8 [r17]=r18,16 /* save ar.rsc value for "loadrs" */ - ;; -.mem.offset 0,0; st8.spill [r16]=r20,16 /* save original r1 */ -.mem.offset 8,0; st8.spill [r17]=r12,16 - adds r12=-16,r1 /* switch to kernel memory stack (with 16 bytes of scratch) */ - ;; -.mem.offset 0,0; st8.spill [r16]=r13,16 -.mem.offset 8,0; st8.spill [r17]=r8,16 /* save ar.fpsr */ - MINSTATE_GET_CURRENT(r13) - ;; -.mem.offset 0,0; st8.spill [r16]=r15,16 -.mem.offset 8,0; st8.spill [r17]=r14,16 - dep r14=-1,r0,60,4 - ;; -.mem.offset 0,0; st8.spill [r16]=r2,16 -.mem.offset 8,0; st8.spill [r17]=r3,16 - adds r2=IA64_PT_REGS_R16_OFFSET,r1 - ;; - mov r8=ar.ccv - movl r1=__gp /* establish kernel global pointer */ - ;; \ - bsw.1 + VMX_SAVE_MIN_WITH_COVER_R19_NO_PANIC // uses r31; defines r2 and r3 ;; alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group mov out0=cr.ivr // pass cr.ivr as first arg + adds r3=8,r2 // set up second base pointer for SAVE_REST + ;; + ssm psr.ic + ;; + srlz.i + ;; + (p15) ssm psr.i + (pUStk) movl r14=ia64_leave_hypervisor + ;; + (pKStk) movl r14=ia64_leave_nested + VMX_SAVE_REST + mov rp=r14 + ;; add out1=16,sp // pass pointer to pt_regs as second arg - - ssm psr.ic - ;; - srlz.i - ;; - (p15) ssm psr.i - adds r3=8,r2 // set up second base pointer for SAVE_REST - srlz.i // ensure everybody knows psr.ic is back on - ;; -.mem.offset 0,0; st8.spill [r2]=r16,16 -.mem.offset 8,0; st8.spill [r3]=r17,16 - ;; -.mem.offset 0,0; st8.spill [r2]=r18,16 -.mem.offset 8,0; st8.spill [r3]=r19,16 - ;; -.mem.offset 0,0; st8.spill [r2]=r20,16 -.mem.offset 8,0; st8.spill [r3]=r21,16 - mov r18=b6 - ;; -.mem.offset 0,0; st8.spill [r2]=r22,16 -.mem.offset 8,0; st8.spill [r3]=r23,16 - mov r19=b7 - ;; -.mem.offset 0,0; st8.spill [r2]=r24,16 -.mem.offset 8,0; st8.spill [r3]=r25,16 - ;; -.mem.offset 0,0; st8.spill [r2]=r26,16 -.mem.offset 8,0; st8.spill [r3]=r27,16 - ;; -.mem.offset 0,0; st8.spill [r2]=r28,16 -.mem.offset 8,0; st8.spill [r3]=r29,16 - ;; -.mem.offset 0,0; st8.spill [r2]=r30,16 -.mem.offset 8,0; st8.spill [r3]=r31,32 - ;; - mov ar.fpsr=r11 /* M-unit */ - st8 [r2]=r8,8 /* ar.ccv */ - adds r24=PT(B6)-PT(F7),r3 - ;; - stf.spill [r2]=f6,32 - stf.spill [r3]=f7,32 - ;; - stf.spill [r2]=f8,32 - stf.spill [r3]=f9,32 - ;; - stf.spill [r2]=f10 - stf.spill [r3]=f11 - adds r25=PT(B7)-PT(F11),r3 - ;; - st8 [r24]=r18,16 /* b6 */ - st8 [r25]=r19,16 /* b7 */ - ;; - st8 [r24]=r9 /* ar.csd */ - st8 [r25]=r10 /* ar.ssd */ - ;; - srlz.d // make sure we see the effect of cr.ivr - movl r14=ia64_leave_nested - ;; - mov rp=r14 br.call.sptk.many b6=ia64_handle_irq - ;; END(vmx_interrupt) .org vmx_ia64_ivt+0x3400 @@ -1448,28 +1322,6 @@ ENTRY(vmx_dispatch_break_fault) ;; END(vmx_dispatch_break_fault) - -ENTRY(vmx_dispatch_interrupt) - VMX_SAVE_MIN_WITH_COVER_R19 // uses r31; defines r2 and r3 - ;; - alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group - mov out0=cr.ivr // pass cr.ivr as first arg - adds r3=8,r2 // set up second base pointer for SAVE_REST - ;; - ssm psr.ic - ;; - srlz.i - ;; - (p15) ssm psr.i - movl r14=ia64_leave_hypervisor - ;; - VMX_SAVE_REST - mov rp=r14 - ;; - add out1=16,sp // pass pointer to pt_regs as second arg - br.call.sptk.many b6=ia64_handle_irq -END(vmx_dispatch_interrupt) - .Lvmx_dispatch_reflection_string: .asciz "vmx_dispatch_reflection\n" .Lvmx_dispatch_virtualization_fault_string: diff -r b771d4cc5bf7 -r 5cad3e2ecec0 xen/arch/ia64/vmx/vmx_minstate.h --- a/xen/arch/ia64/vmx/vmx_minstate.h Thu Nov 22 12:38:07 2007 +0900 +++ b/xen/arch/ia64/vmx/vmx_minstate.h Mon Nov 26 16:27:32 2007 +0900 @@ -120,8 +120,7 @@ (p6) movl out0=panic_string; \ (p6) br.call.spnt.few b6=panic; -#define VMX_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \ - VMX_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \ +#define VMX_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA,VMX_PANIC) \ mov r27=ar.rsc; /* M */ \ mov r20=r1; /* A */ \ mov r25=ar.unat; /* M */ \ @@ -132,13 +131,13 @@ ;; \ cmp.eq p6,p0=r0,r0; \ tbit.z pKStk,pUStk=r29,IA64_PSR_VM_BIT; \ + tbit.z p0,p15=r29,IA64_PSR_I_BIT; \ ;; \ (pUStk) tbit.nz.and p6,p0=r18,IA64_ISR_NI_BIT; \ - ;; \ - P6_BR_VMX_PANIC \ - tbit.z p0,p15=r29,IA64_PSR_I_BIT; \ - mov r1=r16; \ - /* mov r21=r16; */ \ +(pUStk) VMX_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \ + ;; \ +(pUStk) mov r1=r16; \ + VMX_PANIC \ /* switch from user to kernel RBS: */ \ ;; \ invala; /* M */ \ @@ -152,9 +151,8 @@ st8 [r16]=r29; /* save cr.ipsr */ \ ;; \ lfetch.fault.excl.nt1 [r17]; \ - tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \ mov r29=b0 \ - ;; \ + ;; \ adds r16=PT(R8),r1; /* initialize first base pointer */ \ adds r17=PT(R9),r1; /* initialize second base pointer */ \ (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \ @@ -194,10 +192,12 @@ ;; \ .mem.offset 0,0; st8.spill [r16]=r13,16; \ .mem.offset 8,0; st8.spill [r17]=r10,16; /* save ar.fpsr */ \ - mov r13=r21; /* establish `current' */ \ +(pKStk) movl r13=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;/* from MINSTATE_GET_CURRENT */\ ;; \ .mem.offset 0,0; st8.spill [r16]=r15,16; \ .mem.offset 8,0; st8.spill [r17]=r14,16; \ +(pUStk) VMX_MINSTATE_GET_CURRENT(r13); /* establish `current' */ \ +(pKStk) ld8 r13=[r13]; /* establish `current' */ \ ;; \ .mem.offset 0,0; st8.spill [r16]=r2,16; \ .mem.offset 8,0; st8.spill [r17]=r3,16; \ @@ -283,10 +283,10 @@ st8 [r24]=r9; /* ar.csd */ \ st8 [r25]=r10; /* ar.ssd */ \ ;; \ - mov r18=ar.unat; \ - adds r19=PT(EML_UNAT)-PT(R4),r2; \ - ;; \ - st8 [r19]=r18; /* eml_unat */ +(pUStk)mov r18=ar.unat; \ +(pUStk)adds r19=PT(EML_UNAT)-PT(R4),r2; \ + ;; \ +(pUStk)st8 [r19]=r18; /* eml_unat */ #define VMX_SAVE_EXTRA \ .mem.offset 0,0; st8.spill [r2]=r4,16; \ @@ -299,8 +299,10 @@ ;; \ st8 [r2]=r26; /* eml_unat */ -#define VMX_SAVE_MIN_WITH_COVER VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,) -#define VMX_SAVE_MIN_WITH_COVER_R19 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19) +#define VMX_SAVE_MIN_WITH_COVER VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs,,) +#define VMX_SAVE_MIN_WITH_COVER_R19 VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19, P6_BR_VMX_PANIC) +#define VMX_SAVE_MIN_WITH_COVER_R19_NO_PANIC \ + VMX_DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19, ) #define VMX_SAVE_MIN VMX_DO_SAVE_MIN( , mov r30=r0, ) /*