This patch is some preliminary work for assigning a special RID for use
with EFI mappings. It sets up the assembly code portion of the appropriate
page fault handlers to identity map regions that are EFI memory
and have the EFI_RID set.
Background:
The basic idea of this approach is to switch to this RID, which is in the
range reserved for the hypervisor, before making EFI, PAL or SAL calls. The
page fault handler where the identity mapping checks for this RID, if
present it does the identity mapping, else it just follows the normal
mapping rules. In this way, VMX domains should not be able to access this
memory, and they should be able to use the virtual addresses that are used
by EFI for their own purposes.
Cc: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>
Cc: Tristan Gingold <tgingold@xxxxxxx>
Signed-off-by: Simon Horman <horms@xxxxxxxxxxxx>
Index: xen-unstable.hg/xen/arch/ia64/xen/ivt.S
===================================================================
--- xen-unstable.hg.orig/xen/arch/ia64/xen/ivt.S 2007-10-29
12:01:52.000000000 +0900
+++ xen-unstable.hg/xen/arch/ia64/xen/ivt.S 2007-10-29 13:35:39.000000000
+0900
@@ -57,6 +57,7 @@
#include <asm/thread_info.h>
#include <asm/unistd.h>
#include <xen/errno.h>
+#include <linux/efi.h>
#if 1
# define PSR_DEFAULT_BITS psr.ac
@@ -120,8 +121,79 @@ ENTRY(itlb_miss)
/* If address belongs to VMM, go to alt tlb handler */
cmp.eq p6,p0=0x1e,r17
(p6) br.cond.spnt late_alt_itlb_miss
- br.cond.sptk fast_tlb_miss_reflect
+
+ // If it is an EFI address then must have XEN_EFI_RID set
+ // And if that is true, go to alt tlb handler
+ // (r17 == 0x18 && rr[6] == XEN_EFI_RID) ||
+ // (r17 == 0x1c && rr[7] == XEN_EFI_RID)
+ mov r23=6
+ mov r24=7
+ ;;
+ mov r23=rr[r23]
+ mov r24=rr[r24]
+ ;;
+ mov r25=XEN_EFI_RID
+ cmp.eq p8,p0=0x18,r17 // 0xc...
+ cmp.eq p9,p0=0x1c,r17 // 0xe...
+ ;;
+ cmp.ne.and p8,p0=r25,r23 // rr[6] == XEN_EFI_RID
+ cmp.ne.and p9,p0=r25,r24 // rr[7] == XEN_EFI_RID
+ ;;
+(p8) br.cond.spnt fast_tlb_miss_reflect
+(p9) br.cond.spnt fast_tlb_miss_reflect
+
+ // EFI PAGE size is IA64_GRANULE_SIZE
+ // itir's key should be 0, as should the reserved space
+ // thus we can just set itir = (IA64_GRANULE_SHIFT << 2)
+ movl r20=IA64_GRANULE_SHIFT
+ ;;
+ shl r20=r20,2
+ ;;
+ mov cr.itir=r20
+ ;;
+ br.cond.sptk late_alt_itlb_miss
+
+#if 0
+ mov r21=cr.ipsr
+ ;;
+ extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
+ ;;
+ cmp.ne p8,p0=r0,r23 // psr.cpl != 0
+ ;;
+(p8) br.cond.spnt page_fault
+ ;;
+
+ // EFI PAGE size is IA64_GRANULE_SIZE
+ // itir's key should be 0, as should the reserved space
+ // thus we can just set itir = (IA64_GRANULE_SHIFT << 2)
+ movl r20=IA64_GRANULE_SHIFT
+ ;;
+ shl r20=r20,2
+ ;;
+ mov cr.itir=r20
+ ;;
+
+ movl r17=PAGE_KERNEL
+ movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
+ ;;
+ and r19=r19,r16 // clear ed, reserved bits, and PTE ctrl bits
;;
+ or r19=r17,r19 // insert PTE control bits into r19
+ ;;
+
+ cmp.ne p8,p0=r0,r18 // Xen UC bit set
+ ;;
+ cmp.eq.or p8,p0=0x18,r22 // Region 6 is UC for EFI
+ ;;
+(p8) dep r19=-1,r19,4,1 // set bit 4 (uncached) if access to UC area
+ ;;
+
+ itc.i r19 // insert the TLB entry
+ mov pr=r31,-1
+ rfi
+ ;;
+#endif
+
END(itlb_miss)
.org ia64_ivt+0x0800
@@ -137,6 +209,28 @@ ENTRY(dtlb_miss)
/* If address belongs to VMM, go to alt tlb handler */
cmp.eq p6,p0=0x1e,r17
(p6) br.cond.spnt late_alt_dtlb_miss
+
+ // If it is an EFI address then must have XEN_EFI_RID set
+ // And if that is true, go to alt tlb handler
+ // (r17 == 0x18 && rr[6] == XEN_EFI_RID) ||
+ // (r17 == 0x1c && rr[7] == XEN_EFI_RID)
+ mov r23=6
+ mov r24=7
+ ;;
+ mov r23=rr[r23]
+ mov r24=rr[r24]
+ ;;
+ mov r25=XEN_EFI_RID
+ cmp.eq p8,p0=0x18,r17 // 0xc...
+ cmp.eq p9,p0=0x1c,r17 // 0xe...
+ ;;
+ cmp.eq.and p8,p0=r25,r23 // rr[6] == XEN_EFI_RID
+ cmp.eq.and p9,p0=r25,r24 // rr[7] == XEN_EFI_RID
+ ;;
+(p8) br.cond.spnt late_alt_dtlb_miss
+(p9) br.cond.spnt late_alt_dtlb_miss
+ ;;
+
br.cond.sptk fast_tlb_miss_reflect
;;
END(dtlb_miss)
@@ -206,17 +300,39 @@ late_alt_dtlb_miss:
(p8) br.cond.sptk frametable_miss ;;
#endif
// If it is not a Xen address, handle it via page_fault.
+ // If it is not a Xen address, handle it via page_fault.
+ // !( ((r22 == 0x18 || r22 == 0x1c) && rr[6] == XEN_EFI_RID) ||
+ // r22 == 0x1e )
+ // Note that rr[6] == XEN_EFI_RID implies rr[7] == XEN_EFI_RID
extr.u r22=r16,59,5
;;
dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN // clear the key
- cmp.ne p8,p0=0x1e,r22
-(p8) br.cond.sptk page_fault
+ mov r23=6
+ ;;
+ mov r23=rr[r23]
+ ;;
+ mov r25=XEN_EFI_RID
+ cmp.eq p8,p0=0x18,r22 // 0xc...
;;
+ cmp.eq.or p8,p0=0x1c,r22 // 0xe...
+ ;;
+ cmp.eq.and p8,p0=r25,r23 // rr[6] == XEN_EFI_RID
+ ;;
+ cmp.eq.or p8,p0=0x1e,r22 // 0xf...
+ ;;
+(p8) br.cond.spnt alt_dtlb_miss_identity_map
+ br.cond.spnt page_fault
+ ;;
+alt_dtlb_miss_identity_map:
dep r21=-1,r21,IA64_PSR_ED_BIT,1
or r19=r19,r17 // insert PTE control bits into r19
mov cr.itir=r20 // set itir with cleared key
;;
- dep r19=r18,r19,4,1 // set bit 4 (uncached) if access to UC area
+ cmp.ne p8,p0=r0,r18 // Xen UC bit set
+ ;;
+ cmp.eq.or p8,p0=0x18,r22 // Region 6 is UC for EFI
+ ;;
+(p8) dep r19=-1,r19,4,1 // set bit 4 (uncached) if access to UC area
(p6) mov cr.ipsr=r21
;;
(p7) itc.d r19 // insert the TLB entry
--
--
Horms
H: http://www.vergenet.net/~horms/
W: http://www.valinux.co.jp/en/
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