VHPT speculative load happens in the same time when tlb_miss handler is
executing.
180 ld8 r25 = [r17]
181 ld8 r27 = [r18]
182 ld8 r29 = [r28]
183 dep r22 = -1,r24,63,1 //set ti=1
184 ;;
185 st8 [r16] = r29, VLE_ITIR_OFFSET - VLE_TITAG_OFFSET
186 st8 [r28] = r22, VLE_ITIR_OFFSET - VLE_TITAG_OFFSET
187 extr.u r19 = r27, 56, 4
188 mf
Mf is to make sure that before modifying vhpt entry, vhpt entry must be
disabled, otherwise VHPT walker hardware may see enabled half modified vhpt
entry(definitely wrong entry), and load it into TLB cache.
Notice
For example, Write2 is after write1,
Write2 may be visible before write1.
- Anthony
>-----Original Message-----
>From: tgingold@xxxxxxx [mailto:tgingold@xxxxxxx]
>Sent: 2007年10月9日 17:08
>To: Xu, Anthony
>Cc: Tristan Gingold; Xen-ia64-devel
>Subject: RE: [Xen-ia64-devel] Question about vmx_ivt.S
>
>Quoting "Xu, Anthony" <anthony.xu@xxxxxxxxx>:
>
>> Hi Tristan,
>>
>> Yes the mf is necessary,
>> Hardware can speculatively load vhpt entries from VTHP page.
>> We had spent a lot of effort to identity this issue.
>
>I don't fully understand your explanation. Memory ordering issues are only
>SMP issues, not uniprocessor issue. Am I wrong ?
>
>Tristan.
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