# HG changeset patch # User Tristan Gingold # Date 1190465395 -7200 # Node ID 109ef655c59186afe8ce6bd883f4268f47c4209f # Parent 09b45357e492d5e447ea11d1ab2627339cb5902a Add xenitp tool. Xenitp is a low-level debugger. Signed-off-by: Tristan Gingold diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/Makefile --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/Makefile Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,51 @@ +XEN_ROOT=../../.. +include $(XEN_ROOT)/tools/Rules.mk + +#CFLAGS += -Werror -g -O0 + +CFLAGS += -I $(XEN_XC) +CFLAGS += -I $(XEN_LIBXC) + +HDRS = $(wildcard *.h) +OBJS = $(patsubst %.c,%.o,$(wildcard *.c)) + +BIN = +LIBBIN = +SCRIPTS = +MAN1 = $(wildcard *.1) +MAN8 = $(wildcard *.8) + +ifeq ($(XEN_TARGET_ARCH),ia64) +LIBBIN += xenitp +endif + +.PHONY: all +all: build + +.PHONY: build +build: $(BIN) $(LIBBIN) + +.PHONY: install +install: build + [ -d $(DESTDIR)/usr/bin ] || $(INSTALL_DIR) $(DESTDIR)/usr/bin + [ -z "$(LIBBIN)" ] || [ -d $(DESTDIR)/usr/$(LIBDIR)/xen/bin ] || \ + $(INSTALL_DIR) $(DESTDIR)/usr/$(LIBDIR)/xen/bin + [ -d $(DESTDIR)/usr/share/man/man1 ] || \ + $(INSTALL_DIR) $(DESTDIR)/usr/share/man/man1 + [ -d $(DESTDIR)/usr/share/man/man8 ] || \ + $(INSTALL_DIR) $(DESTDIR)/usr/share/man/man8 + $(INSTALL_PROG) $(BIN) $(SCRIPTS) $(DESTDIR)/usr/bin + [ -z "$(LIBBIN)" ] || $(INSTALL_PROG) $(LIBBIN) $(DESTDIR)/usr/$(LIBDIR)/xen/bin + $(INSTALL_DATA) $(MAN1) $(DESTDIR)/usr/share/man/man1 + $(INSTALL_DATA) $(MAN8) $(DESTDIR)/usr/share/man/man8 + +.PHONY: clean +clean: + $(RM) *.a *.so *.o *.rpm $(BIN) $(LIBBIN) + +%: %.c $(HDRS) Makefile + $(CC) $(CFLAGS) -o $@ $< -L$(XEN_LIBXC) -lxenctrl + +XENITP_OBJS=xenitp.o ia64-dis.o ia64-opc.o cpu-ia64-opc.o +xenitp: $(XENITP_OBJS) + $(CC) $(CFLAGS) -o $@ $(XENITP_OBJS) -L$(XEN_LIBXC) -lxenctrl diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/README --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/README Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,36 @@ +xenitp README +************* + + +Xenitp is a low-level, non-symbolic debugger. It only works on ia64. + +* Building xenitp +First do 'make tools' at the top level to build libxc and includes. Then +cd to tools/debugger/xenitp and do make. + +* Using xenitp +Usage is: xenitp DOM +DOM is a domain number. +'help' shows all the command available. +When the domain is running, C-c stops it. + +* Source origin +All these files come from binutils: +cpu-ia64-opc.c +dis-asm.h +ia64-asmtab.c +ia64-asmtab.h +ia64-dis.c +ia64-gen.c +ia64.h +ia64-opc-a.c +ia64-opc-b.c +ia64-opc.c +ia64-opc-d.c +ia64-opc-f.c +ia64-opc.h +ia64-opc-i.c +ia64-opc-m.c +ia64-opc-x.c + +xenitp.c is based on xenctxt.c diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/cpu-ia64-opc.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/cpu-ia64-opc.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,615 @@ +/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Logically, this code should be part of libopcode but since some of + the operand insertion/extraction functions help bfd to implement + relocations, this code is included as part of cpu-ia64.c. This + avoids circular dependencies between libopcode and libbfd and also + obviates the need for applications to link in libopcode when all + they really want is libbfd. + + --davidm Mon Apr 13 22:14:02 1998 */ + +#include "ia64-opc.h" + +#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0]))) + +static const char* +ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED, + ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) +{ + return "internal error---this shouldn't happen"; +} + +static const char* +ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED, + ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) +{ + return "internal error---this shouldn't happen"; +} + +static const char* +ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED, + ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) +{ + return 0; +} + +static const char* +ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED, + ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) +{ + return 0; +} + +static const char* +ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + if (value >= 1u << self->field[0].bits) + return "register number out of range"; + + *code |= value << self->field[0].shift; + return 0; +} + +static const char* +ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + *valuep = ((code >> self->field[0].shift) + & ((1u << self->field[0].bits) - 1)); + return 0; +} + +static const char* +ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + ia64_insn new = 0; + int i; + + for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) + { + new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1)) + << self->field[i].shift); + value >>= self->field[i].bits; + } + if (value) + return "integer operand out of range"; + + *code |= new; + return 0; +} + +static const char* +ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + BFD_HOST_U_64_BIT value = 0; + int i, bits = 0, total = 0; + + for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) + { + bits = self->field[i].bits; + value |= ((code >> self->field[i].shift) + & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total; + total += bits; + } + *valuep = value; + return 0; +} + +static const char* +ins_immu5b (const struct ia64_operand *self, ia64_insn value, + ia64_insn *code) +{ + if (value < 32 || value > 63) + return "value must be between 32 and 63"; + return ins_immu (self, value - 32, code); +} + +static const char* +ext_immu5b (const struct ia64_operand *self, ia64_insn code, + ia64_insn *valuep) +{ + const char *result; + + result = ext_immu (self, code, valuep); + if (result) + return result; + + *valuep = *valuep + 32; + return 0; +} + +static const char* +ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + if (value & 0x7) + return "value not an integer multiple of 8"; + return ins_immu (self, value >> 3, code); +} + +static const char* +ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + const char *result; + + result = ext_immu (self, code, valuep); + if (result) + return result; + + *valuep = *valuep << 3; + return 0; +} + +static const char* +ins_imms_scaled (const struct ia64_operand *self, ia64_insn value, + ia64_insn *code, int scale) +{ + BFD_HOST_64_BIT svalue = value, sign_bit = 0; + ia64_insn new = 0; + int i; + + svalue >>= scale; + + for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) + { + new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1)) + << self->field[i].shift); + sign_bit = (svalue >> (self->field[i].bits - 1)) & 1; + svalue >>= self->field[i].bits; + } + if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1)) + return "integer operand out of range"; + + *code |= new; + return 0; +} + +static const char* +ext_imms_scaled (const struct ia64_operand *self, ia64_insn code, + ia64_insn *valuep, int scale) +{ + int i, bits = 0, total = 0; + BFD_HOST_64_BIT val = 0, sign; + + for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) + { + bits = self->field[i].bits; + val |= ((code >> self->field[i].shift) + & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total; + total += bits; + } + /* sign extend: */ + sign = (BFD_HOST_64_BIT) 1 << (total - 1); + val = (val ^ sign) - sign; + + *valuep = (val << scale); + return 0; +} + +static const char* +ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + return ins_imms_scaled (self, value, code, 0); +} + +static const char* +ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; + + return ins_imms_scaled (self, value, code, 0); +} + +static const char* +ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + return ext_imms_scaled (self, code, valuep, 0); +} + +static const char* +ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + --value; + return ins_imms_scaled (self, value, code, 0); +} + +static const char* +ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value, + ia64_insn *code) +{ + value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; + + --value; + return ins_imms_scaled (self, value, code, 0); +} + +static const char* +ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + const char *res = ext_imms_scaled (self, code, valuep, 0); + + ++*valuep; + return res; +} + +static const char* +ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + return ins_imms_scaled (self, value, code, 1); +} + +static const char* +ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + return ext_imms_scaled (self, code, valuep, 1); +} + +static const char* +ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + return ins_imms_scaled (self, value, code, 4); +} + +static const char* +ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + return ext_imms_scaled (self, code, valuep, 4); +} + +static const char* +ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + return ins_imms_scaled (self, value, code, 16); +} + +static const char* +ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + return ext_imms_scaled (self, code, valuep, 16); +} + +static const char* +ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1; + return ins_immu (self, value ^ mask, code); +} + +static const char* +ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + const char *result; + ia64_insn mask; + + mask = (((ia64_insn) 1) << self->field[0].bits) - 1; + result = ext_immu (self, code, valuep); + if (!result) + { + mask = (((ia64_insn) 1) << self->field[0].bits) - 1; + *valuep ^= mask; + } + return result; +} + +static const char* +ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + --value; + if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) + return "count out of range"; + + *code |= value << self->field[0].shift; + return 0; +} + +static const char* +ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + *valuep = ((code >> self->field[0].shift) + & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1; + return 0; +} + +static const char* +ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + --value; + + if (value > 2) + return "count must be in range 1..3"; + + *code |= value << self->field[0].shift; + return 0; +} + +static const char* +ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + *valuep = ((code >> self->field[0].shift) & 0x3) + 1; + return 0; +} + +static const char* +ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + switch (value) + { + case 0: value = 0; break; + case 7: value = 1; break; + case 15: value = 2; break; + case 16: value = 3; break; + default: return "count must be 0, 7, 15, or 16"; + } + *code |= value << self->field[0].shift; + return 0; +} + +static const char* +ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + ia64_insn value; + + value = (code >> self->field[0].shift) & 0x3; + switch (value) + { + case 0: value = 0; break; + case 1: value = 7; break; + case 2: value = 15; break; + case 3: value = 16; break; + } + *valuep = value; + return 0; +} + +static const char* +ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) +{ + BFD_HOST_64_BIT val = value; + BFD_HOST_U_64_BIT sign = 0; + + if (val < 0) + { + sign = 0x4; + value = -value; + } + switch (value) + { + case 1: value = 3; break; + case 4: value = 2; break; + case 8: value = 1; break; + case 16: value = 0; break; + default: return "count must be +/- 1, 4, 8, or 16"; + } + *code |= (sign | value) << self->field[0].shift; + return 0; +} + +static const char* +ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) +{ + BFD_HOST_64_BIT val; + int negate; + + val = (code >> self->field[0].shift) & 0x7; + negate = val & 0x4; + switch (val & 0x3) + { + case 0: val = 16; break; + case 1: val = 8; break; + case 2: val = 4; break; + case 3: val = 1; break; + } + if (negate) + val = -val; + + *valuep = val; + return 0; +} + +#define CST IA64_OPND_CLASS_CST +#define REG IA64_OPND_CLASS_REG +#define IND IA64_OPND_CLASS_IND +#define ABS IA64_OPND_CLASS_ABS +#define REL IA64_OPND_CLASS_REL + +#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED +#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED + +const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] = + { + /* constants: */ + { CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "" }, + { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" }, + { CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" }, + { CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" }, + { CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" }, + { CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" }, + { CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" }, + { CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" }, + { CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" }, + { CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" }, + { CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" }, + { CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" }, + { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" }, + { CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" }, + + /* register operands: */ + { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */ + "an application register" }, + { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */ + "a branch register" }, + { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */ + "a branch register"}, + { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */ + "a control register"}, + { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */ + "a floating-point register" }, + { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */ + "a floating-point register" }, + { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */ + "a floating-point register" }, + { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */ + "a floating-point register" }, + { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */ + "a predicate register" }, + { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */ + "a predicate register" }, + { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */ + "a general register" }, + { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */ + "a general register" }, + { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */ + "a general register" }, + { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */ + "a general register r0-r3" }, + + /* memory operands: */ + { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */ + "a memory address" }, + + /* indirect operands: */ + { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */ + "a cpuid register" }, + { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */ + "a dbr register" }, + { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */ + "a dtr register" }, + { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */ + "an itr register" }, + { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */ + "an ibr register" }, + { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */ + "an msr register" }, + { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */ + "a pkr register" }, + { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */ + "a pmc register" }, + { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */ + "a pmd register" }, + { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */ + "an rr register" }, + + /* immediate operands: */ + { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */ + "a 5-bit count (0-31)" }, + { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */ + "a 2-bit count (1-4)" }, + { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */ + "a 2-bit count (1-3)" }, + { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */ + "a count (0, 7, 15, or 16)" }, + { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */ + "a 5-bit count (0-31)" }, + { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */ + "a 6-bit count (0-63)" }, + { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */ + "a 6-bit bit pos (0-63)" }, + { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */ + "a 6-bit bit pos (0-63)" }, + { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */ + "a 6-bit bit pos (0-63)" }, + { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */ + "a 1-bit integer (-1, 0)" }, + { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */ + "a 2-bit unsigned (0-3)" }, + { ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */ + "a 5-bit unsigned (32 + (0-31))" }, + { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */ + "a 7-bit unsigned (0-127)" }, + { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */ + "a 7-bit unsigned (0-127)" }, + { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */ + "a frame size (register count)" }, + { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */ + "a local register count" }, + { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */ + "a rotating register count (integer multiple of 8)" }, + { ABS, ins_imms, ext_imms, 0, /* IMM8 */ + {{ 7, 13}, { 1, 36}}, SDEC, + "an 8-bit integer (-128-127)" }, + { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */ + {{ 7, 13}, { 1, 36}}, SDEC, + "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" }, + { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */ + {{ 7, 13}, { 1, 36}}, SDEC, + "an 8-bit integer (-127-128)" }, + { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */ + {{ 7, 13}, { 1, 36}}, SDEC, + "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" }, + { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */ + {{ 7, 13}, { 1, 36}}, SDEC, + "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" }, + { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */ + "a 9-bit unsigned (0-511)" }, + { ABS, ins_imms, ext_imms, 0, /* IMM9a */ + {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC, + "a 9-bit integer (-256-255)" }, + { ABS, ins_imms, ext_imms, 0, /* IMM9b */ + {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC, + "a 9-bit integer (-256-255)" }, + { ABS, ins_imms, ext_imms, 0, /* IMM14 */ + {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC, + "a 14-bit integer (-8192-8191)" }, + { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */ + {{ 7, 6}, { 8, 24}, { 1, 36}}, 0, + "a 17-bit integer (-65536-65535)" }, + { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */ + "a 21-bit unsigned" }, + { ABS, ins_imms, ext_imms, 0, /* IMM22 */ + {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC, + "a 22-bit signed integer" }, + { ABS, ins_immu, ext_immu, 0, /* IMMU24 */ + {{21, 6}, { 2, 31}, { 1, 36}}, 0, + "a 24-bit unsigned" }, + { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */ + "a 44-bit unsigned (least 16 bits ignored/zeroes)" }, + { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */ + "a 62-bit unsigned" }, + { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */ + "a 64-bit unsigned" }, + { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */ + "an increment (+/- 1, 4, 8, or 16)" }, + { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */ + "a 4-bit length (1-16)" }, + { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */ + "a 6-bit length (1-64)" }, + { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */ + "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" }, + { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */ + "an 8-bit mix type" }, + { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */ + "a 6-bit bit pos (0-63)" }, + { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */ + "a branch tag" }, + { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */ + "a branch tag" }, + { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */ + "a branch target" }, + { REL, ins_imms4, ext_imms4, 0, /* TGT25b */ + {{ 7, 6}, {13, 20}, { 1, 36}}, 0, + "a branch target" }, + { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */ + "a branch target" }, + { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ + "a branch target" }, + + { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */ + "ldxmov target" }, + }; diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/dis-asm.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/dis-asm.h Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,548 @@ +/* Interface between the opcode library and its callers. + + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. + + Written by Cygnus Support, 1993. + + The opcode library (libopcodes.a) provides instruction decoders for + a large variety of instruction sets, callable with an identical + interface, for making instruction-processing programs more independent + of the instruction set being processed. */ + +#ifndef DIS_ASM_H +#define DIS_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +#define PARAMS(x) x +typedef void *PTR; +typedef uint64_t bfd_vma; +typedef int64_t bfd_signed_vma; +typedef uint8_t bfd_byte; +typedef int bfd_boolean; +#define BFD_HOST_U_64_BIT unsigned long +#define BFD_HOST_64_BIT long +#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x) + +extern unsigned long bfd_getl64 (const bfd_byte *addr); + +#define BFD64 +#define ATTRIBUTE_FPTR_PRINTF_2 +#define ATTRIBUTE_UNUSED __attribute__((unused)) + +enum bfd_flavour { + bfd_target_unknown_flavour, + bfd_target_aout_flavour, + bfd_target_coff_flavour, + bfd_target_ecoff_flavour, + bfd_target_elf_flavour, + bfd_target_ieee_flavour, + bfd_target_nlm_flavour, + bfd_target_oasys_flavour, + bfd_target_tekhex_flavour, + bfd_target_srec_flavour, + bfd_target_ihex_flavour, + bfd_target_som_flavour, + bfd_target_os9k_flavour, + bfd_target_versados_flavour, + bfd_target_msdos_flavour, + bfd_target_evax_flavour +}; + +enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN }; + +enum bfd_architecture +{ + bfd_arch_unknown, /* File arch not known */ + bfd_arch_obscure, /* Arch known, not one of these */ + bfd_arch_m68k, /* Motorola 68xxx */ +#define bfd_mach_m68000 1 +#define bfd_mach_m68008 2 +#define bfd_mach_m68010 3 +#define bfd_mach_m68020 4 +#define bfd_mach_m68030 5 +#define bfd_mach_m68040 6 +#define bfd_mach_m68060 7 +#define bfd_mach_cpu32 8 +#define bfd_mach_mcf5200 9 +#define bfd_mach_mcf5206e 10 +#define bfd_mach_mcf5307 11 +#define bfd_mach_mcf5407 12 +#define bfd_mach_mcf528x 13 +#define bfd_mach_mcfv4e 14 +#define bfd_mach_mcf521x 15 +#define bfd_mach_mcf5249 16 +#define bfd_mach_mcf547x 17 +#define bfd_mach_mcf548x 18 + bfd_arch_vax, /* DEC Vax */ + bfd_arch_i960, /* Intel 960 */ + /* The order of the following is important. + lower number indicates a machine type that + only accepts a subset of the instructions + available to machines with higher numbers. + The exception is the "ca", which is + incompatible with all other machines except + "core". */ + +#define bfd_mach_i960_core 1 +#define bfd_mach_i960_ka_sa 2 +#define bfd_mach_i960_kb_sb 3 +#define bfd_mach_i960_mc 4 +#define bfd_mach_i960_xa 5 +#define bfd_mach_i960_ca 6 +#define bfd_mach_i960_jx 7 +#define bfd_mach_i960_hx 8 + + bfd_arch_a29k, /* AMD 29000 */ + bfd_arch_sparc, /* SPARC */ +#define bfd_mach_sparc 1 +/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */ +#define bfd_mach_sparc_sparclet 2 +#define bfd_mach_sparc_sparclite 3 +#define bfd_mach_sparc_v8plus 4 +#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */ +#define bfd_mach_sparc_sparclite_le 6 +#define bfd_mach_sparc_v9 7 +#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */ +#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */ +#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */ +/* Nonzero if MACH has the v9 instruction set. */ +#define bfd_mach_sparc_v9_p(mach) \ + ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \ + && (mach) != bfd_mach_sparc_sparclite_le) + bfd_arch_mips, /* MIPS Rxxxx */ +#define bfd_mach_mips3000 3000 +#define bfd_mach_mips3900 3900 +#define bfd_mach_mips4000 4000 +#define bfd_mach_mips4010 4010 +#define bfd_mach_mips4100 4100 +#define bfd_mach_mips4300 4300 +#define bfd_mach_mips4400 4400 +#define bfd_mach_mips4600 4600 +#define bfd_mach_mips4650 4650 +#define bfd_mach_mips5000 5000 +#define bfd_mach_mips6000 6000 +#define bfd_mach_mips8000 8000 +#define bfd_mach_mips10000 10000 +#define bfd_mach_mips16 16 + bfd_arch_i386, /* Intel 386 */ +#define bfd_mach_i386_i386 0 +#define bfd_mach_i386_i8086 1 +#define bfd_mach_i386_i386_intel_syntax 2 +#define bfd_mach_x86_64 3 +#define bfd_mach_x86_64_intel_syntax 4 + bfd_arch_we32k, /* AT&T WE32xxx */ + bfd_arch_tahoe, /* CCI/Harris Tahoe */ + bfd_arch_i860, /* Intel 860 */ + bfd_arch_romp, /* IBM ROMP PC/RT */ + bfd_arch_alliant, /* Alliant */ + bfd_arch_convex, /* Convex */ + bfd_arch_m88k, /* Motorola 88xxx */ + bfd_arch_pyramid, /* Pyramid Technology */ + bfd_arch_h8300, /* Hitachi H8/300 */ +#define bfd_mach_h8300 1 +#define bfd_mach_h8300h 2 +#define bfd_mach_h8300s 3 + bfd_arch_powerpc, /* PowerPC */ +#define bfd_mach_ppc 0 +#define bfd_mach_ppc64 1 +#define bfd_mach_ppc_403 403 +#define bfd_mach_ppc_403gc 4030 +#define bfd_mach_ppc_505 505 +#define bfd_mach_ppc_601 601 +#define bfd_mach_ppc_602 602 +#define bfd_mach_ppc_603 603 +#define bfd_mach_ppc_ec603e 6031 +#define bfd_mach_ppc_604 604 +#define bfd_mach_ppc_620 620 +#define bfd_mach_ppc_630 630 +#define bfd_mach_ppc_750 750 +#define bfd_mach_ppc_860 860 +#define bfd_mach_ppc_a35 35 +#define bfd_mach_ppc_rs64ii 642 +#define bfd_mach_ppc_rs64iii 643 +#define bfd_mach_ppc_7400 7400 + bfd_arch_rs6000, /* IBM RS/6000 */ + bfd_arch_hppa, /* HP PA RISC */ + bfd_arch_d10v, /* Mitsubishi D10V */ + bfd_arch_z8k, /* Zilog Z8000 */ +#define bfd_mach_z8001 1 +#define bfd_mach_z8002 2 + bfd_arch_h8500, /* Hitachi H8/500 */ + bfd_arch_sh, /* Hitachi SH */ +#define bfd_mach_sh 1 +#define bfd_mach_sh2 0x20 +#define bfd_mach_sh_dsp 0x2d +#define bfd_mach_sh2a 0x2a +#define bfd_mach_sh2a_nofpu 0x2b +#define bfd_mach_sh2e 0x2e +#define bfd_mach_sh3 0x30 +#define bfd_mach_sh3_nommu 0x31 +#define bfd_mach_sh3_dsp 0x3d +#define bfd_mach_sh3e 0x3e +#define bfd_mach_sh4 0x40 +#define bfd_mach_sh4_nofpu 0x41 +#define bfd_mach_sh4_nommu_nofpu 0x42 +#define bfd_mach_sh4a 0x4a +#define bfd_mach_sh4a_nofpu 0x4b +#define bfd_mach_sh4al_dsp 0x4d +#define bfd_mach_sh5 0x50 + bfd_arch_alpha, /* Dec Alpha */ +#define bfd_mach_alpha 1 + bfd_arch_arm, /* Advanced Risc Machines ARM */ +#define bfd_mach_arm_2 1 +#define bfd_mach_arm_2a 2 +#define bfd_mach_arm_3 3 +#define bfd_mach_arm_3M 4 +#define bfd_mach_arm_4 5 +#define bfd_mach_arm_4T 6 + bfd_arch_ns32k, /* National Semiconductors ns32000 */ + bfd_arch_w65, /* WDC 65816 */ + bfd_arch_tic30, /* Texas Instruments TMS320C30 */ + bfd_arch_v850, /* NEC V850 */ +#define bfd_mach_v850 0 + bfd_arch_arc, /* Argonaut RISC Core */ +#define bfd_mach_arc_base 0 + bfd_arch_m32r, /* Mitsubishi M32R/D */ +#define bfd_mach_m32r 0 /* backwards compatibility */ + bfd_arch_mn10200, /* Matsushita MN10200 */ + bfd_arch_mn10300, /* Matsushita MN10300 */ + bfd_arch_last + }; + +typedef struct symbol_cache_entry +{ + const char *name; + union + { + PTR p; + bfd_vma i; + } udata; +} asymbol; + +typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2; + +enum dis_insn_type { + dis_noninsn, /* Not a valid instruction */ + dis_nonbranch, /* Not a branch instruction */ + dis_branch, /* Unconditional branch */ + dis_condbranch, /* Conditional branch */ + dis_jsr, /* Jump to subroutine */ + dis_condjsr, /* Conditional jump to subroutine */ + dis_dref, /* Data reference instruction */ + dis_dref2 /* Two data references in instruction */ +}; + +/* This struct is passed into the instruction decoding routine, + and is passed back out into each callback. The various fields are used + for conveying information from your main routine into your callbacks, + for passing information into the instruction decoders (such as the + addresses of the callback functions), or for passing information + back from the instruction decoders to their callers. + + It must be initialized before it is first passed; this can be done + by hand, or using one of the initialization macros below. */ + +typedef struct disassemble_info { + fprintf_ftype fprintf_func; + void *stream; + void *application_data; + + /* Target description. We could replace this with a pointer to the bfd, + but that would require one. There currently isn't any such requirement + so to avoid introducing one we record these explicitly. */ + /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ + enum bfd_flavour flavour; + /* The bfd_arch value. */ + enum bfd_architecture arch; + /* The bfd_mach value. */ + unsigned long mach; + /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ + enum bfd_endian endian; + /* An arch/mach-specific bitmask of selected instruction subsets, mainly + for processors with run-time-switchable instruction sets. The default, + zero, means that there is no constraint. CGEN-based opcodes ports + may use ISA_foo masks. */ + void *insn_sets; + + /* Some targets need information about the current section to accurately + display insns. If this is NULL, the target disassembler function + will have to make its best guess. */ + //asection *section; + + /* An array of pointers to symbols either at the location being disassembled + or at the start of the function being disassembled. The array is sorted + so that the first symbol is intended to be the one used. The others are + present for any misc. purposes. This is not set reliably, but if it is + not NULL, it is correct. */ + asymbol **symbols; + /* Number of symbols in array. */ + int num_symbols; + + /* For use by the disassembler. + The top 16 bits are reserved for public use (and are documented here). + The bottom 16 bits are for the internal use of the disassembler. */ + unsigned long flags; +#define INSN_HAS_RELOC 0x80000000 + void *private_data; + + /* Function used to get bytes to disassemble. MEMADDR is the + address of the stuff to be disassembled, MYADDR is the address to + put the bytes in, and LENGTH is the number of bytes to read. + INFO is a pointer to this struct. + Returns an errno value or 0 for success. */ + int (*read_memory_func) + (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, + struct disassemble_info *info); + + /* Function which should be called if we get an error that we can't + recover from. STATUS is the errno value from read_memory_func and + MEMADDR is the address that we were trying to read. INFO is a + pointer to this struct. */ + void (*memory_error_func) + (int status, bfd_vma memaddr, struct disassemble_info *info); + + /* Function called to print ADDR. */ + void (*print_address_func) + (bfd_vma addr, struct disassemble_info *info); + + /* Function called to determine if there is a symbol at the given ADDR. + If there is, the function returns 1, otherwise it returns 0. + This is used by ports which support an overlay manager where + the overlay number is held in the top part of an address. In + some circumstances we want to include the overlay number in the + address, (normally because there is a symbol associated with + that address), but sometimes we want to mask out the overlay bits. */ + int (* symbol_at_address_func) + (bfd_vma addr, struct disassemble_info * info); + + /* Function called to check if a SYMBOL is can be displayed to the user. + This is used by some ports that want to hide special symbols when + displaying debugging outout. */ + bfd_boolean (* symbol_is_valid) + (asymbol *, struct disassemble_info * info); + + /* These are for buffer_read_memory. */ + bfd_byte *buffer; + bfd_vma buffer_vma; + unsigned int buffer_length; + + /* This variable may be set by the instruction decoder. It suggests + the number of bytes objdump should display on a single line. If + the instruction decoder sets this, it should always set it to + the same value in order to get reasonable looking output. */ + int bytes_per_line; + + /* The next two variables control the way objdump displays the raw data. */ + /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ + /* output will look like this: + 00: 00000000 00000000 + with the chunks displayed according to "display_endian". */ + int bytes_per_chunk; + enum bfd_endian display_endian; + + /* Number of octets per incremented target address + Normally one, but some DSPs have byte sizes of 16 or 32 bits. */ + unsigned int octets_per_byte; + + /* The number of zeroes we want to see at the end of a section before we + start skipping them. */ + unsigned int skip_zeroes; + + /* The number of zeroes to skip at the end of a section. If the number + of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES, + they will be disassembled. If there are fewer than + SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic + attempt to avoid disassembling zeroes inserted by section + alignment. */ + unsigned int skip_zeroes_at_end; + + /* Whether the disassembler always needs the relocations. */ + bfd_boolean disassembler_needs_relocs; + + /* Results from instruction decoders. Not all decoders yet support + this information. This info is set each time an instruction is + decoded, and is only valid for the last such instruction. + + To determine whether this decoder supports this information, set + insn_info_valid to 0, decode an instruction, then check it. */ + + char insn_info_valid; /* Branch info has been set. */ + char branch_delay_insns; /* How many sequential insn's will run before + a branch takes effect. (0 = normal) */ + char data_size; /* Size of data reference in insn, in bytes */ + enum dis_insn_type insn_type; /* Type of instruction */ + bfd_vma target; /* Target address of branch or dref, if known; + zero if unknown. */ + bfd_vma target2; /* Second target address for dref2 */ + + /* Command line options specific to the target disassembler. */ + char * disassembler_options; + +} disassemble_info; + + +/* Standard disassemblers. Disassemble one instruction at the given + target address. Return number of octets processed. */ +typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); + +extern int print_insn_big_mips (bfd_vma, disassemble_info *); +extern int print_insn_little_mips (bfd_vma, disassemble_info *); +extern int print_insn_i386 (bfd_vma, disassemble_info *); +extern int print_insn_i386_att (bfd_vma, disassemble_info *); +extern int print_insn_i386_intel (bfd_vma, disassemble_info *); +extern int print_insn_ia64 (bfd_vma, disassemble_info *); +extern int print_insn_i370 (bfd_vma, disassemble_info *); +extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); +extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); +extern int print_insn_m68k (bfd_vma, disassemble_info *); +extern int print_insn_z80 (bfd_vma, disassemble_info *); +extern int print_insn_z8001 (bfd_vma, disassemble_info *); +extern int print_insn_z8002 (bfd_vma, disassemble_info *); +extern int print_insn_h8300 (bfd_vma, disassemble_info *); +extern int print_insn_h8300h (bfd_vma, disassemble_info *); +extern int print_insn_h8300s (bfd_vma, disassemble_info *); +extern int print_insn_h8500 (bfd_vma, disassemble_info *); +extern int print_insn_alpha (bfd_vma, disassemble_info *); +extern int print_insn_big_arm (bfd_vma, disassemble_info *); +extern int print_insn_little_arm (bfd_vma, disassemble_info *); +extern int print_insn_sparc (bfd_vma, disassemble_info *); +extern int print_insn_avr (bfd_vma, disassemble_info *); +extern int print_insn_bfin (bfd_vma, disassemble_info *); +extern int print_insn_d10v (bfd_vma, disassemble_info *); +extern int print_insn_d30v (bfd_vma, disassemble_info *); +extern int print_insn_dlx (bfd_vma, disassemble_info *); +extern int print_insn_fr30 (bfd_vma, disassemble_info *); +extern int print_insn_hppa (bfd_vma, disassemble_info *); +extern int print_insn_i860 (bfd_vma, disassemble_info *); +extern int print_insn_i960 (bfd_vma, disassemble_info *); +extern int print_insn_ip2k (bfd_vma, disassemble_info *); +extern int print_insn_m32r (bfd_vma, disassemble_info *); +extern int print_insn_m88k (bfd_vma, disassemble_info *); +extern int print_insn_maxq_little (bfd_vma, disassemble_info *); +extern int print_insn_maxq_big (bfd_vma, disassemble_info *); +extern int print_insn_mcore (bfd_vma, disassemble_info *); +extern int print_insn_mmix (bfd_vma, disassemble_info *); +extern int print_insn_mn10200 (bfd_vma, disassemble_info *); +extern int print_insn_mn10300 (bfd_vma, disassemble_info *); +extern int print_insn_mt (bfd_vma, disassemble_info *); +extern int print_insn_msp430 (bfd_vma, disassemble_info *); +extern int print_insn_ns32k (bfd_vma, disassemble_info *); +extern int print_insn_crx (bfd_vma, disassemble_info *); +extern int print_insn_openrisc (bfd_vma, disassemble_info *); +extern int print_insn_big_or32 (bfd_vma, disassemble_info *); +extern int print_insn_little_or32 (bfd_vma, disassemble_info *); +extern int print_insn_pdp11 (bfd_vma, disassemble_info *); +extern int print_insn_pj (bfd_vma, disassemble_info *); +extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_rs6000 (bfd_vma, disassemble_info *); +extern int print_insn_s390 (bfd_vma, disassemble_info *); +extern int print_insn_sh (bfd_vma, disassemble_info *); +extern int print_insn_tic30 (bfd_vma, disassemble_info *); +extern int print_insn_tic4x (bfd_vma, disassemble_info *); +extern int print_insn_tic54x (bfd_vma, disassemble_info *); +extern int print_insn_tic80 (bfd_vma, disassemble_info *); +extern int print_insn_v850 (bfd_vma, disassemble_info *); +extern int print_insn_vax (bfd_vma, disassemble_info *); +extern int print_insn_w65 (bfd_vma, disassemble_info *); +extern int print_insn_xstormy16 (bfd_vma, disassemble_info *); +extern int print_insn_xtensa (bfd_vma, disassemble_info *); +extern int print_insn_sh64 (bfd_vma, disassemble_info *); +extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); +extern int print_insn_frv (bfd_vma, disassemble_info *); +extern int print_insn_iq2000 (bfd_vma, disassemble_info *); +extern int print_insn_xc16x (bfd_vma, disassemble_info *); +extern int print_insn_m32c (bfd_vma, disassemble_info *); + +extern disassembler_ftype arc_get_disassembler (void *); +//extern disassembler_ftype cris_get_disassembler (bfd *); + +extern void print_mips_disassembler_options (FILE *); +extern void print_ppc_disassembler_options (FILE *); +extern void print_arm_disassembler_options (FILE *); +extern void parse_arm_disassembler_option (char *); +extern int get_arm_regname_num_options (void); +extern int set_arm_regname_option (int); +extern int get_arm_regnames (int, const char **, const char **, const char *const **); +extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); + +/* Fetch the disassembler for a given BFD, if that support is available. */ +//extern disassembler_ftype disassembler (bfd *); + +/* Amend the disassemble_info structure as necessary for the target architecture. + Should only be called after initialising the info->arch field. */ +extern void disassemble_init_for_target (struct disassemble_info * info); + +/* Document any target specific options available from the disassembler. */ +extern void disassembler_usage (FILE *); + + +/* This block of definitions is for particular callers who read instructions + into a buffer before calling the instruction decoder. */ + +/* Here is a function which callers may wish to use for read_memory_func. + It gets bytes from a buffer. */ +extern int buffer_read_memory + (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *); + +/* This function goes with buffer_read_memory. + It prints a message using info->fprintf_func and info->stream. */ +extern void perror_memory (int, bfd_vma, struct disassemble_info *); + + +/* Just print the address in hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ +extern void generic_print_address + (bfd_vma, struct disassemble_info *); + +/* Always true. */ +extern int generic_symbol_at_address + (bfd_vma, struct disassemble_info *); + +/* Also always true. */ +extern bfd_boolean generic_symbol_is_valid + (asymbol *, struct disassemble_info *); + +/* Method to initialize a disassemble_info struct. This should be + called by all applications creating such a struct. */ +extern void init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func); + +/* For compatibility with existing code. */ +#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) +#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) + + +#ifdef __cplusplus +} +#endif + +#endif /* ! defined (DIS_ASM_H) */ diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-asmtab.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-asmtab.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,8774 @@ +/* This file is automatically generated by ia64-gen. Do not edit! */ +static const char * const ia64_strings[] = { + "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", + "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", + "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16", + "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", + "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", + "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", + "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", + "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", + "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", + "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", + "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", + "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", + "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", + "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia", + "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8", + "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le", + "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many", + "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", + "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", + "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1", + "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1", + "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", + "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", + "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", + "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", + "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig", + "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2", + "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1", + "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa", + "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4", + "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2", + "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", + "zxt4", +}; + +static const struct ia64_dependency +dependencies[] = { + { "ALAT", 0, 0, 0, -1, NULL, }, + { "AR[BSP]", 26, 0, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, + { "AR[CCV]", 26, 0, 2, 32, NULL, }, + { "AR[CFLG]", 26, 0, 2, 27, NULL, }, + { "AR[CSD]", 26, 0, 2, 25, NULL, }, + { "AR[EC]", 26, 0, 2, 66, NULL, }, + { "AR[EFLAG]", 26, 0, 2, 24, NULL, }, + { "AR[FCR]", 26, 0, 2, 21, NULL, }, + { "AR[FDR]", 26, 0, 2, 30, NULL, }, + { "AR[FIR]", 26, 0, 2, 29, NULL, }, + { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, + { "AR[FSR]", 26, 0, 2, 28, NULL, }, + { "AR[ITC]", 26, 0, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, + { "AR[LC]", 26, 0, 2, 65, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 0, 64, NULL, }, + { "AR[RNAT]", 26, 0, 2, 19, NULL, }, + { "AR[RSC]", 26, 0, 2, 16, NULL, }, + { "AR[SSD]", 26, 0, 2, 26, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, + { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 0, -1, NULL, }, + { "CPUID#", 7, 0, 5, -1, NULL, }, + { "CR[CMCV]", 27, 0, 3, 74, NULL, }, + { "CR[DCR]", 27, 0, 3, 0, NULL, }, + { "CR[EOI]", 27, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", }, + { "CR[GPTA]", 27, 0, 3, 9, NULL, }, + { "CR[IFA]", 27, 0, 1, 20, NULL, }, + { "CR[IFA]", 27, 0, 3, 20, NULL, }, + { "CR[IFS]", 27, 0, 3, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IHA]", 27, 0, 3, 25, NULL, }, + { "CR[IIM]", 27, 0, 3, 24, NULL, }, + { "CR[IIP]", 27, 0, 3, 19, NULL, }, + { "CR[IIP]", 27, 0, 1, 19, NULL, }, + { "CR[IIPA]", 27, 0, 3, 22, NULL, }, + { "CR[IPSR]", 27, 0, 3, 16, NULL, }, + { "CR[IPSR]", 27, 0, 1, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, }, + { "CR[ISR]", 27, 0, 3, 17, NULL, }, + { "CR[ITIR]", 27, 0, 3, 21, NULL, }, + { "CR[ITIR]", 27, 0, 1, 21, NULL, }, + { "CR[ITM]", 27, 0, 3, 1, NULL, }, + { "CR[ITV]", 27, 0, 3, 72, NULL, }, + { "CR[IVA]", 27, 0, 4, 2, NULL, }, + { "CR[IVR]", 27, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR Ð CR65)\" on page 2:118", }, + { "CR[LID]", 27, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID Ð CR64)\" on page 2:117", }, + { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, }, + { "CR[PMV]", 27, 0, 3, 73, NULL, }, + { "CR[PTA]", 27, 0, 3, 8, NULL, }, + { "CR[TPR]", 27, 0, 3, 66, NULL, }, + { "CR[TPR]", 27, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR Ð CR66)\" on page 2:119", }, + { "CR[TPR]", 27, 0, 1, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, }, + { "DBR#", 11, 0, 2, -1, NULL, }, + { "DBR#", 11, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC", 0, 0, 0, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 0, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, }, + { "GR0", 14, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, }, + { "IBR#", 16, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 3, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "IP", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 0, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "memory", 0, 0, 0, -1, NULL, }, + { "MSR#", 18, 0, 5, -1, NULL, }, + { "PKR#", 19, 0, 3, -1, NULL, }, + { "PKR#", 19, 0, 0, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", }, + { "PMD#", 21, 0, 2, -1, NULL, }, + { "PR0", 0, 0, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 0, -1, NULL, }, + { "PSR.ac", 28, 0, 1, 3, NULL, }, + { "PSR.ac", 28, 0, 3, 3, NULL, }, + { "PSR.ac", 28, 0, 2, 3, NULL, }, + { "PSR.ac", 28, 0, 2, 3, NULL, }, + { "PSR.be", 28, 0, 1, 1, NULL, }, + { "PSR.be", 28, 0, 3, 1, NULL, }, + { "PSR.be", 28, 0, 2, 1, NULL, }, + { "PSR.be", 28, 0, 2, 1, NULL, }, + { "PSR.bn", 28, 0, 2, 44, NULL, }, + { "PSR.cpl", 28, 0, 1, 32, NULL, }, + { "PSR.cpl", 28, 0, 2, 32, NULL, }, + { "PSR.da", 28, 0, 2, 38, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.db", 28, 0, 2, 24, NULL, }, + { "PSR.db", 28, 0, 2, 24, NULL, }, + { "PSR.dd", 28, 0, 2, 39, NULL, }, + { "PSR.dfh", 28, 0, 3, 19, NULL, }, + { "PSR.dfh", 28, 0, 2, 19, NULL, }, + { "PSR.dfh", 28, 0, 2, 19, NULL, }, + { "PSR.dfl", 28, 0, 3, 18, NULL, }, + { "PSR.dfl", 28, 0, 2, 18, NULL, }, + { "PSR.dfl", 28, 0, 2, 18, NULL, }, + { "PSR.di", 28, 0, 3, 22, NULL, }, + { "PSR.di", 28, 0, 2, 22, NULL, }, + { "PSR.di", 28, 0, 2, 22, NULL, }, + { "PSR.dt", 28, 0, 3, 17, NULL, }, + { "PSR.dt", 28, 0, 2, 17, NULL, }, + { "PSR.dt", 28, 0, 2, 17, NULL, }, + { "PSR.ed", 28, 0, 2, 43, NULL, }, + { "PSR.i", 28, 0, 2, 14, NULL, }, + { "PSR.ia", 28, 0, 0, 14, NULL, }, + { "PSR.ic", 28, 0, 2, 13, NULL, }, + { "PSR.ic", 28, 0, 3, 13, NULL, }, + { "PSR.ic", 28, 0, 2, 13, NULL, }, + { "PSR.id", 28, 0, 0, 14, NULL, }, + { "PSR.is", 28, 0, 0, 14, NULL, }, + { "PSR.it", 28, 0, 2, 14, NULL, }, + { "PSR.lp", 28, 0, 2, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.lp", 28, 0, 2, 25, NULL, }, + { "PSR.mc", 28, 0, 2, 35, NULL, }, + { "PSR.mfh", 28, 0, 2, 5, NULL, }, + { "PSR.mfl", 28, 0, 2, 4, NULL, }, + { "PSR.pk", 28, 0, 3, 15, NULL, }, + { "PSR.pk", 28, 0, 2, 15, NULL, }, + { "PSR.pk", 28, 0, 2, 15, NULL, }, + { "PSR.pp", 28, 0, 2, 21, NULL, }, + { "PSR.ri", 28, 0, 0, 41, NULL, }, + { "PSR.rt", 28, 0, 2, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.rt", 28, 0, 2, 27, NULL, }, + { "PSR.si", 28, 0, 2, 23, NULL, }, + { "PSR.si", 28, 0, 3, 23, NULL, }, + { "PSR.si", 28, 0, 2, 23, NULL, }, + { "PSR.sp", 28, 0, 2, 20, NULL, }, + { "PSR.sp", 28, 0, 3, 20, NULL, }, + { "PSR.sp", 28, 0, 2, 20, NULL, }, + { "PSR.ss", 28, 0, 2, 40, NULL, }, + { "PSR.tb", 28, 0, 3, 26, NULL, }, + { "PSR.tb", 28, 0, 2, 26, NULL, }, + { "PSR.tb", 28, 0, 2, 26, NULL, }, + { "PSR.up", 28, 0, 2, 2, NULL, }, + { "PSR.vm", 28, 0, 1, 46, NULL, }, + { "PSR.vm", 28, 0, 2, 46, NULL, }, + { "RR#", 25, 0, 3, -1, NULL, }, + { "RR#", 25, 0, 2, -1, NULL, }, + { "RSE", 29, 0, 2, -1, NULL, }, + { "ALAT", 0, 1, 0, -1, NULL, }, + { "AR[BSP]", 26, 1, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, + { "AR[CCV]", 26, 1, 2, 32, NULL, }, + { "AR[CFLG]", 26, 1, 2, 27, NULL, }, + { "AR[CSD]", 26, 1, 2, 25, NULL, }, + { "AR[EC]", 26, 1, 2, 66, NULL, }, + { "AR[EFLAG]", 26, 1, 2, 24, NULL, }, + { "AR[FCR]", 26, 1, 2, 21, NULL, }, + { "AR[FDR]", 26, 1, 2, 30, NULL, }, + { "AR[FIR]", 26, 1, 2, 29, NULL, }, + { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, + { "AR[FSR]", 26, 1, 2, 28, NULL, }, + { "AR[ITC]", 26, 1, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, + { "AR[LC]", 26, 1, 2, 65, NULL, }, + { "AR[PFS]", 26, 1, 0, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[RNAT]", 26, 1, 2, 19, NULL, }, + { "AR[RSC]", 26, 1, 2, 16, NULL, }, + { "AR[SSD]", 26, 1, 2, 26, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, }, + { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, + { "CFM", 6, 1, 2, -1, NULL, }, + { "CPUID#", 7, 1, 0, -1, NULL, }, + { "CR[CMCV]", 27, 1, 2, 74, NULL, }, + { "CR[DCR]", 27, 1, 2, 0, NULL, }, + { "CR[EOI]", 27, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", }, + { "CR[GPTA]", 27, 1, 2, 9, NULL, }, + { "CR[IFA]", 27, 1, 2, 20, NULL, }, + { "CR[IFS]", 27, 1, 2, 23, NULL, }, + { "CR[IHA]", 27, 1, 2, 25, NULL, }, + { "CR[IIM]", 27, 1, 2, 24, NULL, }, + { "CR[IIP]", 27, 1, 2, 19, NULL, }, + { "CR[IIPA]", 27, 1, 2, 22, NULL, }, + { "CR[IPSR]", 27, 1, 2, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, }, + { "CR[ISR]", 27, 1, 2, 17, NULL, }, + { "CR[ITIR]", 27, 1, 2, 21, NULL, }, + { "CR[ITM]", 27, 1, 2, 1, NULL, }, + { "CR[ITV]", 27, 1, 2, 72, NULL, }, + { "CR[IVA]", 27, 1, 2, 2, NULL, }, + { "CR[IVR]", 27, 1, 7, 65, "SC", }, + { "CR[LID]", 27, 1, 7, 64, "SC", }, + { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, }, + { "CR[PMV]", 27, 1, 2, 73, NULL, }, + { "CR[PTA]", 27, 1, 2, 8, NULL, }, + { "CR[TPR]", 27, 1, 2, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, }, + { "DBR#", 11, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 0, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 0, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, }, + { "GR0", 14, 1, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, }, + { "IBR#", 16, 1, 2, -1, NULL, }, + { "InService*", 17, 1, 7, -1, "SC", }, + { "IP", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 0, -1, NULL, }, + { "memory", 0, 1, 0, -1, NULL, }, + { "MSR#", 18, 1, 7, -1, "SC", }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 2, -1, NULL, }, + { "PMC#", 20, 1, 2, -1, NULL, }, + { "PMD#", 21, 1, 2, -1, NULL, }, + { "PR0", 0, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PSR.ac", 28, 1, 2, 3, NULL, }, + { "PSR.be", 28, 1, 2, 1, NULL, }, + { "PSR.bn", 28, 1, 2, 44, NULL, }, + { "PSR.cpl", 28, 1, 2, 32, NULL, }, + { "PSR.da", 28, 1, 2, 38, NULL, }, + { "PSR.db", 28, 1, 2, 24, NULL, }, + { "PSR.dd", 28, 1, 2, 39, NULL, }, + { "PSR.dfh", 28, 1, 2, 19, NULL, }, + { "PSR.dfl", 28, 1, 2, 18, NULL, }, + { "PSR.di", 28, 1, 2, 22, NULL, }, + { "PSR.dt", 28, 1, 2, 17, NULL, }, + { "PSR.ed", 28, 1, 2, 43, NULL, }, + { "PSR.i", 28, 1, 2, 14, NULL, }, + { "PSR.ia", 28, 1, 2, 14, NULL, }, + { "PSR.ic", 28, 1, 2, 13, NULL, }, + { "PSR.id", 28, 1, 2, 14, NULL, }, + { "PSR.is", 28, 1, 2, 14, NULL, }, + { "PSR.it", 28, 1, 2, 14, NULL, }, + { "PSR.lp", 28, 1, 2, 25, NULL, }, + { "PSR.mc", 28, 1, 2, 35, NULL, }, + { "PSR.mfh", 28, 1, 0, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfl", 28, 1, 0, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.pk", 28, 1, 2, 15, NULL, }, + { "PSR.pp", 28, 1, 2, 21, NULL, }, + { "PSR.ri", 28, 1, 2, 41, NULL, }, + { "PSR.rt", 28, 1, 2, 27, NULL, }, + { "PSR.si", 28, 1, 2, 23, NULL, }, + { "PSR.sp", 28, 1, 2, 20, NULL, }, + { "PSR.ss", 28, 1, 2, 40, NULL, }, + { "PSR.tb", 28, 1, 2, 26, NULL, }, + { "PSR.up", 28, 1, 2, 2, NULL, }, + { "PSR.vm", 28, 1, 2, 46, NULL, }, + { "RR#", 25, 1, 2, -1, NULL, }, + { "RSE", 29, 1, 2, -1, NULL, }, + { "PR63", 24, 2, 6, -1, NULL, }, +}; + +static const unsigned short dep0[] = { + 97, 282, 2140, 2327, +}; + +static const unsigned short dep1[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2327, 4135, 20616, +}; + +static const unsigned short dep2[] = { + 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2347, 2348, 2351, + 2352, 2355, 2356, +}; + +static const unsigned short dep3[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 20616, +}; + +static const unsigned short dep4[] = { + 97, 282, 22646, 22647, 22649, 22650, 22652, 22653, 22655, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep5[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 4135, 20616, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep6[] = { + 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2347, 2349, + 2351, 2353, 2355, +}; + +static const unsigned short dep7[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2344, 2345, 2348, 2349, 2352, 2353, 2356, 4135, 20616, +}; + +static const unsigned short dep8[] = { + 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2346, 2348, 2350, + 2352, 2354, 2356, +}; + +static const unsigned short dep9[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2344, 2346, 2347, 2350, 2351, 2354, 2355, 4135, 20616, +}; + +static const unsigned short dep10[] = { + 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2346, 2347, + 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, +}; + +static const unsigned short dep11[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2344, 2345, 2346, 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, + 4135, 20616, +}; + +static const unsigned short dep12[] = { + 97, 282, 2395, +}; + +static const unsigned short dep13[] = { + 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2082, 2083, 2166, 2168, + 2169, 2171, 2172, 2174, 2175, 4135, +}; + +static const unsigned short dep14[] = { + 97, 163, 282, 325, 2395, 28866, 29018, +}; + +static const unsigned short dep15[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 40, 41, 97, 150, 152, 158, 162, + 164, 175, 185, 186, 188, 282, 325, 2082, 2083, 2166, 2168, 2169, 2171, 2172, + 2174, 2175, 4135, 28866, 29018, +}; + +static const unsigned short dep16[] = { + 1, 6, 40, 97, 137, 196, 201, 241, 282, 312, 2395, 28866, 29018, +}; + +static const unsigned short dep17[] = { + 1, 25, 27, 38, 40, 41, 97, 158, 162, 164, 166, 167, 175, 185, 186, 188, 196, + 201, 241, 282, 312, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175, + 4135, 28866, 29018, +}; + +static const unsigned short dep18[] = { + 1, 40, 51, 97, 196, 241, 248, 282, 28866, 29018, +}; + +static const unsigned short dep19[] = { + 1, 38, 40, 41, 97, 158, 160, 161, 162, 175, 185, 190, 191, 196, 241, 248, + 282, 4135, 28866, 29018, +}; + +static const unsigned short dep20[] = { + 40, 97, 241, 282, +}; + +static const unsigned short dep21[] = { + 97, 158, 162, 175, 185, 241, 282, +}; + +static const unsigned short dep22[] = { + 1, 40, 97, 131, 135, 136, 138, 139, 142, 143, 146, 149, 152, 155, 156, 157, + 158, 161, 162, 163, 164, 167, 168, 169, 170, 173, 174, 175, 178, 181, 184, + 185, 188, 189, 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316, + 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333, + 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 28866, 29018, +}; + +static const unsigned short dep23[] = { + 1, 38, 40, 41, 50, 51, 55, 58, 73, 97, 137, 138, 158, 162, 175, 185, 190, + 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, + 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333, 334, 335, 336, + 337, 338, 339, 340, 341, 342, 343, 344, 4135, 28866, 29018, +}; + +static const unsigned short dep24[] = { + 97, 136, 282, 311, +}; + +static const unsigned short dep25[] = { + 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 311, +}; + +static const unsigned short dep26[] = { + 97, 137, 282, 312, +}; + +static const unsigned short dep27[] = { + 25, 26, 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 312, + +}; + +static const unsigned short dep28[] = { + 97, 190, 282, 344, +}; + +static const unsigned short dep29[] = { + 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 344, +}; + +static const unsigned short dep30[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175, + 4135, +}; + +static const unsigned short dep31[] = { + 1, 25, 40, 97, 196, 228, 229, 241, 282, 2082, 2285, 2288, 2395, 28866, 29018, + +}; + +static const unsigned short dep32[] = { + 1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228, + 230, 241, 282, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286, + 2288, 4135, 28866, 29018, +}; + +static const unsigned short dep33[] = { + 97, 282, +}; + +static const unsigned short dep34[] = { + 97, 158, 162, 175, 185, 282, 2082, 2084, +}; + +static const unsigned short dep35[] = { + 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2168, 2169, 2171, + 2172, 2174, 2175, 4135, +}; + +static const unsigned short dep36[] = { + 6, 37, 38, 39, 97, 125, 126, 201, 241, 282, 307, 308, 2395, +}; + +static const unsigned short dep37[] = { + 6, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 241, 282, 307, + 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135, +}; + +static const unsigned short dep38[] = { + 24, 97, 227, 282, 2395, +}; + +static const unsigned short dep39[] = { + 24, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 227, 282, 2166, 2168, 2169, + 2171, 2172, 2174, 2175, 4135, +}; + +static const unsigned short dep40[] = { + 6, 24, 37, 38, 39, 97, 125, 126, 201, 227, 241, 282, 307, 308, 2395, +}; + +static const unsigned short dep41[] = { + 6, 24, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 227, 241, 282, + 307, 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135, +}; + +static const unsigned short dep42[] = { + 1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228, + 230, 241, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286, 2288, 4135, + 28866, 29018, +}; + +static const unsigned short dep43[] = { + 97, 158, 162, 175, 185, 282, +}; + +static const unsigned short dep44[] = { + 15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, + 22832, 22835, 22836, +}; + +static const unsigned short dep45[] = { + 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep46[] = { + 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325, + 18601, 18602, 18761, 18762, 18764, 18765, 22646, 22647, 22648, 22650, 22651, + 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep47[] = { + 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, + 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135, + 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep48[] = { + 16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, + 22832, 22835, 22836, +}; + +static const unsigned short dep49[] = { + 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep50[] = { + 17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, + 22832, 22835, 22836, +}; + +static const unsigned short dep51[] = { + 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep52[] = { + 18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, + 22832, 22835, 22836, +}; + +static const unsigned short dep53[] = { + 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep54[] = { + 15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + +}; + +static const unsigned short dep55[] = { + 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, +}; + +static const unsigned short dep56[] = { + 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325, + 18601, 18602, 18761, 18762, 18764, 18765, +}; + +static const unsigned short dep57[] = { + 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, + 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135, + 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, +}; + +static const unsigned short dep58[] = { + 16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + +}; + +static const unsigned short dep59[] = { + 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, +}; + +static const unsigned short dep60[] = { + 17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + +}; + +static const unsigned short dep61[] = { + 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, +}; + +static const unsigned short dep62[] = { + 18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, + +}; + +static const unsigned short dep63[] = { + 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, + 18764, 18766, +}; + +static const unsigned short dep64[] = { + 97, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, +}; + +static const unsigned short dep65[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, + 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, +}; + +static const unsigned short dep66[] = { + 11, 97, 206, 282, +}; + +static const unsigned short dep67[] = { + 11, 40, 41, 97, 158, 162, 175, 185, 206, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep68[] = { + 11, 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep69[] = { + 12, 97, 207, 282, +}; + +static const unsigned short dep70[] = { + 11, 40, 41, 97, 158, 162, 175, 185, 207, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep71[] = { + 13, 97, 208, 282, +}; + +static const unsigned short dep72[] = { + 11, 40, 41, 97, 158, 162, 175, 185, 208, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep73[] = { + 14, 97, 209, 282, +}; + +static const unsigned short dep74[] = { + 11, 40, 41, 97, 158, 162, 175, 185, 209, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep75[] = { + 15, 97, 211, 212, 282, +}; + +static const unsigned short dep76[] = { + 40, 41, 97, 158, 162, 175, 185, 211, 212, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep77[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep78[] = { + 16, 97, 214, 215, 282, +}; + +static const unsigned short dep79[] = { + 40, 41, 97, 158, 162, 175, 185, 214, 215, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep80[] = { + 17, 97, 217, 218, 282, +}; + +static const unsigned short dep81[] = { + 40, 41, 97, 158, 162, 175, 185, 217, 218, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep82[] = { + 18, 97, 220, 221, 282, +}; + +static const unsigned short dep83[] = { + 40, 41, 97, 158, 162, 175, 185, 220, 221, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep84[] = { + 15, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167, + 2170, 2173, 4135, +}; + +static const unsigned short dep85[] = { + 15, 16, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, + 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep86[] = { + 15, 17, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, + 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep87[] = { + 15, 18, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, + 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep88[] = { + 15, 97, 210, 211, 282, +}; + +static const unsigned short dep89[] = { + 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2166, 2167, 2170, + 2173, 4135, +}; + +static const unsigned short dep90[] = { + 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, +}; + +static const unsigned short dep91[] = { + 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, + 216, 218, 219, 221, 282, 2166, 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep92[] = { + 16, 97, 213, 214, 282, +}; + +static const unsigned short dep93[] = { + 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2166, 2167, 2170, + 2173, 4135, +}; + +static const unsigned short dep94[] = { + 17, 97, 216, 217, 282, +}; + +static const unsigned short dep95[] = { + 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2166, 2167, 2170, + 2173, 4135, +}; + +static const unsigned short dep96[] = { + 18, 97, 219, 220, 282, +}; + +static const unsigned short dep97[] = { + 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2166, 2167, 2170, + 2173, 4135, +}; + +static const unsigned short dep98[] = { + 15, 97, 210, 211, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, + 2348, 2351, 2352, 2355, 2356, +}; + +static const unsigned short dep99[] = { + 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, + 16530, 16531, 16533, +}; + +static const unsigned short dep100[] = { + 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2166, 2167, + 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351, 2352, 2355, 2356, +}; + +static const unsigned short dep101[] = { + 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, + 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2344, 2347, + 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533, +}; + +static const unsigned short dep102[] = { + 16, 97, 213, 214, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, + 2348, 2351, 2352, 2355, 2356, +}; + +static const unsigned short dep103[] = { + 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, + 16530, 16531, 16533, +}; + +static const unsigned short dep104[] = { + 17, 97, 216, 217, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, + 2348, 2351, 2352, 2355, 2356, +}; + +static const unsigned short dep105[] = { + 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, + 16530, 16531, 16533, +}; + +static const unsigned short dep106[] = { + 18, 97, 219, 220, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, + 2348, 2351, 2352, 2355, 2356, +}; + +static const unsigned short dep107[] = { + 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, + 16530, 16531, 16533, +}; + +static const unsigned short dep108[] = { + 15, 97, 210, 211, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, + 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep109[] = { + 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep110[] = { + 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 22646, 22647, + 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835, + 22836, +}; + +static const unsigned short dep111[] = { + 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, + 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 4135, 16528, + 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep112[] = { + 16, 97, 213, 214, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, + 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep113[] = { + 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep114[] = { + 17, 97, 216, 217, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, + 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep115[] = { + 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep116[] = { + 18, 97, 219, 220, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, + 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep117[] = { + 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, + 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep118[] = { + 97, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351, + 2352, 2355, 2356, +}; + +static const unsigned short dep119[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, + 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533, + +}; + +static const unsigned short dep120[] = { + 97, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, + 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep121[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, + 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835, + 22836, +}; + +static const unsigned short dep122[] = { + 19, 20, 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, + 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, + +}; + +static const unsigned short dep123[] = { + 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2138, 2139, 2140, 2166, + 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep124[] = { + 97, 282, 2083, 2084, 2286, 2287, +}; + +static const unsigned short dep125[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2285, 2287, 4135, 20616, +}; + +static const unsigned short dep126[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2082, 2084, 2166, 2167, 2170, 2173, 2327, + 4135, 20616, +}; + +static const unsigned short dep127[] = { + 97, 282, 14455, 14457, 14458, 14460, 14461, 14463, 14635, 14636, 14639, 14640, + 14643, 14644, +}; + +static const unsigned short dep128[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 4135, 14635, 14636, + 14639, 14640, 14643, 14644, 20616, 24694, 24695, 24698, 24701, +}; + +static const unsigned short dep129[] = { + 97, 122, 124, 125, 127, 282, 303, 304, 307, 308, +}; + +static const unsigned short dep130[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 303, 304, 307, 308, 4135, 24694, 24695, + 24698, 24701, +}; + +static const unsigned short dep131[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616, + +}; + +static const unsigned short dep132[] = { + 40, 41, 97, 119, 122, 125, 158, 162, 175, 185, 282, 2327, 4135, 20616, 24694, + +}; + +static const unsigned short dep133[] = { + 6, 24, 26, 27, 97, 201, 227, 230, 282, 2081, 2284, +}; + +static const unsigned short dep134[] = { + 40, 41, 97, 158, 162, 175, 185, 201, 227, 229, 282, 2138, 2139, 2140, 2166, + 2167, 2170, 2173, 2284, 4135, 20616, +}; + +static const unsigned short dep135[] = { + 6, 24, 25, 26, 40, 41, 97, 158, 162, 175, 185, 282, 2081, 2166, 2167, 2170, + 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep136[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2347, 2348, + 2351, 2352, 2355, 2356, 4135, +}; + +static const unsigned short dep137[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, 22824, + 22827, 22828, 22831, 22832, 22835, 22836, +}; + +static const unsigned short dep138[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2348, + 2349, 2352, 2353, 2356, 4135, +}; + +static const unsigned short dep139[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2346, 2347, + 2350, 2351, 2354, 2355, 4135, +}; + +static const unsigned short dep140[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2346, + 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 4135, +}; + +static const unsigned short dep141[] = { + 0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167, 2170, 2173, + 4135, +}; + +static const unsigned short dep142[] = { + 0, 97, 195, 282, +}; + +static const unsigned short dep143[] = { + 0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 195, 282, 2166, 2167, 2170, + 2173, 4135, +}; + +static const unsigned short dep144[] = { + 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep145[] = { + 2, 28, 97, 197, 231, 282, 28866, 29018, +}; + +static const unsigned short dep146[] = { + 1, 2, 28, 29, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 28866, 29018, + +}; + +static const unsigned short dep147[] = { + 1, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 4135, + 28866, 29018, +}; + +static const unsigned short dep148[] = { + 0, 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135, + +}; + +static const unsigned short dep149[] = { + 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 28, 29, 30, 31, 97, 196, 197, 198, 199, 200, 202, 203, 204, 205, 206, 207, + 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, 223, 224, 225, 231, + 232, 233, 234, 282, 2071, 2081, 2274, 2284, 28866, 29018, +}; + +static const unsigned short dep150[] = { + 29, 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 196, 197, 198, 199, + 200, 202, 203, 204, 205, 206, 207, 208, 209, 211, 212, 214, 215, 217, 218, + 220, 221, 222, 223, 224, 225, 231, 232, 233, 234, 282, 2138, 2139, 2140, 2166, + 2167, 2170, 2173, 2274, 2284, 4135, 20616, 28866, 29018, +}; + +static const unsigned short dep151[] = { + 97, 282, 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666, + 14667, 14669, 14670, 14679, +}; + +static const unsigned short dep152[] = { + 40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 2166, 2167, 2170, 2173, 4135, + 14645, 14646, 14666, 14667, 14669, 14670, 14679, +}; + +static const unsigned short dep153[] = { + 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666, 14667, + 14669, 14670, 14679, +}; + +static const unsigned short dep154[] = { + 183, 184, 14645, 14646, 14666, 14667, 14669, 14670, 14679, +}; + +static const unsigned short dep155[] = { + 97, 282, 14465, 14466, 14469, 14470, 14480, 14481, 14483, 14484, 14486, 14487, + 14489, 14490, 14493, 14495, 14496, 14505, 14506, 14507, 14508, 14510, 14515, + 14516, 14518, 14519, 14525, 14645, 14646, 14652, 14653, 14654, 14655, 14657, + 14659, 14666, 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, +}; + +static const unsigned short dep156[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170, + 2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666, + 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, 34888, +}; + +static const unsigned short dep157[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170, + 2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666, + 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, +}; + +static const unsigned short dep158[] = { + 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 28, 29, 30, 31, 40, 41, 97, 137, 138, 158, 162, 175, 180, 181, 185, 190, 191, + 282, 2071, 2081, 2166, 2167, 2170, 2173, 2327, 4135, 20616, 28866, +}; + +static const unsigned short dep159[] = { + 43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63, + 64, 65, 67, 69, 70, 71, 72, 73, 94, 96, 97, 243, 244, 245, 246, 247, 248, + 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261, 263, 264, 265, 281, + 282, 2116, 2310, +}; + +static const unsigned short dep160[] = { + 40, 41, 96, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191, 243, 244, + 245, 246, 247, 248, 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261, + 263, 264, 265, 281, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2310, 4135, + 20616, +}; + +static const unsigned short dep161[] = { + 59, 95, 97, 254, 281, 282, 2140, 2327, +}; + +static const unsigned short dep162[] = { + 40, 41, 43, 44, 46, 48, 49, 51, 52, 53, 54, 56, 57, 60, 61, 63, 64, 65, 66, + 67, 69, 70, 71, 94, 95, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191, + 254, 281, 282, 2107, 2116, 2166, 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep163[] = { + 2, 28, 41, 97, 197, 231, 241, 282, 2140, 2327, 28866, 29018, +}; + +static const unsigned short dep164[] = { + 2, 25, 26, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231, + 241, 282, 2327, 4135, 20616, 28866, 29018, +}; + +static const unsigned short dep165[] = { + 97, 129, 130, 133, 134, 140, 141, 144, 145, 147, 148, 150, 151, 153, 154, + 157, 159, 160, 165, 166, 169, 170, 171, 172, 174, 176, 177, 179, 180, 182, + 183, 186, 187, 189, 282, 309, 310, 314, 316, 317, 318, 319, 321, 323, 327, + 330, 331, 333, 334, 335, 336, 338, 339, 340, 342, 343, +}; + +static const unsigned short dep166[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 309, 310, 314, 316, + 317, 318, 319, 321, 323, 327, 330, 331, 333, 334, 335, 336, 338, 339, 340, + 342, 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, 34888, +}; + +static const unsigned short dep167[] = { + 97, 128, 130, 132, 134, 169, 170, 189, 282, 309, 310, 330, 331, 333, 334, + 343, +}; + +static const unsigned short dep168[] = { + 40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 309, 310, 330, 331, 333, 334, + 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep169[] = { + 40, 41, 97, 130, 131, 134, 135, 137, 138, 141, 142, 145, 146, 148, 149, 151, + 152, 154, 155, 157, 158, 159, 161, 162, 164, 165, 167, 168, 169, 170, 172, + 173, 174, 175, 176, 178, 179, 181, 182, 184, 185, 187, 188, 189, 190, 191, + 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep170[] = { + 40, 41, 97, 130, 131, 134, 135, 158, 162, 169, 170, 175, 185, 189, 282, 2166, + 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep171[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 153, 155, 158, 162, 171, 173, + 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep172[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 139, 140, 142, 143, 153, 155, + 158, 162, 171, 173, 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, + 2173, 4135, 20616, +}; + +static const unsigned short dep173[] = { + 77, 78, 97, 101, 102, 269, 270, 282, 284, 285, +}; + +static const unsigned short dep174[] = { + 40, 41, 47, 62, 78, 80, 86, 97, 99, 102, 137, 138, 158, 160, 161, 162, 175, + 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166, 2167, + 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep175[] = { + 40, 41, 47, 62, 78, 80, 97, 99, 102, 104, 106, 137, 138, 158, 160, 161, 162, + 175, 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166, + 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep176[] = { + 97, 282, 12480, 12481, 12633, +}; + +static const unsigned short dep177[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 12633, 20616, +}; + +static const unsigned short dep178[] = { + 97, 282, 6219, 6220, 6411, +}; + +static const unsigned short dep179[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 6411, 20616, +}; + +static const unsigned short dep180[] = { + 97, 282, 6237, 6424, +}; + +static const unsigned short dep181[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 6424, 20616, +}; + +static const unsigned short dep182[] = { + 97, 282, 6255, 6256, 6257, 6258, 6435, 6437, 8484, +}; + +static const unsigned short dep183[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 6258, 6436, 6437, 8304, 8483, 20616, +}; + +static const unsigned short dep184[] = { + 97, 282, 6259, 6260, 6438, +}; + +static const unsigned short dep185[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 6438, 20616, +}; + +static const unsigned short dep186[] = { + 97, 282, 6261, 6439, +}; + +static const unsigned short dep187[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 6439, 20616, +}; + +static const unsigned short dep188[] = { + 97, 282, 10350, 10530, +}; + +static const unsigned short dep189[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 10530, 20616, +}; + +static const unsigned short dep190[] = { + 77, 78, 82, 83, 97, 101, 102, 269, 270, 272, 273, 282, 284, 285, +}; + +static const unsigned short dep191[] = { + 40, 41, 47, 62, 78, 80, 83, 86, 97, 99, 102, 137, 138, 158, 160, 161, 162, + 175, 185, 190, 191, 192, 269, 270, 272, 274, 282, 284, 285, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep192[] = { + 77, 78, 97, 101, 102, 104, 105, 269, 270, 282, 284, 285, 286, 287, +}; + +static const unsigned short dep193[] = { + 40, 41, 47, 62, 78, 80, 97, 99, 102, 104, 106, 137, 138, 158, 160, 161, 162, + 175, 185, 190, 191, 192, 269, 270, 282, 284, 285, 286, 287, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep194[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 12481, 20616, +}; + +static const unsigned short dep195[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 6219, 20616, +}; + +static const unsigned short dep196[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 6237, 20616, +}; + +static const unsigned short dep197[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 6257, 8303, 20616, +}; + +static const unsigned short dep198[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 6259, 20616, +}; + +static const unsigned short dep199[] = { + 40, 41, 97, 137, 138, 158, 162, 175, 183, 184, 185, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 6260, 6261, 20616, +}; + +static const unsigned short dep200[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2327, 4135, 10350, 20616, +}; + +static const unsigned short dep201[] = { + 40, 41, 97, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, 2166, 2167, + 2170, 2173, 2327, 4135, 6186, 20616, +}; + +static const unsigned short dep202[] = { + 77, 79, 80, 97, 98, 99, 100, 268, 269, 282, 283, 284, +}; + +static const unsigned short dep203[] = { + 40, 41, 78, 79, 83, 85, 97, 100, 102, 104, 107, 137, 138, 158, 162, 175, 185, + 190, 191, 192, 268, 270, 282, 283, 285, 2138, 2139, 2140, 2166, 2167, 2170, + 2173, 4135, 20616, +}; + +static const unsigned short dep204[] = { + 77, 79, 80, 81, 97, 98, 99, 100, 103, 268, 269, 271, 282, 283, 284, +}; + +static const unsigned short dep205[] = { + 40, 41, 78, 79, 81, 83, 85, 97, 100, 102, 103, 104, 107, 137, 138, 158, 162, + 175, 185, 190, 191, 192, 268, 270, 271, 282, 283, 285, 2138, 2139, 2140, 2166, + 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep206[] = { + 77, 79, 80, 84, 85, 86, 97, 98, 99, 100, 268, 269, 274, 275, 282, 283, 284, + +}; + +static const unsigned short dep207[] = { + 40, 41, 78, 79, 83, 85, 97, 100, 102, 137, 138, 158, 162, 175, 185, 190, 191, + 192, 268, 270, 273, 275, 282, 283, 285, 2138, 2139, 2140, 2166, 2167, 2170, + 2173, 4135, 20616, +}; + +static const unsigned short dep208[] = { + 77, 79, 80, 97, 98, 99, 100, 106, 107, 108, 268, 269, 282, 283, 284, 287, + 288, +}; + +static const unsigned short dep209[] = { + 40, 41, 78, 79, 97, 100, 102, 104, 107, 137, 138, 158, 162, 175, 185, 190, + 191, 192, 268, 270, 282, 283, 285, 286, 288, 2138, 2139, 2140, 2166, 2167, + 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep210[] = { + 40, 41, 46, 70, 97, 158, 162, 175, 185, 190, 191, 192, 282, 2138, 2139, 2140, + 2166, 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep211[] = { + 40, 41, 97, 158, 162, 175, 185, 190, 191, 192, 282, 2138, 2139, 2140, 2166, + 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep212[] = { + 40, 41, 70, 77, 82, 84, 97, 137, 138, 153, 155, 158, 162, 175, 185, 190, 191, + 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep213[] = { + 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2135, 2136, 2137, 2138, + 2139, 2140, 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 20616, + +}; + +static const unsigned short dep214[] = { + 40, 41, 70, 77, 82, 84, 97, 153, 155, 158, 162, 175, 185, 192, 282, 2138, + 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep215[] = { + 40, 41, 78, 79, 97, 100, 137, 138, 158, 162, 175, 185, 190, 191, 268, 270, + 282, 283, 285, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, +}; + +static const unsigned short dep216[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep217[] = { + 5, 97, 200, 282, 2140, 2327, +}; + +static const unsigned short dep218[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 200, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, + +}; + +static const unsigned short dep219[] = { + 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, 185, + 190, 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep220[] = { + 0, 97, 195, 282, 2140, 2327, +}; + +static const unsigned short dep221[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, + 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep222[] = { + 0, 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, + 135, 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, + 185, 190, 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, + 4135, 20616, +}; + +static const unsigned short dep223[] = { + 31, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, + 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, + +}; + +static const unsigned short dep224[] = { + 0, 97, 195, 282, 2327, 26715, +}; + +static const unsigned short dep225[] = { + 0, 97, 109, 195, 282, 289, +}; + +static const unsigned short dep226[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, + +}; + +static const unsigned short dep227[] = { + 0, 5, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, + +}; + +static const unsigned short dep228[] = { + 0, 31, 97, 109, 195, 234, 282, 289, +}; + +static const unsigned short dep229[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 234, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, + +}; + +static const unsigned short dep230[] = { + 0, 97, 109, 195, 282, 289, 2140, 2327, +}; + +static const unsigned short dep231[] = { + 0, 3, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, + 191, 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep232[] = { + 0, 3, 5, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, + 135, 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, + 190, 191, 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, + 4135, 20616, +}; + +static const unsigned short dep233[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, + 191, 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep234[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, + 2327, 4135, 16528, 16530, 16531, 16533, 20616, +}; + +static const unsigned short dep235[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep236[] = { + 0, 31, 97, 109, 195, 234, 282, 289, 2140, 2327, +}; + +static const unsigned short dep237[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 234, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, + 20616, +}; + +static const unsigned short dep238[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, + 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep239[] = { + 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, 185, + 190, 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 4135, + 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep240[] = { + 0, 97, 195, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, +}; + +static const unsigned short dep241[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, + 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 4135, + 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep242[] = { + 0, 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, + 135, 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, + 185, 190, 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, + 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep243[] = { + 0, 97, 195, 282, 2137, 2325, 18601, 18602, 18761, 18762, 18764, 18765, +}; + +static const unsigned short dep244[] = { + 97, 282, 2136, 2140, 2325, 2327, 18601, 18602, 18761, 18762, 18764, 18765, + +}; + +static const unsigned short dep245[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 2327, 4135, 16528, + 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep246[] = { + 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, 185, + 190, 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 2327, + 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep247[] = { + 0, 97, 195, 282, 2136, 2140, 2325, 2327, 18601, 18602, 18761, 18762, 18764, + 18765, +}; + +static const unsigned short dep248[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, + 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, + 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 2327, + 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, +}; + +static const unsigned short dep249[] = { + 0, 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, + 135, 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, + 185, 190, 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, + 2327, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, + +}; + +static const unsigned short dep250[] = { + 0, 97, 195, 282, 2137, 2140, 2325, 2327, 18601, 18602, 18761, 18762, 18764, + 18765, +}; + +static const unsigned short dep251[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 282, 289, 2135, 2136, 2137, 2138, 2139, 2140, 2166, 2167, 2170, + 2173, 4135, 16528, 16530, 16531, 16533, 20616, +}; + +static const unsigned short dep252[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 137, 138, 139, 140, 142, 143, 153, 155, 156, + 158, 162, 171, 173, 175, 185, 192, 282, 2166, 2167, 2170, 2173, 4135, +}; + +static const unsigned short dep253[] = { + 40, 41, 70, 76, 77, 82, 84, 97, 137, 138, 139, 140, 142, 143, 153, 155, 156, + 158, 162, 171, 173, 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, + 2173, 2327, 4135, 20616, +}; + +static const unsigned short dep254[] = { + 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, + 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, + +}; + +static const unsigned short dep255[] = { + 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, + 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, + 192, 195, 282, 289, 2135, 2136, 2137, 2138, 2139, 2140, 2166, 2167, 2170, + 2173, 2327, 4135, 16528, 16530, 16531, 16533, 20616, +}; + +static const unsigned short dep256[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 24, 26, 27, 28, 29, 30, 31, 97, 196, 197, 198, 199, 200, 201, 202, 203, + 204, 205, 206, 207, 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, + 223, 224, 225, 227, 230, 231, 232, 233, 234, 282, 2071, 2081, 2140, 2274, + 2284, 2327, 28866, 29018, +}; + +static const unsigned short dep257[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 24, 25, 26, 28, 29, 30, 31, 40, 41, 97, 137, 138, 158, 162, 175, 180, + 181, 185, 190, 191, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, + 207, 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, 223, 224, 225, + 227, 229, 231, 232, 233, 234, 282, 2071, 2081, 2138, 2139, 2140, 2166, 2167, + 2170, 2173, 2274, 2284, 2327, 4135, 20616, 28866, 29018, +}; + +#define NELS(X) (sizeof(X)/sizeof(X[0])) +static const struct ia64_opcode_dependency +op_dependencies[] = { + { NELS(dep1), dep1, NELS(dep0), dep0, }, + { NELS(dep3), dep3, NELS(dep2), dep2, }, + { NELS(dep5), dep5, NELS(dep4), dep4, }, + { NELS(dep7), dep7, NELS(dep6), dep6, }, + { NELS(dep9), dep9, NELS(dep8), dep8, }, + { NELS(dep11), dep11, NELS(dep10), dep10, }, + { NELS(dep13), dep13, NELS(dep12), dep12, }, + { NELS(dep15), dep15, NELS(dep14), dep14, }, + { NELS(dep17), dep17, NELS(dep16), dep16, }, + { NELS(dep19), dep19, NELS(dep18), dep18, }, + { NELS(dep21), dep21, NELS(dep20), dep20, }, + { NELS(dep23), dep23, NELS(dep22), dep22, }, + { NELS(dep25), dep25, NELS(dep24), dep24, }, + { NELS(dep27), dep27, NELS(dep26), dep26, }, + { NELS(dep29), dep29, NELS(dep28), dep28, }, + { NELS(dep30), dep30, NELS(dep12), dep12, }, + { NELS(dep32), dep32, NELS(dep31), dep31, }, + { NELS(dep34), dep34, NELS(dep33), dep33, }, + { NELS(dep35), dep35, NELS(dep12), dep12, }, + { NELS(dep37), dep37, NELS(dep36), dep36, }, + { NELS(dep39), dep39, NELS(dep38), dep38, }, + { NELS(dep41), dep41, NELS(dep40), dep40, }, + { NELS(dep42), dep42, NELS(dep31), dep31, }, + { NELS(dep43), dep43, NELS(dep33), dep33, }, + { NELS(dep45), dep45, NELS(dep44), dep44, }, + { NELS(dep47), dep47, NELS(dep46), dep46, }, + { NELS(dep49), dep49, NELS(dep48), dep48, }, + { NELS(dep51), dep51, NELS(dep50), dep50, }, + { NELS(dep53), dep53, NELS(dep52), dep52, }, + { NELS(dep55), dep55, NELS(dep54), dep54, }, + { NELS(dep57), dep57, NELS(dep56), dep56, }, + { NELS(dep59), dep59, NELS(dep58), dep58, }, + { NELS(dep61), dep61, NELS(dep60), dep60, }, + { NELS(dep63), dep63, NELS(dep62), dep62, }, + { NELS(dep65), dep65, NELS(dep64), dep64, }, + { NELS(dep67), dep67, NELS(dep66), dep66, }, + { NELS(dep68), dep68, NELS(dep33), dep33, }, + { NELS(dep70), dep70, NELS(dep69), dep69, }, + { NELS(dep72), dep72, NELS(dep71), dep71, }, + { NELS(dep74), dep74, NELS(dep73), dep73, }, + { NELS(dep76), dep76, NELS(dep75), dep75, }, + { NELS(dep77), dep77, NELS(dep33), dep33, }, + { NELS(dep79), dep79, NELS(dep78), dep78, }, + { NELS(dep81), dep81, NELS(dep80), dep80, }, + { NELS(dep83), dep83, NELS(dep82), dep82, }, + { NELS(dep84), dep84, NELS(dep33), dep33, }, + { NELS(dep85), dep85, NELS(dep33), dep33, }, + { NELS(dep86), dep86, NELS(dep33), dep33, }, + { NELS(dep87), dep87, NELS(dep33), dep33, }, + { NELS(dep89), dep89, NELS(dep88), dep88, }, + { NELS(dep91), dep91, NELS(dep90), dep90, }, + { NELS(dep93), dep93, NELS(dep92), dep92, }, + { NELS(dep95), dep95, NELS(dep94), dep94, }, + { NELS(dep97), dep97, NELS(dep96), dep96, }, + { NELS(dep99), dep99, NELS(dep98), dep98, }, + { NELS(dep101), dep101, NELS(dep100), dep100, }, + { NELS(dep103), dep103, NELS(dep102), dep102, }, + { NELS(dep105), dep105, NELS(dep104), dep104, }, + { NELS(dep107), dep107, NELS(dep106), dep106, }, + { NELS(dep109), dep109, NELS(dep108), dep108, }, + { NELS(dep111), dep111, NELS(dep110), dep110, }, + { NELS(dep113), dep113, NELS(dep112), dep112, }, + { NELS(dep115), dep115, NELS(dep114), dep114, }, + { NELS(dep117), dep117, NELS(dep116), dep116, }, + { NELS(dep119), dep119, NELS(dep118), dep118, }, + { NELS(dep121), dep121, NELS(dep120), dep120, }, + { NELS(dep122), dep122, NELS(dep64), dep64, }, + { NELS(dep123), dep123, NELS(dep33), dep33, }, + { NELS(dep125), dep125, NELS(dep124), dep124, }, + { NELS(dep126), dep126, NELS(dep0), dep0, }, + { NELS(dep128), dep128, NELS(dep127), dep127, }, + { NELS(dep130), dep130, NELS(dep129), dep129, }, + { NELS(dep131), dep131, NELS(dep0), dep0, }, + { NELS(dep132), dep132, NELS(dep0), dep0, }, + { NELS(dep134), dep134, NELS(dep133), dep133, }, + { NELS(dep135), dep135, NELS(dep0), dep0, }, + { NELS(dep136), dep136, NELS(dep2), dep2, }, + { NELS(dep137), dep137, NELS(dep4), dep4, }, + { NELS(dep138), dep138, NELS(dep6), dep6, }, + { NELS(dep139), dep139, NELS(dep8), dep8, }, + { NELS(dep140), dep140, NELS(dep10), dep10, }, + { NELS(dep141), dep141, NELS(dep33), dep33, }, + { NELS(dep143), dep143, NELS(dep142), dep142, }, + { NELS(dep144), dep144, NELS(dep142), dep142, }, + { NELS(dep146), dep146, NELS(dep145), dep145, }, + { NELS(dep147), dep147, NELS(dep145), dep145, }, + { NELS(dep148), dep148, NELS(dep142), dep142, }, + { NELS(dep150), dep150, NELS(dep149), dep149, }, + { NELS(dep152), dep152, NELS(dep151), dep151, }, + { NELS(dep154), dep154, NELS(dep153), dep153, }, + { NELS(dep156), dep156, NELS(dep155), dep155, }, + { NELS(dep157), dep157, NELS(dep155), dep155, }, + { NELS(dep158), dep158, NELS(dep0), dep0, }, + { NELS(dep160), dep160, NELS(dep159), dep159, }, + { NELS(dep162), dep162, NELS(dep161), dep161, }, + { NELS(dep164), dep164, NELS(dep163), dep163, }, + { NELS(dep166), dep166, NELS(dep165), dep165, }, + { NELS(dep168), dep168, NELS(dep167), dep167, }, + { NELS(dep169), dep169, NELS(dep0), dep0, }, + { NELS(dep170), dep170, NELS(dep0), dep0, }, + { NELS(dep171), dep171, NELS(dep0), dep0, }, + { NELS(dep172), dep172, NELS(dep33), dep33, }, + { NELS(dep174), dep174, NELS(dep173), dep173, }, + { NELS(dep175), dep175, NELS(dep173), dep173, }, + { NELS(dep177), dep177, NELS(dep176), dep176, }, + { NELS(dep179), dep179, NELS(dep178), dep178, }, + { NELS(dep181), dep181, NELS(dep180), dep180, }, + { NELS(dep183), dep183, NELS(dep182), dep182, }, + { NELS(dep185), dep185, NELS(dep184), dep184, }, + { NELS(dep187), dep187, NELS(dep186), dep186, }, + { NELS(dep189), dep189, NELS(dep188), dep188, }, + { NELS(dep191), dep191, NELS(dep190), dep190, }, + { NELS(dep193), dep193, NELS(dep192), dep192, }, + { NELS(dep194), dep194, NELS(dep0), dep0, }, + { NELS(dep195), dep195, NELS(dep0), dep0, }, + { NELS(dep196), dep196, NELS(dep0), dep0, }, + { NELS(dep197), dep197, NELS(dep0), dep0, }, + { NELS(dep198), dep198, NELS(dep0), dep0, }, + { NELS(dep199), dep199, NELS(dep0), dep0, }, + { NELS(dep200), dep200, NELS(dep0), dep0, }, + { NELS(dep201), dep201, NELS(dep0), dep0, }, + { NELS(dep203), dep203, NELS(dep202), dep202, }, + { NELS(dep205), dep205, NELS(dep204), dep204, }, + { NELS(dep207), dep207, NELS(dep206), dep206, }, + { NELS(dep209), dep209, NELS(dep208), dep208, }, + { NELS(dep210), dep210, NELS(dep0), dep0, }, + { NELS(dep211), dep211, NELS(dep0), dep0, }, + { NELS(dep212), dep212, NELS(dep0), dep0, }, + { NELS(dep213), dep213, NELS(dep33), dep33, }, + { NELS(dep214), dep214, NELS(dep33), dep33, }, + { NELS(dep215), dep215, NELS(dep202), dep202, }, + { NELS(dep216), dep216, NELS(dep0), dep0, }, + { NELS(dep218), dep218, NELS(dep217), dep217, }, + { NELS(dep219), dep219, NELS(dep0), dep0, }, + { NELS(dep221), dep221, NELS(dep220), dep220, }, + { NELS(dep222), dep222, NELS(dep220), dep220, }, + { NELS(dep223), dep223, NELS(dep0), dep0, }, + { NELS(dep221), dep221, NELS(dep224), dep224, }, + { NELS(dep226), dep226, NELS(dep225), dep225, }, + { NELS(dep227), dep227, NELS(dep225), dep225, }, + { NELS(dep229), dep229, NELS(dep228), dep228, }, + { NELS(dep231), dep231, NELS(dep230), dep230, }, + { NELS(dep232), dep232, NELS(dep230), dep230, }, + { NELS(dep233), dep233, NELS(dep230), dep230, }, + { NELS(dep234), dep234, NELS(dep0), dep0, }, + { NELS(dep235), dep235, NELS(dep230), dep230, }, + { NELS(dep237), dep237, NELS(dep236), dep236, }, + { NELS(dep238), dep238, NELS(dep64), dep64, }, + { NELS(dep239), dep239, NELS(dep64), dep64, }, + { NELS(dep241), dep241, NELS(dep240), dep240, }, + { NELS(dep242), dep242, NELS(dep240), dep240, }, + { NELS(dep241), dep241, NELS(dep243), dep243, }, + { NELS(dep245), dep245, NELS(dep244), dep244, }, + { NELS(dep246), dep246, NELS(dep244), dep244, }, + { NELS(dep248), dep248, NELS(dep247), dep247, }, + { NELS(dep249), dep249, NELS(dep247), dep247, }, + { NELS(dep248), dep248, NELS(dep250), dep250, }, + { NELS(dep251), dep251, NELS(dep225), dep225, }, + { NELS(dep252), dep252, NELS(dep33), dep33, }, + { NELS(dep253), dep253, NELS(dep0), dep0, }, + { NELS(dep254), dep254, NELS(dep64), dep64, }, + { NELS(dep255), dep255, NELS(dep230), dep230, }, + { 0, NULL, 0, NULL, }, + { NELS(dep257), dep257, NELS(dep256), dep256, }, +}; + +static const struct ia64_completer_table +completer_table[] = { + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 594, -1, 0, 1, 6 }, + { 0x0, 0x0, 0, 657, -1, 0, 1, 18 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, + { 0x0, 0x0, 0, 756, -1, 0, 1, 18 }, + { 0x0, 0x0, 0, 2198, -1, 0, 1, 10 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, + { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, 2406, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, 1140, -1, 0, 1, 129 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 45 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, + { 0x0, 0x0, 0, 2246, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2473, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2250, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, 2252, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2482, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2485, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2507, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2510, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 36 }, + { 0x0, 0x0, 0, 2518, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 1409, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 83 }, + { 0x0, 0x0, 0, 1457, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1466, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1475, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1477, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 1479, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 1488, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1497, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1506, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1515, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1524, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1533, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1543, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1553, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1563, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1572, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1578, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1584, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1590, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1596, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1602, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1608, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1614, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1620, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1626, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1632, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1638, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1644, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1650, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1656, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1662, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1668, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1674, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1678, -1, 0, 1, 158 }, + { 0x0, 0x0, 0, 1682, -1, 0, 1, 159 }, + { 0x0, 0x0, 0, 1686, -1, 0, 1, 159 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 85 }, + { 0x0, 0x0, 0, 258, -1, 0, 1, 41 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 68 }, + { 0x1, 0x1, 0, 1166, -1, 20, 1, 68 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 73 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 93 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 94 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 96 }, + { 0x0, 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0x0, 0x0, 220, 2460, -1, 0, 1, 29 }, + { 0x3, 0x3, 220, 2461, -1, 27, 1, 29 }, + { 0x1, 0x1, 220, 2462, -1, 27, 1, 29 }, + { 0x0, 0x0, 220, 2463, -1, 0, 1, 66 }, + { 0x0, 0x0, 220, 2464, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2465, -1, 0, 1, 29 }, + { 0x1, 0x1, 220, 2466, -1, 36, 1, 66 }, + { 0x1, 0x1, 220, 2467, -1, 37, 1, 29 }, + { 0x0, 0x0, 220, 2468, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2469, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2470, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2471, -1, 0, 1, 66 }, + { 0x0, 0x0, 220, 2472, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 37, -1, 0, 1, 29 }, + { 0x1, 0x1, 220, 2474, -1, 36, 1, 66 }, + { 0x1, 0x1, 220, 2475, -1, 37, 1, 29 }, + { 0x0, 0x0, 220, 2476, -1, 0, 1, 29 }, + { 0x1, 0x1, 220, 2477, -1, 36, 1, 66 }, + { 0x1, 0x1, 220, 2478, -1, 37, 1, 29 }, + { 0x0, 0x0, 220, 2479, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2480, -1, 0, 1, 66 }, + { 0x0, 0x0, 220, 2481, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 42, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2483, -1, 0, 1, 66 }, + { 0x0, 0x0, 220, 2484, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 43, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2486, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2487, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2488, -1, 0, 1, 49 }, + { 0x1, 0x1, 220, 2489, -1, 27, 1, 49 }, + { 0x1, 0x1, 220, 2490, -1, 28, 1, 49 }, + { 0x3, 0x3, 220, 2491, -1, 27, 1, 49 }, + { 0x1, 0x1, 220, 2492, -1, 29, 1, 49 }, + { 0x5, 0x5, 220, 2493, -1, 27, 1, 49 }, + { 0x3, 0x3, 220, 2494, -1, 28, 1, 49 }, + { 0x7, 0x7, 220, 2495, -1, 27, 1, 49 }, + { 0x0, 0x0, 220, 2496, -1, 0, 1, 49 }, + { 0x0, 0x0, 220, 2497, -1, 0, 1, 49 }, + { 0x0, 0x0, 220, 2498, -1, 0, 1, 49 }, + { 0x0, 0x0, 220, 2499, -1, 0, 1, 49 }, + { 0x1, 0x1, 220, 2500, -1, 28, 1, 29 }, + { 0x0, 0x0, 220, 2501, -1, 0, 1, 29 }, + { 0x3, 0x3, 220, 2502, -1, 27, 1, 29 }, + { 0x1, 0x1, 220, 2503, -1, 27, 1, 29 }, + { 0x0, 0x0, 220, 2504, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2505, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2506, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 52, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2508, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2509, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 57, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 2511, -1, 0, 1, 24 }, + { 0x0, 0x0, 220, 2512, -1, 0, 1, 24 }, + { 0x0, 0x0, 220, 2513, -1, 0, 1, 24 }, + { 0x0, 0x0, 220, 2514, -1, 0, 1, 24 }, + { 0x0, 0x0, 220, 2515, -1, 0, 1, 35 }, + { 0x0, 0x0, 220, 2516, -1, 0, 1, 66 }, + { 0x0, 0x0, 220, 2517, -1, 0, 1, 29 }, + { 0x0, 0x0, 220, 64, -1, 0, 1, 29 }, + { 0x1, 0x1, 221, 2519, -1, 34, 1, 66 }, + { 0x1, 0x1, 221, 2520, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2521, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2522, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2523, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2524, -1, 34, 1, 46 }, + { 0x1, 0x1, 221, 2525, -1, 34, 1, 42 }, + { 0x400001, 0x400001, 221, 2526, -1, 12, 1, 61 }, + { 0x1, 0x1, 221, 2527, -1, 34, 1, 56 }, + { 0x1400001, 0x1400001, 221, 2528, -1, 12, 1, 61 }, + { 0x5, 0x5, 221, 2529, -1, 34, 1, 56 }, + { 0x600001, 0x600001, 221, 2530, -1, 12, 1, 61 }, + { 0x3, 0x3, 221, 2531, -1, 33, 1, 56 }, + { 0x1600001, 0x1600001, 221, 2532, -1, 12, 1, 51 }, + { 0xb, 0xb, 221, 2533, -1, 33, 1, 51 }, + { 0x1, 0x1, 221, 2534, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2535, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2536, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2537, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2538, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2539, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2540, -1, 34, 1, 51 }, + { 0x1, 0x1, 221, 2541, -1, 34, 1, 51 }, + { 0x400001, 0x400001, 221, 2542, -1, 12, 1, 61 }, + { 0x1, 0x1, 221, 2543, -1, 34, 1, 56 }, + { 0x600001, 0x1600001, 221, 2544, -1, 12, 1, 61 }, + { 0x3, 0xb, 221, 2545, -1, 33, 1, 56 }, + { 0x1, 0x1, 221, 2546, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2547, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2548, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2549, -1, 34, 1, 56 }, + { 0x400001, 0x400001, 221, 2550, -1, 12, 1, 61 }, + { 0x1, 0x1, 221, 2551, -1, 34, 1, 56 }, + { 0x1400001, 0x1400001, 221, 2552, -1, 12, 1, 61 }, + { 0x5, 0x5, 221, 2553, -1, 34, 1, 56 }, + { 0x600001, 0x600001, 221, 2554, -1, 12, 1, 61 }, + { 0x3, 0x3, 221, 2555, -1, 33, 1, 56 }, + { 0x1600001, 0x1600001, 221, 2556, -1, 12, 1, 51 }, + { 0xb, 0xb, 221, 2557, -1, 33, 1, 51 }, + { 0x1, 0x1, 221, 2558, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2559, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2560, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2561, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2562, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2563, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2564, -1, 34, 1, 51 }, + { 0x1, 0x1, 221, 2565, -1, 34, 1, 51 }, + { 0x400001, 0x400001, 221, 2566, -1, 12, 1, 61 }, + { 0x1, 0x1, 221, 2567, -1, 34, 1, 56 }, + { 0x600001, 0x1600001, 221, 2568, -1, 12, 1, 61 }, + { 0x3, 0xb, 221, 2569, -1, 33, 1, 56 }, + { 0x1, 0x1, 221, 2570, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2571, -1, 34, 1, 56 }, + { 0x1, 0x1, 221, 2572, -1, 34, 1, 61 }, + { 0x1, 0x1, 221, 2573, -1, 34, 1, 56 }, + { 0x41, 0x41, 221, 2574, -1, 28, 1, 31 }, + { 0x1, 0x1, 221, 2575, -1, 34, 1, 31 }, + { 0x83, 0x83, 221, 2576, -1, 27, 1, 31 }, + { 0x81, 0x81, 221, 2577, -1, 27, 1, 31 }, + { 0x1, 0x1, 221, 2578, -1, 34, 1, 66 }, + { 0x1, 0x1, 221, 2579, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2580, -1, 34, 1, 31 }, + { 0x5, 0x5, 221, 2581, -1, 34, 1, 66 }, + { 0x9, 0x9, 221, 2582, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2583, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2584, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2585, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2586, -1, 34, 1, 66 }, + { 0x1, 0x1, 221, 2587, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2588, -1, 34, 1, 31 }, + { 0x5, 0x5, 221, 2589, -1, 34, 1, 66 }, + { 0x9, 0x9, 221, 2590, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2591, -1, 34, 1, 31 }, + { 0x5, 0x5, 221, 2592, -1, 34, 1, 66 }, + { 0x9, 0x9, 221, 2593, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2594, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2595, -1, 34, 1, 66 }, + { 0x1, 0x1, 221, 2596, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2597, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2598, -1, 34, 1, 66 }, + { 0x1, 0x1, 221, 2599, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2600, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2601, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2602, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2603, -1, 34, 1, 51 }, + { 0x81, 0x81, 221, 2604, -1, 27, 1, 51 }, + { 0x41, 0x41, 221, 2605, -1, 28, 1, 51 }, + { 0x83, 0x83, 221, 2606, -1, 27, 1, 51 }, + { 0x21, 0x21, 221, 2607, -1, 29, 1, 51 }, + { 0x85, 0x85, 221, 2608, -1, 27, 1, 51 }, + { 0x43, 0x43, 221, 2609, -1, 28, 1, 51 }, + { 0x87, 0x87, 221, 2610, -1, 27, 1, 51 }, + { 0x1, 0x1, 221, 2611, -1, 34, 1, 51 }, + { 0x1, 0x1, 221, 2612, -1, 34, 1, 51 }, + { 0x1, 0x1, 221, 2613, -1, 34, 1, 51 }, + { 0x1, 0x1, 221, 2614, -1, 34, 1, 51 }, + { 0x41, 0x41, 221, 2615, -1, 28, 1, 31 }, + { 0x1, 0x1, 221, 2616, -1, 34, 1, 31 }, + { 0x83, 0x83, 221, 2617, -1, 27, 1, 31 }, + { 0x81, 0x81, 221, 2618, -1, 27, 1, 31 }, + { 0x1, 0x1, 221, 2619, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2620, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2621, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2622, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2623, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2624, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2625, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2626, -1, 34, 1, 26 }, + { 0x1, 0x1, 221, 2627, -1, 34, 1, 26 }, + { 0x1, 0x1, 221, 2628, -1, 34, 1, 26 }, + { 0x1, 0x1, 221, 2629, -1, 34, 1, 26 }, + { 0x1, 0x1, 221, 2630, -1, 34, 1, 37 }, + { 0x1, 0x1, 221, 2631, -1, 34, 1, 66 }, + { 0x1, 0x1, 221, 2632, -1, 34, 1, 31 }, + { 0x1, 0x1, 221, 2633, -1, 34, 1, 31 }, + { 0x1, 0x1, 222, 2634, -1, 35, 1, 66 }, + { 0x1, 0x1, 222, 2635, -1, 35, 1, 32 }, + { 0x1, 0x1, 222, 2636, -1, 35, 1, 32 }, + { 0x1, 0x1, 222, 2637, -1, 35, 1, 32 }, + { 0x1, 0x1, 222, 2638, -1, 35, 1, 32 }, + { 0x1, 0x1, 222, 2639, -1, 35, 1, 47 }, + { 0x1, 0x1, 222, 2640, -1, 35, 1, 43 }, + { 0x800001, 0x800001, 222, 2641, -1, 12, 1, 62 }, + { 0x1, 0x1, 222, 2642, -1, 35, 1, 57 }, + { 0x1800001, 0x1800001, 222, 2643, -1, 12, 1, 62 }, + { 0x3, 0x3, 222, 2644, -1, 35, 1, 57 }, + { 0xa00001, 0xa00001, 222, 2645, -1, 12, 1, 62 }, + { 0x5, 0x5, 222, 2646, -1, 33, 1, 57 }, + { 0x1a00001, 0x1a00001, 222, 2647, -1, 12, 1, 52 }, + { 0xd, 0xd, 222, 2648, -1, 33, 1, 52 }, + { 0x1, 0x1, 222, 2649, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2650, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2651, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2652, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2653, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2654, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2655, -1, 35, 1, 52 }, + { 0x1, 0x1, 222, 2656, -1, 35, 1, 52 }, + { 0x800001, 0x800001, 222, 2657, -1, 12, 1, 62 }, + { 0x1, 0x1, 222, 2658, -1, 35, 1, 57 }, + { 0xa00001, 0x1a00001, 222, 2659, -1, 12, 1, 62 }, + { 0x5, 0xd, 222, 2660, -1, 33, 1, 57 }, + { 0x1, 0x1, 222, 2661, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2662, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2663, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2664, -1, 35, 1, 57 }, + { 0x800001, 0x800001, 222, 2665, -1, 12, 1, 62 }, + { 0x1, 0x1, 222, 2666, -1, 35, 1, 57 }, + { 0x1800001, 0x1800001, 222, 2667, -1, 12, 1, 62 }, + { 0x3, 0x3, 222, 2668, -1, 35, 1, 57 }, + { 0xa00001, 0xa00001, 222, 2669, -1, 12, 1, 62 }, + { 0x5, 0x5, 222, 2670, -1, 33, 1, 57 }, + { 0x1a00001, 0x1a00001, 222, 2671, -1, 12, 1, 52 }, + { 0xd, 0xd, 222, 2672, -1, 33, 1, 52 }, + { 0x1, 0x1, 222, 2673, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2674, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2675, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2676, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2677, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2678, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2679, -1, 35, 1, 52 }, + { 0x1, 0x1, 222, 2680, -1, 35, 1, 52 }, + { 0x800001, 0x800001, 222, 2681, -1, 12, 1, 62 }, + { 0x1, 0x1, 222, 2682, -1, 35, 1, 57 }, + { 0xa00001, 0x1a00001, 222, 2683, -1, 12, 1, 62 }, + { 0x5, 0xd, 222, 2684, -1, 33, 1, 57 }, + { 0x1, 0x1, 222, 2685, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2686, -1, 35, 1, 57 }, + { 0x1, 0x1, 222, 2687, -1, 35, 1, 62 }, + { 0x1, 0x1, 222, 2688, -1, 35, 1, 57 }, + { 0x81, 0x81, 222, 2689, -1, 28, 1, 32 }, + { 0x1, 0x1, 222, 2690, -1, 35, 1, 32 }, + { 0x103, 0x103, 222, 2691, -1, 27, 1, 32 }, + { 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27, 1, 0 }, + { 0x1, 0x1, 238, 3024, -1, 27, 1, 0 }, + { 0x1, 0x1, 238, 3025, -1, 27, 1, 0 }, + { 0x0, 0x0, 261, -1, 2344, 0, 0, -1 }, + { 0x0, 0x0, 261, -1, 2346, 0, 0, -1 }, + { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, + { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, + { 0x0, 0x0, 261, -1, 2385, 0, 0, -1 }, + { 0x0, 0x0, 261, -1, 2387, 0, 0, -1 }, + { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, + { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, + { 0x0, 0x0, 263, 23, -1, 0, 1, 0 }, + { 0x0, 0x0, 263, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 263, -1, -1, 0, 1, 0 }, + { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, + { 0x0, 0x0, 263, 180, -1, 0, 1, 0 }, + { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 301, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 323, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 349, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 371, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, + { 0x0, 0x0, 264, -1, 2296, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2298, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2300, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2302, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2304, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2306, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2308, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2310, 12, 1, 50 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 50 }, + { 0x0, 0x0, 264, -1, 2312, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2314, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2316, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2318, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x0, 0x0, 264, -1, 2320, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2322, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2324, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2326, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2328, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2330, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2332, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2334, 12, 1, 50 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 50 }, + { 0x0, 0x0, 264, -1, 2336, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2338, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2340, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2342, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, 393, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 395, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 517, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 519, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 401, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 403, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 525, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 527, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 409, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 411, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 533, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 535, -1, 12, 1, 2 }, + { 0x0, 0x0, 265, -1, 2303, 0, 0, -1 }, + { 0x9, 0x9, 265, -1, 2311, 33, 1, 50 }, + { 0x9, 0x9, 265, -1, 2975, 33, 1, 50 }, + { 0x0, 0x0, 265, 1399, 2376, 0, 0, -1 }, + { 0x3, 0x3, 265, 1400, -1, 27, 1, 50 }, + { 0x0, 0x0, 269, 2856, -1, 0, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x1, 0x1, 271, 3018, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, 3019, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, 3020, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, 3021, -1, 28, 1, 0 }, + { 0x1, 0x1, 273, -1, -1, 27, 1, 100 }, + { 0x1, 0x1, 273, -1, -1, 27, 1, 100 }, + { 0x0, 0x0, 273, -1, 968, 0, 0, -1 }, + { 0x0, 0x0, 274, 3031, 2833, 0, 0, -1 }, + { 0x0, 0x0, 274, 3032, 2835, 0, 0, -1 }, + { 0x0, 0x0, 275, -1, 2834, 0, 0, -1 }, + { 0x0, 0x0, 275, -1, 2836, 0, 0, -1 }, + { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 281, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 285, -1, 2350, 0, 1, 30 }, + { 0x0, 0x0, 286, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 286, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 286, 2001, 3000, 0, 1, 1 }, + { 0x0, 0x0, 286, 2002, 3001, 0, 1, 1 }, + { 0x0, 0x0, 286, -1, 518, 0, 0, -1 }, + { 0x0, 0x0, 286, -1, 520, 0, 0, -1 }, + { 0x0, 0x0, 286, 2005, 3004, 0, 1, 76 }, + { 0x0, 0x0, 286, 2006, 3005, 0, 1, 76 }, + { 0x0, 0x0, 286, -1, 526, 0, 0, -1 }, + { 0x0, 0x0, 286, -1, 528, 0, 0, -1 }, + { 0x0, 0x0, 286, 2009, 3008, 0, 1, 1 }, + { 0x0, 0x0, 286, 2010, 3009, 0, 1, 1 }, + { 0x0, 0x0, 286, -1, 534, 0, 0, -1 }, + { 0x0, 0x0, 286, -1, 536, 0, 0, -1 }, +}; + +static const struct ia64_main_table +main_table[] = { + { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 0, }, + { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 1, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 67, 27, 0, 0 }, 0x0, 2, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 64, 26, 0, 0 }, 0x0, 3, }, + { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 24, 67, 27, 0, 0 }, 0x0, 4, }, + { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 5, }, + { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 24, 64, 26, 0, 0 }, 0x0, 6, }, + { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 24, 64, 26, 0, 0 }, 0x0, 7, }, + { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 3, 53, 54, 55 }, 0x221, 8, }, + { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 53, 54, 55, 0 }, 0x261, 9, }, + { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 10, }, + { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 11, }, + { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 12, }, + { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 13, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 16, 0, 0, 0, 0 }, 0x40, 969, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x0, 825, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x40, 826, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x200, 2234, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x240, 2235, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x0, 582, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x40, 583, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 82, 0, 0, 0, 0 }, 0x40, 990, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x0, 827, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x40, 828, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x210, 3029, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x250, 3030, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x30, 590, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x70, 591, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x230, 588, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x270, 589, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x0, 584, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x40, 585, }, + { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 537, }, + { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 960, }, + { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 66, 0, 0, 0, 0 }, 0x2, 1138, }, + { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 1263, }, + { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 70, 0, 0, 0, 0 }, 0x0, 3033, }, + { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 66, 0, 0, 0, 0 }, 0x0, 16, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 83, 0, 0, 0, 0 }, 0x40, 1023, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 83, 0, 0, 0, 0 }, 0x0, 829, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 83, 0, 0, 0, 0 }, 0x40, 830, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 83, 0, 0, 0 }, 0x0, 586, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 83, 0, 0, 0 }, 0x40, 587, }, + { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 16, 78, 0, 0, 0 }, 0x20, 2852, }, + { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 82, 78, 0, 0, 0 }, 0x20, 2853, }, + { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 222, }, + { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 25, 81, 0, 0, 0 }, 0x0, 2239, }, + { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 24, 82, 0, 0, 0 }, 0x0, 226, }, + { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 18, 82, 0, 0, 0 }, 0x0, 227, }, + { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 25, 81, 0, 0, 0 }, 0x0, 2240, }, + { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 19, 81, 0, 0, 0 }, 0x0, 2241, }, + { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 25, 81, 0, 0, 0 }, 0x0, 2242, }, + { 25, 4, 0, 0x0000000020000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 18, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x0, 1222, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 25, 26, 0, 0 }, 0x40, 1223, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 26, 25, 0 }, 0x0, 1181, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 26, 25, 0, 0 }, 0x40, 1182, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 26, 25, 0 }, 0x0, 1090, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 26, 25, 0, 0 }, 0x40, 1091, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x0, 1052, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 25, 26, 0, 0 }, 0x40, 1053, }, + { 26, 1, 2, 0x0000018200000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x40, 1376, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x0, 1092, }, + { 26, 1, 1, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 7, 26, 0, 0 }, 0x40, 1093, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 26, 7, 0 }, 0x40, 1226, }, + { 26, 1, 1, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 26, 7, 0, 0 }, 0x40, 1227, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x40, 1187, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x0, 1229, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 56, 26, 0, 0 }, 0x40, 1230, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 58, 26, 0 }, 0x0, 1188, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 58, 26, 0, 0 }, 0x40, 1189, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 58, 26, 0 }, 0x0, 1097, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 58, 26, 0, 0 }, 0x40, 1098, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 56, 26, 0 }, 0x0, 1059, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 56, 26, 0, 0 }, 0x40, 1060, }, + { 26, 1, 2, 0x0000018a00000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x40, 1381, }, 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0x400, 191, }, + { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 192, }, + { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 193, }, + { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 2785, }, + { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 2786, }, + { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 194, }, + { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 195, }, + { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 196, }, + { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 197, }, + { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 198, }, + { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 199, }, + { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 200, }, + { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 201, }, + { 249, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 202, }, + { 249, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 203, }, + { 249, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 204, }, + { 250, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x0, 205, }, + { 251, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 206, }, + { 252, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 207, }, + { 253, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 208, }, + { 254, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 1150, }, + { 255, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 209, }, + { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 23, 26, 77, 0 }, 0x0, 3040, }, + { 256, 2, 1, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 26, 77, 0, 0 }, 0x40, 3041, }, + { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 22, 26, 77, 0 }, 0x40, 2003, }, + { 256, 2, 1, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 26, 77, 0, 0 }, 0x40, 2004, }, + { 257, 2, 2, 0x000000a000082000ull, 0x000001fe00083000ull, { 22, 23, 50, 0, 0 }, 0x0, 3044, }, + { 257, 2, 1, 0x000000a000082000ull, 0x000001fe00083000ull, { 22, 50, 0, 0, 0 }, 0x40, 3045, }, + { 257, 2, 2, 0x000000a000082000ull, 0x000001fe00083000ull, { 23, 22, 50, 0, 0 }, 0x40, 2007, }, + { 257, 2, 1, 0x000000a000082000ull, 0x000001fe00083000ull, { 23, 50, 0, 0, 0 }, 0x40, 2008, }, + { 258, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 210, }, + { 259, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 23, 26, 0, 0 }, 0x0, 3048, }, + { 259, 2, 1, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 26, 0, 0, 0 }, 0x40, 3049, }, + { 259, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 22, 26, 0, 0 }, 0x40, 2011, }, + { 259, 2, 1, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 26, 0, 0, 0 }, 0x40, 2012, }, + { 260, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 211, }, + { 262, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 212, }, + { 266, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1131, }, + { 267, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1132, }, + { 268, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1133, }, + { 272, 4, 0, 0x00000000c0000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x28, 223, }, + { 277, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 213, }, + { 278, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 214, }, + { 279, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 215, }, + { 280, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 216, }, + { 282, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 1179, }, + { 282, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 1261, }, + { 283, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21, 0, 0 }, 0x40, 1180, }, + { 284, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 217, }, + { 284, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 218, }, + { 287, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 219, }, + { 288, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 220, }, + { 289, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 221, }, +}; + +static const char dis_table[] = { +0xa0, 0xc7, 0xc8, 0xa0, 0x2e, 0xd8, 0xa0, 0x2c, 0xc0, 0xa0, 0x1c, 0x00, +0x98, 0xb0, 0x02, 0x50, 0x90, 0x50, 0x90, 0x28, 0x24, 0x39, 0x28, 0x24, +0x39, 0x20, 0x90, 0x28, 0x24, 0x39, 0x18, 0x24, 0x39, 0x10, 0x91, 0x60, +0x90, 0x28, 0x24, 0x39, 0x00, 0x10, 0x10, 0x58, 0x41, 0x61, 0xc7, 0xc0, +0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, +0x10, 0x10, 0x52, 0xc0, 0xc0, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, +0x10, 0x10, 0x10, 0x24, 0x24, 0x70, 0x90, 0x28, 0x24, 0x38, 0xf0, 0x24, +0x38, 0xe8, 0xa8, 0x0b, 0x48, 0x15, 0x20, 0x97, 0x20, 0x95, 0xc8, 0x9a, +0xb8, 0x05, 0x38, 0x91, 0x18, 0x90, 0xa0, 0x90, 0x60, 0x80, 0x90, 0x20, +0x34, 0xa6, 0xa4, 0x25, 0x00, 0x34, 0xa3, 0x80, 0xa4, 0x36, 0xa0, 0x36, +0xd9, 0x90, 0x50, 0x90, 0x28, 0x80, 0x36, 0xcf, 0x80, 0x34, 0x86, 0x81, +0x33, 0xe2, 0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x24, 0x10, 0x34, +0x83, 0xa4, 0x1f, 0x08, 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0x2f, 0xc0, 0x85, 0x34, +0xce, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x76, 0xc0, 0x39, 0xd3, 0xe5, +0x22, 0x78, 0xc0, 0x39, 0xf7, 0xcb, 0x61, 0x2f, 0x80, 0x85, 0x34, 0xcd, +0x90, 0x48, 0xcb, 0xa1, 0x2f, 0x40, 0x85, 0x34, 0xcc, 0xcb, 0xa1, 0x2f, +0x00, 0x85, 0x34, 0xcb, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, +0xe5, 0x22, 0x68, 0xc0, 0x39, 0xbb, 0xe5, 0x22, 0x5c, 0xc0, 0x39, 0x8b, +0xcb, 0x61, 0x2d, 0x40, 0x85, 0x34, 0xba, 0x98, 0x50, 0x00, 0x80, 0xe5, +0x22, 0x50, 0xc0, 0x39, 0x5b, 0xe5, 0x22, 0x44, 0xc0, 0x39, 0x2b, 0xcb, +0x61, 0x2d, 0x00, 0x85, 0x34, 0xb9, 0x90, 0x48, 0xcb, 0xa1, 0x2c, 0xc0, +0x85, 0x34, 0xb8, 0xcb, 0xa1, 0x2c, 0x80, 0x85, 0x34, 0xb7, 0x91, 0x00, +0x90, 0x80, 0x90, 0x40, 0xe5, 0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, +0x01, 0x80, 0x30, 0x07, 0x90, 0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, +0xe5, 0x20, 0x00, 0x00, 0x30, 0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, +0x35, 0xc0, 0x38, 0xcd, 0xe5, 0x22, 0x38, 0x00, 0x38, 0xf5, 0x90, 0x40, +0xe5, 0x22, 0x24, 0x40, 0x38, 0x87, 0xe5, 0x22, 0x26, 0x80, 0x38, 0xaf, +0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x25, 0x48, 0x90, 0x80, 0x90, 0x40, +0xe5, 0x22, 0x8c, 0xc0, 0x3a, 0x2f, 0xe5, 0x22, 0x89, 0xc0, 0x3a, 0x3b, +0x90, 0x40, 0xe5, 0x22, 0x7c, 0xc0, 0x39, 0xef, 0xe5, 0x22, 0x79, 0xc0, +0x39, 0xfb, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, +0x6a, 0xc0, 0x39, 0xc3, 0xe5, 0x22, 0x5e, 0xc0, 0x39, 0x93, 0xcb, 0x61, +0x2b, 0x00, 0x85, 0x34, 0xb0, 0x90, 0x40, 0xe5, 0x22, 0x52, 0xc0, 0x39, +0x63, 0xe5, 0x22, 0x46, 0xc0, 0x39, 0x33, 0x90, 0x48, 0xcb, 0xa1, 0x2a, +0x80, 0x85, 0x34, 0xae, 0xcb, 0xa1, 0x2a, 0xc0, 0x85, 0x34, 0xaf, 0x10, +0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0x3c, 0x40, 0x38, 0xed, 0xe5, +0x22, 0x39, 0x40, 0x38, 0xfb, 0x90, 0x40, 0xe5, 0x22, 0x2a, 0xc0, 0x38, +0xa7, 0xe5, 0x22, 0x27, 0xc0, 0x38, 0xb5, +}; + +static const struct ia64_dis_names ia64_dis_names[] = { +{ 0x51, 41, 0, 10 }, +{ 0x31, 41, 1, 20 }, +{ 0x11, 42, 0, 19 }, +{ 0x29, 41, 0, 12 }, +{ 0x19, 41, 1, 24 }, +{ 0x9, 42, 0, 23 }, +{ 0x15, 41, 0, 14 }, +{ 0xd, 41, 1, 28 }, +{ 0x5, 42, 0, 27 }, +{ 0xb, 41, 0, 16 }, +{ 0x7, 41, 1, 32 }, +{ 0x3, 42, 0, 31 }, +{ 0x51, 39, 1, 58 }, +{ 0x50, 39, 0, 34 }, +{ 0xd1, 39, 1, 57 }, +{ 0xd0, 39, 0, 33 }, +{ 0x31, 39, 1, 68 }, +{ 0x30, 39, 1, 44 }, +{ 0x11, 40, 1, 67 }, +{ 0x10, 40, 0, 43 }, +{ 0x71, 39, 1, 66 }, +{ 0x70, 39, 1, 42 }, +{ 0x31, 40, 1, 65 }, +{ 0x30, 40, 0, 41 }, +{ 0x29, 39, 1, 60 }, +{ 0x28, 39, 0, 36 }, +{ 0x69, 39, 1, 59 }, +{ 0x68, 39, 0, 35 }, +{ 0x19, 39, 1, 72 }, +{ 0x18, 39, 1, 48 }, +{ 0x9, 40, 1, 71 }, +{ 0x8, 40, 0, 47 }, +{ 0x39, 39, 1, 70 }, +{ 0x38, 39, 1, 46 }, +{ 0x19, 40, 1, 69 }, +{ 0x18, 40, 0, 45 }, +{ 0x15, 39, 1, 62 }, +{ 0x14, 39, 0, 38 }, +{ 0x35, 39, 1, 61 }, +{ 0x34, 39, 0, 37 }, +{ 0xd, 39, 1, 76 }, +{ 0xc, 39, 1, 52 }, +{ 0x5, 40, 1, 75 }, +{ 0x4, 40, 0, 51 }, +{ 0x1d, 39, 1, 74 }, +{ 0x1c, 39, 1, 50 }, +{ 0xd, 40, 1, 73 }, +{ 0xc, 40, 0, 49 }, +{ 0xb, 39, 1, 64 }, +{ 0xa, 39, 0, 40 }, +{ 0x1b, 39, 1, 63 }, +{ 0x1a, 39, 0, 39 }, +{ 0x7, 39, 1, 80 }, +{ 0x6, 39, 1, 56 }, +{ 0x3, 40, 1, 79 }, +{ 0x2, 40, 0, 55 }, +{ 0xf, 39, 1, 78 }, +{ 0xe, 39, 1, 54 }, +{ 0x7, 40, 1, 77 }, +{ 0x6, 40, 0, 53 }, +{ 0x8, 38, 0, 82 }, +{ 0x18, 38, 0, 81 }, +{ 0x1, 38, 1, 86 }, +{ 0x2, 38, 0, 85 }, +{ 0x3, 38, 1, 84 }, +{ 0x4, 38, 0, 83 }, +{ 0x1, 336, 0, 87 }, +{ 0x20, 289, 0, 98 }, +{ 0x220, 289, 0, 94 }, +{ 0x1220, 289, 0, 91 }, +{ 0xa20, 289, 0, 92 }, +{ 0x620, 289, 0, 93 }, +{ 0x120, 289, 0, 95 }, +{ 0xa0, 289, 0, 96 }, +{ 0x60, 289, 0, 97 }, +{ 0x10, 289, 0, 102 }, +{ 0x90, 289, 0, 99 }, +{ 0x50, 289, 0, 100 }, +{ 0x30, 289, 0, 101 }, +{ 0x8, 289, 0, 103 }, +{ 0x4, 289, 0, 104 }, +{ 0x2, 289, 0, 105 }, +{ 0x1, 289, 0, 106 }, +{ 0x1, 411, 0, 108 }, +{ 0x3, 411, 0, 107 }, +{ 0x2, 417, 0, 109 }, +{ 0x1, 417, 0, 110 }, +{ 0x2, 413, 0, 111 }, +{ 0x1, 413, 0, 112 }, +{ 0x2, 415, 0, 113 }, +{ 0x1, 415, 0, 114 }, +{ 0x2, 419, 0, 115 }, +{ 0x1, 419, 0, 116 }, +{ 0x1, 268, 0, 143 }, +{ 0x5, 268, 0, 141 }, +{ 0x3, 268, 0, 142 }, +{ 0x140, 277, 0, 119 }, +{ 0x540, 277, 0, 117 }, +{ 0x340, 277, 0, 118 }, +{ 0xc0, 277, 0, 131 }, +{ 0x2c0, 277, 0, 129 }, +{ 0x1c0, 277, 0, 130 }, +{ 0x20, 277, 0, 146 }, +{ 0xa0, 277, 0, 144 }, +{ 0x60, 277, 0, 145 }, +{ 0x10, 277, 0, 158 }, +{ 0x50, 277, 0, 156 }, +{ 0x30, 277, 0, 157 }, +{ 0x8, 277, 0, 170 }, +{ 0x28, 277, 0, 168 }, +{ 0x18, 277, 0, 169 }, +{ 0x4, 277, 0, 180 }, +{ 0x2, 277, 0, 181 }, +{ 0x1, 277, 0, 182 }, +{ 0x140, 271, 0, 122 }, +{ 0x540, 271, 0, 120 }, +{ 0x340, 271, 0, 121 }, +{ 0xc0, 271, 0, 134 }, +{ 0x2c0, 271, 0, 132 }, +{ 0x1c0, 271, 0, 133 }, +{ 0x20, 271, 0, 149 }, +{ 0xa0, 271, 0, 147 }, +{ 0x60, 271, 0, 148 }, +{ 0x10, 271, 0, 161 }, +{ 0x50, 271, 0, 159 }, +{ 0x30, 271, 0, 160 }, +{ 0x8, 271, 0, 173 }, +{ 0x28, 271, 0, 171 }, +{ 0x18, 271, 0, 172 }, +{ 0x4, 271, 0, 183 }, +{ 0x2, 271, 0, 184 }, +{ 0x1, 271, 0, 185 }, +{ 0x140, 274, 0, 125 }, +{ 0x540, 274, 0, 123 }, +{ 0x340, 274, 0, 124 }, +{ 0xc0, 274, 0, 137 }, +{ 0x2c0, 274, 0, 135 }, +{ 0x1c0, 274, 0, 136 }, +{ 0x20, 274, 0, 152 }, +{ 0xa0, 274, 0, 150 }, +{ 0x60, 274, 0, 151 }, +{ 0x10, 274, 0, 164 }, +{ 0x50, 274, 0, 162 }, +{ 0x30, 274, 0, 163 }, +{ 0x8, 274, 0, 176 }, +{ 0x28, 274, 0, 174 }, +{ 0x18, 274, 0, 175 }, +{ 0x4, 274, 0, 186 }, +{ 0x2, 274, 0, 187 }, +{ 0x1, 274, 0, 188 }, +{ 0x140, 286, 0, 128 }, +{ 0x540, 286, 0, 126 }, +{ 0x340, 286, 0, 127 }, +{ 0xc0, 286, 0, 140 }, +{ 0x2c0, 286, 0, 138 }, +{ 0x1c0, 286, 0, 139 }, +{ 0x20, 286, 0, 155 }, +{ 0xa0, 286, 0, 153 }, +{ 0x60, 286, 0, 154 }, +{ 0x10, 286, 0, 167 }, +{ 0x50, 286, 0, 165 }, +{ 0x30, 286, 0, 166 }, +{ 0x8, 286, 0, 179 }, +{ 0x28, 286, 0, 177 }, +{ 0x18, 286, 0, 178 }, +{ 0x4, 286, 0, 189 }, +{ 0x2, 286, 0, 190 }, +{ 0x1, 286, 0, 191 }, +{ 0x8, 390, 0, 192 }, +{ 0x4, 390, 0, 193 }, +{ 0x2, 390, 0, 194 }, +{ 0x1, 390, 0, 195 }, +{ 0x20, 288, 0, 203 }, +{ 0x220, 288, 0, 199 }, +{ 0x1220, 288, 0, 196 }, +{ 0xa20, 288, 0, 197 }, +{ 0x620, 288, 0, 198 }, +{ 0x120, 288, 0, 200 }, +{ 0xa0, 288, 0, 201 }, +{ 0x60, 288, 0, 202 }, +{ 0x10, 288, 0, 207 }, +{ 0x90, 288, 0, 204 }, +{ 0x50, 288, 0, 205 }, +{ 0x30, 288, 0, 206 }, +{ 0x8, 288, 0, 208 }, +{ 0x4, 288, 0, 209 }, +{ 0x2, 288, 0, 210 }, +{ 0x1, 288, 0, 211 }, +{ 0x20, 287, 0, 219 }, +{ 0x220, 287, 0, 215 }, +{ 0x1220, 287, 0, 212 }, +{ 0xa20, 287, 0, 213 }, +{ 0x620, 287, 0, 214 }, +{ 0x120, 287, 0, 216 }, +{ 0xa0, 287, 0, 217 }, +{ 0x60, 287, 0, 218 }, +{ 0x10, 287, 0, 223 }, +{ 0x90, 287, 0, 220 }, +{ 0x50, 287, 0, 221 }, +{ 0x30, 287, 0, 222 }, +{ 0x8, 287, 0, 224 }, +{ 0x4, 287, 0, 225 }, +{ 0x2, 287, 0, 226 }, +{ 0x1, 287, 0, 227 }, +{ 0x140, 279, 0, 230 }, +{ 0x540, 279, 0, 228 }, +{ 0x340, 279, 0, 229 }, +{ 0xc0, 279, 0, 239 }, +{ 0x2c0, 279, 0, 237 }, +{ 0x1c0, 279, 0, 238 }, +{ 0x20, 279, 0, 248 }, +{ 0xa0, 279, 0, 246 }, +{ 0x60, 279, 0, 247 }, +{ 0x10, 279, 0, 257 }, +{ 0x50, 279, 0, 255 }, +{ 0x30, 279, 0, 256 }, +{ 0x8, 279, 0, 266 }, +{ 0x28, 279, 0, 264 }, +{ 0x18, 279, 0, 265 }, +{ 0x4, 279, 0, 273 }, +{ 0x2, 279, 0, 274 }, +{ 0x1, 279, 0, 275 }, +{ 0x140, 281, 0, 233 }, +{ 0x540, 281, 0, 231 }, +{ 0x340, 281, 0, 232 }, +{ 0xc0, 281, 0, 242 }, +{ 0x2c0, 281, 0, 240 }, +{ 0x1c0, 281, 0, 241 }, +{ 0x20, 281, 0, 251 }, +{ 0xa0, 281, 0, 249 }, +{ 0x60, 281, 0, 250 }, +{ 0x10, 281, 0, 260 }, +{ 0x50, 281, 0, 258 }, +{ 0x30, 281, 0, 259 }, +{ 0x8, 281, 0, 269 }, +{ 0x28, 281, 0, 267 }, +{ 0x18, 281, 0, 268 }, +{ 0x4, 281, 0, 276 }, +{ 0x2, 281, 0, 277 }, +{ 0x1, 281, 0, 278 }, +{ 0x140, 283, 0, 236 }, +{ 0x540, 283, 0, 234 }, +{ 0x340, 283, 0, 235 }, +{ 0xc0, 283, 0, 245 }, +{ 0x2c0, 283, 0, 243 }, +{ 0x1c0, 283, 0, 244 }, +{ 0x20, 283, 0, 254 }, +{ 0xa0, 283, 0, 252 }, +{ 0x60, 283, 0, 253 }, +{ 0x10, 283, 0, 263 }, +{ 0x50, 283, 0, 261 }, +{ 0x30, 283, 0, 262 }, +{ 0x8, 283, 0, 272 }, +{ 0x28, 283, 0, 270 }, +{ 0x18, 283, 0, 271 }, +{ 0x4, 283, 0, 279 }, +{ 0x2, 283, 0, 280 }, +{ 0x1, 283, 0, 281 }, +{ 0x140, 278, 0, 284 }, +{ 0x540, 278, 0, 282 }, +{ 0x340, 278, 0, 283 }, +{ 0xc0, 278, 0, 293 }, +{ 0x2c0, 278, 0, 291 }, +{ 0x1c0, 278, 0, 292 }, +{ 0x20, 278, 0, 302 }, +{ 0xa0, 278, 0, 300 }, +{ 0x60, 278, 0, 301 }, +{ 0x10, 278, 0, 311 }, +{ 0x50, 278, 0, 309 }, +{ 0x30, 278, 0, 310 }, +{ 0x8, 278, 0, 320 }, +{ 0x28, 278, 0, 318 }, +{ 0x18, 278, 0, 319 }, +{ 0x4, 278, 0, 327 }, +{ 0x2, 278, 0, 328 }, +{ 0x1, 278, 0, 329 }, +{ 0x140, 280, 0, 287 }, +{ 0x540, 280, 0, 285 }, +{ 0x340, 280, 0, 286 }, +{ 0xc0, 280, 0, 296 }, +{ 0x2c0, 280, 0, 294 }, +{ 0x1c0, 280, 0, 295 }, +{ 0x20, 280, 0, 305 }, +{ 0xa0, 280, 0, 303 }, +{ 0x60, 280, 0, 304 }, +{ 0x10, 280, 0, 314 }, +{ 0x50, 280, 0, 312 }, +{ 0x30, 280, 0, 313 }, +{ 0x8, 280, 0, 323 }, +{ 0x28, 280, 0, 321 }, +{ 0x18, 280, 0, 322 }, +{ 0x4, 280, 0, 330 }, +{ 0x2, 280, 0, 331 }, +{ 0x1, 280, 0, 332 }, +{ 0x140, 282, 0, 290 }, +{ 0x540, 282, 0, 288 }, +{ 0x340, 282, 0, 289 }, +{ 0xc0, 282, 0, 299 }, +{ 0x2c0, 282, 0, 297 }, +{ 0x1c0, 282, 0, 298 }, +{ 0x20, 282, 0, 308 }, +{ 0xa0, 282, 0, 306 }, +{ 0x60, 282, 0, 307 }, +{ 0x10, 282, 0, 317 }, +{ 0x50, 282, 0, 315 }, +{ 0x30, 282, 0, 316 }, +{ 0x8, 282, 0, 326 }, +{ 0x28, 282, 0, 324 }, +{ 0x18, 282, 0, 325 }, +{ 0x4, 282, 0, 333 }, +{ 0x2, 282, 0, 334 }, +{ 0x1, 282, 0, 335 }, +{ 0x1, 410, 0, 337 }, +{ 0x3, 410, 0, 336 }, +{ 0x2, 416, 0, 338 }, +{ 0x1, 416, 0, 339 }, +{ 0x2, 412, 0, 340 }, +{ 0x1, 412, 0, 341 }, +{ 0x2, 414, 0, 342 }, +{ 0x1, 414, 0, 343 }, +{ 0x2, 418, 0, 344 }, +{ 0x1, 418, 0, 345 }, +{ 0x1, 267, 0, 372 }, +{ 0x5, 267, 0, 370 }, +{ 0x3, 267, 0, 371 }, +{ 0x140, 276, 0, 348 }, +{ 0x540, 276, 0, 346 }, +{ 0x340, 276, 0, 347 }, +{ 0xc0, 276, 0, 360 }, +{ 0x2c0, 276, 0, 358 }, +{ 0x1c0, 276, 0, 359 }, +{ 0x20, 276, 0, 375 }, +{ 0xa0, 276, 0, 373 }, +{ 0x60, 276, 0, 374 }, +{ 0x10, 276, 0, 387 }, +{ 0x50, 276, 0, 385 }, +{ 0x30, 276, 0, 386 }, +{ 0x8, 276, 0, 399 }, +{ 0x28, 276, 0, 397 }, +{ 0x18, 276, 0, 398 }, +{ 0x4, 276, 0, 409 }, +{ 0x2, 276, 0, 410 }, +{ 0x1, 276, 0, 411 }, +{ 0x140, 270, 0, 351 }, +{ 0x540, 270, 0, 349 }, +{ 0x340, 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0x19, 63, 1, 2299 }, +{ 0x19, 64, 1, 2298 }, +{ 0x19, 65, 1, 2297 }, +{ 0x7, 81, 1, 2296 }, +{ 0x7, 82, 1, 2295 }, +{ 0x7, 83, 1, 2294 }, +{ 0x7, 84, 0, 2293 }, +{ 0x3, 62, 1, 2604 }, +{ 0x3, 63, 1, 2603 }, +{ 0x6, 63, 1, 2599 }, +{ 0x3, 64, 1, 2602 }, +{ 0x6, 64, 1, 2598 }, +{ 0x3, 65, 1, 2601 }, +{ 0x6, 65, 1, 2597 }, +{ 0x3, 66, 0, 2600 }, +{ 0x8, 86, 1, 2468 }, +{ 0x8, 87, 1, 2467 }, +{ 0x2, 88, 1, 2466 }, +{ 0x2, 89, 1, 2465 }, +{ 0x2, 90, 1, 2464 }, +{ 0x2, 91, 1, 2463 }, +{ 0x2, 92, 1, 2462 }, +{ 0x2, 93, 0, 2461 }, +{ 0x18, 86, 1, 2460 }, +{ 0x18, 87, 1, 2459 }, +{ 0x6, 88, 1, 2458 }, +{ 0x6, 89, 1, 2457 }, +{ 0x6, 90, 1, 2456 }, +{ 0x6, 91, 1, 2455 }, +{ 0x6, 92, 1, 2454 }, +{ 0x6, 93, 0, 2453 }, +{ 0x14, 86, 1, 2448 }, +{ 0x22, 87, 1, 2445 }, +{ 0x44, 87, 1, 2447 }, +{ 0xa, 94, 0, 2446 }, +{ 0x34, 86, 1, 2304 }, +{ 0xc4, 87, 1, 2303 }, +{ 0x38, 93, 1, 2301 }, +{ 0xe, 117, 0, 2302 }, +{ 0xc, 86, 1, 2608 }, +{ 0xa, 87, 1, 2605 }, +{ 0x14, 87, 1, 2607 }, +{ 0x6, 94, 0, 2606 }, +{ 0x2, 86, 1, 2316 }, +{ 0x2, 87, 1, 2315 }, +{ 0x4, 92, 1, 2314 }, +{ 0x4, 93, 0, 2313 }, +{ 0x12, 86, 1, 2312 }, +{ 0x42, 87, 1, 2311 }, +{ 0xc, 92, 1, 2310 }, +{ 0xc, 93, 0, 2309 }, +{ 0xa, 86, 1, 2452 }, +{ 0x12, 87, 1, 2451 }, +{ 0x24, 87, 1, 2449 }, +{ 0x5, 94, 0, 2450 }, +{ 0x1a, 86, 1, 2308 }, +{ 0x32, 87, 1, 2307 }, +{ 0x34, 93, 1, 2305 }, +{ 0x7, 117, 0, 2306 }, +{ 0x6, 86, 1, 2612 }, +{ 0x6, 87, 1, 2611 }, +{ 0xc, 87, 1, 2609 }, +{ 0x3, 94, 0, 2610 }, +{ 0x1, 86, 1, 2628 }, +{ 0x1, 87, 1, 2627 }, +{ 0x1, 88, 1, 2626 }, +{ 0x1, 89, 1, 2625 }, +{ 0x1, 90, 1, 2624 }, +{ 0x1, 91, 1, 2623 }, +{ 0x1, 92, 1, 2622 }, +{ 0x1, 93, 0, 2621 }, +{ 0x3, 86, 1, 2620 }, +{ 0x3, 87, 1, 2619 }, +{ 0x3, 88, 1, 2618 }, +{ 0x3, 89, 1, 2617 }, +{ 0x3, 90, 1, 2616 }, +{ 0x3, 91, 1, 2615 }, +{ 0x3, 92, 1, 2614 }, +{ 0x3, 93, 0, 2613 }, +{ 0x8, 53, 1, 2492 }, +{ 0x8, 54, 1, 2491 }, +{ 0x2, 55, 1, 2490 }, +{ 0x2, 56, 1, 2489 }, +{ 0x2, 57, 1, 2488 }, +{ 0x2, 58, 1, 2487 }, +{ 0x2, 59, 1, 2486 }, +{ 0x2, 60, 0, 2485 }, +{ 0x18, 53, 1, 2484 }, +{ 0x18, 54, 1, 2483 }, +{ 0x6, 55, 1, 2482 }, +{ 0x6, 56, 1, 2481 }, +{ 0x6, 57, 1, 2480 }, +{ 0x6, 58, 1, 2479 }, +{ 0x6, 59, 1, 2478 }, +{ 0x6, 60, 0, 2477 }, +{ 0x14, 53, 1, 2472 }, +{ 0x22, 54, 1, 2469 }, +{ 0x44, 54, 1, 2471 }, +{ 0xa, 61, 0, 2470 }, +{ 0x34, 53, 1, 2320 }, +{ 0xc4, 54, 1, 2319 }, +{ 0x38, 60, 1, 2317 }, +{ 0xe, 80, 0, 2318 }, +{ 0xc, 53, 1, 2632 }, +{ 0xa, 54, 1, 2629 }, +{ 0x14, 54, 1, 2631 }, +{ 0x6, 61, 0, 2630 }, +{ 0x2, 53, 1, 2332 }, +{ 0x2, 54, 1, 2331 }, +{ 0x4, 59, 1, 2330 }, +{ 0x4, 60, 0, 2329 }, +{ 0x12, 53, 1, 2328 }, +{ 0x42, 54, 1, 2327 }, +{ 0xc, 59, 1, 2326 }, +{ 0xc, 60, 0, 2325 }, +{ 0xa, 53, 1, 2476 }, +{ 0x12, 54, 1, 2475 }, +{ 0x24, 54, 1, 2473 }, +{ 0x5, 61, 0, 2474 }, +{ 0x1a, 53, 1, 2324 }, +{ 0x32, 54, 1, 2323 }, +{ 0x34, 60, 1, 2321 }, +{ 0x7, 80, 0, 2322 }, +{ 0x6, 53, 1, 2636 }, +{ 0x6, 54, 1, 2635 }, +{ 0xc, 54, 1, 2633 }, +{ 0x3, 61, 0, 2634 }, +{ 0x1, 53, 1, 2652 }, +{ 0x1, 54, 1, 2651 }, +{ 0x1, 55, 1, 2650 }, +{ 0x1, 56, 1, 2649 }, +{ 0x1, 57, 1, 2648 }, +{ 0x1, 58, 1, 2647 }, +{ 0x1, 59, 1, 2646 }, +{ 0x1, 60, 0, 2645 }, +{ 0x3, 53, 1, 2644 }, +{ 0x3, 54, 1, 2643 }, +{ 0x3, 55, 1, 2642 }, +{ 0x3, 56, 1, 2641 }, +{ 0x3, 57, 1, 2640 }, +{ 0x3, 58, 1, 2639 }, +{ 0x3, 59, 1, 2638 }, +{ 0x3, 60, 0, 2637 }, +{ 0x1, 4, 0, 2653 }, +{ 0x1, 296, 0, 2654 }, +{ 0x1, 379, 0, 2655 }, +{ 0x1, 374, 0, 2656 }, +{ 0x2, 358, 0, 2657 }, +{ 0x1, 358, 0, 2660 }, +{ 0x2, 357, 0, 2658 }, +{ 0x1, 357, 0, 2661 }, +{ 0x2, 356, 0, 2659 }, +{ 0x1, 356, 0, 2662 }, +{ 0x1, 355, 0, 2663 }, +{ 0x1, 354, 0, 2664 }, +{ 0x2, 353, 0, 2665 }, +{ 0x1, 353, 0, 2667 }, +{ 0x2, 352, 0, 2666 }, +{ 0x1, 352, 0, 2668 }, +{ 0x1, 382, 0, 2675 }, +{ 0x8, 381, 0, 2669 }, +{ 0x4, 381, 0, 2671 }, +{ 0x2, 381, 0, 2673 }, +{ 0x1, 381, 0, 2676 }, +{ 0x8, 380, 0, 2670 }, +{ 0x4, 380, 0, 2672 }, +{ 0x2, 380, 0, 2674 }, +{ 0x1, 380, 0, 2677 }, +{ 0x1, 351, 0, 2684 }, +{ 0x8, 350, 0, 2678 }, +{ 0x4, 350, 0, 2680 }, +{ 0x2, 350, 0, 2682 }, +{ 0x1, 350, 0, 2685 }, +{ 0x8, 349, 0, 2679 }, +{ 0x4, 349, 0, 2681 }, +{ 0x2, 349, 1, 2683 }, +{ 0x4, 143, 0, 1377 }, +{ 0x1, 349, 0, 2686 }, +{ 0x1, 6, 0, 2687 }, +{ 0x1, 7, 0, 2688 }, +{ 0x1, 295, 0, 2689 }, +{ 0x1, 456, 0, 2690 }, +{ 0x1, 346, 0, 2691 }, +{ 0x1, 13, 0, 2692 }, +{ 0x1, 11, 0, 2693 }, +{ 0x1, 422, 0, 2694 }, +{ 0x1, 394, 0, 2695 }, +{ 0x1, 393, 0, 2696 }, +{ 0x1, 455, 0, 2697 }, +{ 0x1, 345, 0, 2698 }, +{ 0x1, 12, 0, 2699 }, +{ 0x1, 10, 0, 2700 }, +{ 0x1, 5, 0, 2701 }, +{ 0x1, 421, 0, 2702 }, +{ 0x1, 420, 0, 2703 }, +{ 0x1, 1, 0, 2704 }, +{ 0x1, 0, 0, 2705 }, +}; + diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-asmtab.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-asmtab.h Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,148 @@ +/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Bob Manson of Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef IA64_ASMTAB_H +#define IA64_ASMTAB_H + +#include "ia64.h" + +/* The primary opcode table is made up of the following: */ +struct ia64_main_table +{ + /* The entry in the string table that corresponds to the name of this + opcode. */ + unsigned short name_index; + + /* The type of opcode; corresponds to the TYPE field in + struct ia64_opcode. */ + unsigned char opcode_type; + + /* The number of outputs for this opcode. */ + unsigned char num_outputs; + + /* The base insn value for this opcode. It may be modified by completers. */ + ia64_insn opcode; + + /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ + ia64_insn mask; + + /* The operands of this instruction. Corresponds to the OPERANDS field + in struct ia64_opcode. */ + unsigned char operands[5]; + + /* The flags for this instruction. Corresponds to the FLAGS field in + struct ia64_opcode. */ + short flags; + + /* The tree of completers for this instruction; this is an offset into + completer_table. */ + short completers; +}; + +/* Each instruction has a set of possible "completers", or additional + suffixes that can alter the instruction's behavior, and which has + potentially different dependencies. + + The completer entries modify certain bits in the instruction opcode. + Which bits are to be modified are marked by the BITS, MASK and + OFFSET fields. The completer entry may also note dependencies for the + opcode. + + These completers are arranged in a DAG; the pointers are indexes + into the completer_table array. The completer DAG is searched by + find_completer () and ia64_find_matching_opcode (). + + Note that each completer needs to be applied in turn, so that if we + have the instruction + cmp.lt.unc + the completer entries for both "lt" and "unc" would need to be applied + to the opcode's value. + + Some instructions do not require any completers; these contain an + empty completer entry. Instructions that require a completer do + not contain an empty entry. + + Terminal completers (those completers that validly complete an + instruction) are marked by having the TERMINAL_COMPLETER flag set. + + Only dependencies listed in the terminal completer for an opcode are + considered to apply to that opcode instance. */ + +struct ia64_completer_table +{ + /* The bit value that this completer sets. */ + unsigned int bits; + + /* And its mask. 1s are bits that are to be modified in the + instruction. */ + unsigned int mask; + + /* The entry in the string table that corresponds to the name of this + completer. */ + unsigned short name_index; + + /* An alternative completer, or -1 if this is the end of the chain. */ + short alternative; + + /* A pointer to the DAG of completers that can potentially follow + this one, or -1. */ + short subentries; + + /* The bit offset in the instruction where BITS and MASK should be + applied. */ + unsigned char offset : 7; + + unsigned char terminal_completer : 1; + + /* Index into the dependency list table */ + short dependencies; +}; + +/* This contains sufficient information for the disassembler to resolve + the complete name of the original instruction. */ +struct ia64_dis_names +{ + /* COMPLETER_INDEX represents the tree of completers that make up + the instruction. The LSB represents the top of the tree for the + specified instruction. + + A 0 bit indicates to go to the next alternate completer via the + alternative field; a 1 bit indicates that the current completer + is part of the instruction, and to go down the subentries index. + We know we've reached the final completer when we run out of 1 + bits. + + There is always at least one 1 bit. */ + unsigned int completer_index : 20; + + /* The index in the main_table[] array for the instruction. */ + unsigned short insn_index : 11; + + /* If set, the next entry in this table is an alternate possibility + for this instruction encoding. Which one to use is determined by + the instruction type and other factors (see opcode_verify ()). */ + unsigned int next_flag : 1; + + /* The disassembly priority of this entry among instructions. */ + unsigned short priority; +}; + +#endif diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-dis.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-dis.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,273 @@ +/* ia64-dis.c -- Disassemble ia64 instructions + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include + +#include "dis-asm.h" +#include "ia64.h" + +#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) + +/* Disassemble ia64 instruction. */ + +/* Return the instruction type for OPCODE found in unit UNIT. */ + +static enum ia64_insn_type +unit_to_type (ia64_insn opcode, enum ia64_unit unit) +{ + enum ia64_insn_type type; + int op; + + op = IA64_OP (opcode); + + if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) + { + type = IA64_TYPE_A; + } + else + { + switch (unit) + { + case IA64_UNIT_I: + type = IA64_TYPE_I; break; + case IA64_UNIT_M: + type = IA64_TYPE_M; break; + case IA64_UNIT_B: + type = IA64_TYPE_B; break; + case IA64_UNIT_F: + type = IA64_TYPE_F; break; + case IA64_UNIT_L: + case IA64_UNIT_X: + type = IA64_TYPE_X; break; + default: + type = -1; + } + } + return type; +} + +int +print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) +{ + ia64_insn t0, t1, slot[3], template, s_bit, insn; + int slotnum, j, status, need_comma, retval, slot_multiplier; + const struct ia64_operand *odesc; + const struct ia64_opcode *idesc; + const char *err, *str, *tname; + BFD_HOST_U_64_BIT value; + bfd_byte bundle[16]; + enum ia64_unit unit; + char regname[16]; + + if (info->bytes_per_line == 0) + info->bytes_per_line = 6; + info->display_endian = info->endian; + + slot_multiplier = info->bytes_per_line; + retval = slot_multiplier; + + slotnum = (((long) memaddr) & 0xf) / slot_multiplier; + if (slotnum > 2) + return -1; + + memaddr -= (memaddr & 0xf); + status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* bundles are always in little-endian byte order */ + t0 = bfd_getl64 (bundle); + t1 = bfd_getl64 (bundle + 8); + s_bit = t0 & 1; + template = (t0 >> 1) & 0xf; + slot[0] = (t0 >> 5) & 0x1ffffffffffLL; + slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); + slot[2] = (t1 >> 23) & 0x1ffffffffffLL; + + tname = ia64_templ_desc[template].name; + if (slotnum == 0) + (*info->fprintf_func) (info->stream, "[%s] ", tname); + else + (*info->fprintf_func) (info->stream, " "); + + unit = ia64_templ_desc[template].exec_unit[slotnum]; + + if (template == 2 && slotnum == 1) + { + /* skip L slot in MLI template: */ + slotnum = 2; + retval += slot_multiplier; + } + + insn = slot[slotnum]; + + if (unit == IA64_UNIT_NIL) + goto decoding_failed; + + idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); + if (idesc == NULL) + goto decoding_failed; + + /* print predicate, if any: */ + + if ((idesc->flags & IA64_OPCODE_NO_PRED) + || (insn & 0x3f) == 0) + (*info->fprintf_func) (info->stream, " "); + else + (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); + + /* now the actual instruction: */ + + (*info->fprintf_func) (info->stream, "%s", idesc->name); + if (idesc->operands[0]) + (*info->fprintf_func) (info->stream, " "); + + need_comma = 0; + for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) + { + odesc = elf64_ia64_operands + idesc->operands[j]; + + if (need_comma) + (*info->fprintf_func) (info->stream, ","); + + if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) + { + /* special case of 64 bit immediate load: */ + value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) + | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) + | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) + { + /* 62-bit immediate for nop.x/break.x */ + value = ((slot[1] & 0x1ffffffffffLL) << 21) + | (((insn >> 36) & 0x1) << 20) + | ((insn >> 6) & 0xfffff); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) + { + /* 60-bit immediate for long branches. */ + value = (((insn >> 13) & 0xfffff) + | (((insn >> 36) & 1) << 59) + | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4; + } + else + { + err = (*odesc->extract) (odesc, insn, &value); + if (err) + { + (*info->fprintf_func) (info->stream, "%s", err); + goto done; + } + } + + switch (odesc->class) + { + case IA64_OPND_CLASS_CST: + (*info->fprintf_func) (info->stream, "%s", odesc->str); + break; + + case IA64_OPND_CLASS_REG: + if (odesc->str[0] == 'a' && odesc->str[1] == 'r') + { + switch (value) + { + case 0: case 1: case 2: case 3: + case 4: case 5: case 6: case 7: + sprintf (regname, "ar.k%u", (unsigned int) value); + break; + case 16: strcpy (regname, "ar.rsc"); break; + case 17: strcpy (regname, "ar.bsp"); break; + case 18: strcpy (regname, "ar.bspstore"); break; + case 19: strcpy (regname, "ar.rnat"); break; + case 32: strcpy (regname, "ar.ccv"); break; + case 36: strcpy (regname, "ar.unat"); break; + case 40: strcpy (regname, "ar.fpsr"); break; + case 44: strcpy (regname, "ar.itc"); break; + case 64: strcpy (regname, "ar.pfs"); break; + case 65: strcpy (regname, "ar.lc"); break; + case 66: strcpy (regname, "ar.ec"); break; + default: + sprintf (regname, "ar%u", (unsigned int) value); + break; + } + (*info->fprintf_func) (info->stream, "%s", regname); + } + else + (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_IND: + (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_ABS: + str = 0; + if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) + switch (value) + { + case 0x0: str = "@brcst"; break; + case 0x8: str = "@mix"; break; + case 0x9: str = "@shuf"; break; + case 0xa: str = "@alt"; break; + case 0xb: str = "@rev"; break; + } + + if (str) + (*info->fprintf_func) (info->stream, "%s", str); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) + (*info->fprintf_func) (info->stream, "%lld", (long long) value); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) + (*info->fprintf_func) (info->stream, "%llu", (long long) value); + else + (*info->fprintf_func) (info->stream, "0x%llx", (long long) value); + break; + + case IA64_OPND_CLASS_REL: + (*info->print_address_func) (memaddr + value, info); + break; + } + + need_comma = 1; + if (j + 1 == idesc->num_outputs) + { + (*info->fprintf_func) (info->stream, "="); + need_comma = 0; + } + } + if (slotnum + 1 == ia64_templ_desc[template].group_boundary + || ((slotnum == 2) && s_bit)) + (*info->fprintf_func) (info->stream, ";;"); + + done: + ia64_free_opcode ((struct ia64_opcode *)idesc); + failed: + if (slotnum == 2) + retval += 16 - 3*slot_multiplier; + return retval; + + decoding_failed: + (*info->fprintf_func) (info->stream, " data8 %#011llx", (long long) insn); + goto failed; +} diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-gen.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-gen.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,2865 @@ +/* ia64-gen.c -- Generate a shrunk set of opcode tables + Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2006 + Free Software Foundation, Inc. + Written by Bob Manson, Cygnus Solutions, + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* While the ia64-opc-* set of opcode tables are easy to maintain, + they waste a tremendous amount of space. ia64-gen rearranges the + instructions into a directed acyclic graph (DAG) of instruction opcodes and + their possible completers, as well as compacting the set of strings used. + + The disassembler table consists of a state machine that does + branching based on the bits of the opcode being disassembled. The + state encodings have been chosen to minimize the amount of space + required. + + The resource table is constructed based on some text dependency tables, + which are also easier to maintain than the final representation. */ + +#include +#include +#include + +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "sysdep.h" +#include "getopt.h" +#include "ia64-opc.h" +#include "ia64-opc-a.c" +#include "ia64-opc-i.c" +#include "ia64-opc-m.c" +#include "ia64-opc-b.c" +#include "ia64-opc-f.c" +#include "ia64-opc-x.c" +#include "ia64-opc-d.c" + +#include +#define _(String) gettext (String) + +/* This is a copy of fprintf_vma from bfd/bfd-in2.h. We have to use this + always, because we might be compiled without BFD64 defined, if configured + for a 32-bit target and --enable-targets=all is used. This will work for + both 32-bit and 64-bit hosts. */ +#define _opcode_int64_low(x) ((unsigned long) (((x) & 0xffffffff))) +#define _opcode_int64_high(x) ((unsigned long) (((x) >> 32) & 0xffffffff)) +#define opcode_fprintf_vma(s,x) \ + fprintf ((s), "%08lx%08lx", _opcode_int64_high (x), _opcode_int64_low (x)) + +const char * program_name = NULL; +int debug = 0; + +#define NELEMS(a) (sizeof (a) / sizeof ((a)[0])) +#define tmalloc(X) (X *) xmalloc (sizeof (X)) + +/* The main opcode table entry. Each entry is a unique combination of + name and flags (no two entries in the table compare as being equal + via opcodes_eq). */ +struct main_entry +{ + /* The base name of this opcode. The names of its completers are + appended to it to generate the full instruction name. */ + struct string_entry *name; + /* The base opcode entry. Which one to use is a fairly arbitrary choice; + it uses the first one passed to add_opcode_entry. */ + struct ia64_opcode *opcode; + /* The list of completers that can be applied to this opcode. */ + struct completer_entry *completers; + /* Next entry in the chain. */ + struct main_entry *next; + /* Index in the main table. */ + int main_index; +} *maintable, **ordered_table; + +int otlen = 0; +int ottotlen = 0; +int opcode_count = 0; + +/* The set of possible completers for an opcode. */ +struct completer_entry +{ + /* This entry's index in the ia64_completer_table[] array. */ + int num; + + /* The name of the completer. */ + struct string_entry *name; + + /* This entry's parent. */ + struct completer_entry *parent; + + /* Set if this is a terminal completer (occurs at the end of an + opcode). */ + int is_terminal; + + /* An alternative completer. */ + struct completer_entry *alternative; + + /* Additional completers that can be appended to this one. */ + struct completer_entry *addl_entries; + + /* Before compute_completer_bits () is invoked, this contains the actual + instruction opcode for this combination of opcode and completers. + Afterwards, it contains those bits that are different from its + parent opcode. */ + ia64_insn bits; + + /* Bits set to 1 correspond to those bits in this completer's opcode + that are different from its parent completer's opcode (or from + the base opcode if the entry is the root of the opcode's completer + list). This field is filled in by compute_completer_bits (). */ + ia64_insn mask; + + /* Index into the opcode dependency list, or -1 if none. */ + int dependencies; + + /* Remember the order encountered in the opcode tables. */ + int order; +}; + +/* One entry in the disassembler name table. */ +struct disent +{ + /* The index into the ia64_name_dis array for this entry. */ + int ournum; + + /* The index into the main_table[] array. */ + int insn; + + /* The disassmbly priority of this entry. */ + int priority; + + /* The completer_index value for this entry. */ + int completer_index; + + /* How many other entries share this decode. */ + int nextcnt; + + /* The next entry sharing the same decode. */ + struct disent *nexte; + + /* The next entry in the name list. */ + struct disent *next_ent; +} *disinsntable = NULL; + +/* A state machine that will eventually be used to generate the + disassembler table. */ +struct bittree +{ + struct disent *disent; + struct bittree *bits[3]; /* 0, 1, and X (don't care). */ + int bits_to_skip; + int skip_flag; +} *bittree; + +/* The string table contains all opcodes and completers sorted in + alphabetical order. */ + +/* One entry in the string table. */ +struct string_entry +{ + /* The index in the ia64_strings[] array for this entry. */ + int num; + /* And the string. */ + char *s; +} **string_table = NULL; + +int strtablen = 0; +int strtabtotlen = 0; + + +/* Resource dependency entries. */ +struct rdep +{ + char *name; /* Resource name. */ + unsigned + mode:2, /* RAW, WAW, or WAR. */ + semantics:3; /* Dependency semantics. */ + char *extra; /* Additional semantics info. */ + int nchks; + int total_chks; /* Total #of terminal insns. */ + int *chks; /* Insn classes which read (RAW), write + (WAW), or write (WAR) this rsrc. */ + int *chknotes; /* Dependency notes for each class. */ + int nregs; + int total_regs; /* Total #of terminal insns. */ + int *regs; /* Insn class which write (RAW), write2 + (WAW), or read (WAR) this rsrc. */ + int *regnotes; /* Dependency notes for each class. */ + + int waw_special; /* Special WAW dependency note. */ +} **rdeps = NULL; + +static int rdepslen = 0; +static int rdepstotlen = 0; + +/* Array of all instruction classes. */ +struct iclass +{ + char *name; /* Instruction class name. */ + int is_class; /* Is a class, not a terminal. */ + int nsubs; + int *subs; /* Other classes within this class. */ + int nxsubs; + int xsubs[4]; /* Exclusions. */ + char *comment; /* Optional comment. */ + int note; /* Optional note. */ + int terminal_resolved; /* Did we match this with anything? */ + int orphan; /* Detect class orphans. */ +} **ics = NULL; + +static int iclen = 0; +static int ictotlen = 0; + +/* An opcode dependency (chk/reg pair of dependency lists). */ +struct opdep +{ + int chk; /* index into dlists */ + int reg; /* index into dlists */ +} **opdeps; + +static int opdeplen = 0; +static int opdeptotlen = 0; + +/* A generic list of dependencies w/notes encoded. These may be shared. */ +struct deplist +{ + int len; + unsigned short *deps; +} **dlists; + +static int dlistlen = 0; +static int dlisttotlen = 0; + + +static void fail (const char *, ...) ATTRIBUTE_PRINTF_1; +static void warn (const char *, ...) ATTRIBUTE_PRINTF_1; +static struct rdep * insert_resource (const char *, enum ia64_dependency_mode); +static int deplist_equals (struct deplist *, struct deplist *); +static short insert_deplist (int, unsigned short *); +static short insert_dependencies (int, unsigned short *, int, unsigned short *); +static void mark_used (struct iclass *, int); +static int fetch_insn_class (const char *, int); +static int sub_compare (const void *, const void *); +static void load_insn_classes (void); +static void parse_resource_users (const char *, int **, int *, int **); +static int parse_semantics (char *); +static void add_dep (const char *, const char *, const char *, int, int, char *, int); +static void load_depfile (const char *, enum ia64_dependency_mode); +static void load_dependencies (void); +static int irf_operand (int, const char *); +static int in_iclass_mov_x (struct ia64_opcode *, struct iclass *, const char *, const char *); +static int in_iclass (struct ia64_opcode *, struct iclass *, const char *, const char *, int *); +static int lookup_regindex (const char *, int); +static int lookup_specifier (const char *); +static void print_dependency_table (void); +static struct string_entry * insert_string (char *); +static void gen_dis_table (struct bittree *); +static void print_dis_table (void); +static void generate_disassembler (void); +static void print_string_table (void); +static int completer_entries_eq (struct completer_entry *, struct completer_entry *); +static struct completer_entry * insert_gclist (struct completer_entry *); +static int get_prefix_len (const char *); +static void compute_completer_bits (struct main_entry *, struct completer_entry *); +static void collapse_redundant_completers (void); +static int insert_opcode_dependencies (struct ia64_opcode *, struct completer_entry *); +static void insert_completer_entry (struct ia64_opcode *, struct main_entry *, int); +static void print_completer_entry (struct completer_entry *); +static void print_completer_table (void); +static int opcodes_eq (struct ia64_opcode *, struct ia64_opcode *); +static void add_opcode_entry (struct ia64_opcode *); +static void print_main_table (void); +static void shrink (struct ia64_opcode *); +static void print_version (void); +static void usage (FILE *, int); +static void finish_distable (void); +static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_insn, int, int, int); +static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, struct completer_entry *, int); +static void compact_distree (struct bittree *); +static struct bittree * make_bittree_entry (void); +static struct disent * add_dis_table_ent (struct disent *, int, int, int); + + +static void +fail (const char *message, ...) +{ + va_list args; + + va_start (args, message); + fprintf (stderr, _("%s: Error: "), program_name); + vfprintf (stderr, message, args); + va_end (args); + xexit (1); +} + +static void +warn (const char *message, ...) +{ + va_list args; + + va_start (args, message); + + fprintf (stderr, _("%s: Warning: "), program_name); + vfprintf (stderr, message, args); + va_end (args); +} + +/* Add NAME to the resource table, where TYPE is RAW or WAW. */ +static struct rdep * +insert_resource (const char *name, enum ia64_dependency_mode type) +{ + if (rdepslen == rdepstotlen) + { + rdepstotlen += 20; + rdeps = (struct rdep **) + xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); + } + rdeps[rdepslen] = tmalloc(struct rdep); + memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); + rdeps[rdepslen]->name = xstrdup (name); + rdeps[rdepslen]->mode = type; + rdeps[rdepslen]->waw_special = 0; + + return rdeps[rdepslen++]; +} + +/* Are the lists of dependency indexes equivalent? */ +static int +deplist_equals (struct deplist *d1, struct deplist *d2) +{ + int i; + + if (d1->len != d2->len) + return 0; + + for (i = 0; i < d1->len; i++) + if (d1->deps[i] != d2->deps[i]) + return 0; + + return 1; +} + +/* Add the list of dependencies to the list of dependency lists. */ +static short +insert_deplist (int count, unsigned short *deps) +{ + /* Sort the list, then see if an equivalent list exists already. + this results in a much smaller set of dependency lists. */ + struct deplist *list; + char set[0x10000]; + int i; + + memset ((void *)set, 0, sizeof (set)); + for (i = 0; i < count; i++) + set[deps[i]] = 1; + + count = 0; + for (i = 0; i < (int) sizeof (set); i++) + if (set[i]) + ++count; + + list = tmalloc (struct deplist); + list->len = count; + list->deps = (unsigned short *) malloc (sizeof (unsigned short) * count); + + for (i = 0, count = 0; i < (int) sizeof (set); i++) + if (set[i]) + list->deps[count++] = i; + + /* Does this list exist already? */ + for (i = 0; i < dlistlen; i++) + if (deplist_equals (list, dlists[i])) + { + free (list->deps); + free (list); + return i; + } + + if (dlistlen == dlisttotlen) + { + dlisttotlen += 20; + dlists = (struct deplist **) + xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); + } + dlists[dlistlen] = list; + + return dlistlen++; +} + +/* Add the given pair of dependency lists to the opcode dependency list. */ +static short +insert_dependencies (int nchks, unsigned short *chks, + int nregs, unsigned short *regs) +{ + struct opdep *pair; + int i; + int regind = -1; + int chkind = -1; + + if (nregs > 0) + regind = insert_deplist (nregs, regs); + if (nchks > 0) + chkind = insert_deplist (nchks, chks); + + for (i = 0; i < opdeplen; i++) + if (opdeps[i]->chk == chkind + && opdeps[i]->reg == regind) + return i; + + pair = tmalloc (struct opdep); + pair->chk = chkind; + pair->reg = regind; + + if (opdeplen == opdeptotlen) + { + opdeptotlen += 20; + opdeps = (struct opdep **) + xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); + } + opdeps[opdeplen] = pair; + + return opdeplen++; +} + +static void +mark_used (struct iclass *ic, int clear_terminals) +{ + int i; + + ic->orphan = 0; + if (clear_terminals) + ic->terminal_resolved = 1; + + for (i = 0; i < ic->nsubs; i++) + mark_used (ics[ic->subs[i]], clear_terminals); + + for (i = 0; i < ic->nxsubs; i++) + mark_used (ics[ic->xsubs[i]], clear_terminals); +} + +/* Look up an instruction class; if CREATE make a new one if none found; + returns the index into the insn class array. */ +static int +fetch_insn_class (const char *full_name, int create) +{ + char *name; + char *notestr; + char *xsect; + char *comment; + int i, note = 0; + int ind; + int is_class = 0; + + if (strncmp (full_name, "IC:", 3) == 0) + { + name = xstrdup (full_name + 3); + is_class = 1; + } + else + name = xstrdup (full_name); + + if ((xsect = strchr(name, '\\')) != NULL) + is_class = 1; + if ((comment = strchr(name, '[')) != NULL) + is_class = 1; + if ((notestr = strchr(name, '+')) != NULL) + is_class = 1; + + /* If it is a composite class, then ignore comments and notes that come after + the '\\', since they don't apply to the part we are decoding now. */ + if (xsect) + { + if (comment > xsect) + comment = 0; + if (notestr > xsect) + notestr = 0; + } + + if (notestr) + { + char *nextnotestr; + + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + warn (_("multiple note %s not handled\n"), notestr); + } + } + + /* If it's a composite class, leave the notes and comments in place so that + we have a unique name for the composite class. Otherwise, we remove + them. */ + if (!xsect) + { + if (notestr) + *notestr = 0; + if (comment) + *comment = 0; + } + + for (i = 0; i < iclen; i++) + if (strcmp (name, ics[i]->name) == 0 + && ((comment == NULL && ics[i]->comment == NULL) + || (comment != NULL && ics[i]->comment != NULL + && strncmp (ics[i]->comment, comment, + strlen (ics[i]->comment)) == 0)) + && note == ics[i]->note) + return i; + + if (!create) + return -1; + + /* Doesn't exist, so make a new one. */ + if (iclen == ictotlen) + { + ictotlen += 20; + ics = (struct iclass **) + xrealloc (ics, (ictotlen) * sizeof (struct iclass *)); + } + + ind = iclen++; + ics[ind] = tmalloc (struct iclass); + memset ((void *)ics[ind], 0, sizeof (struct iclass)); + ics[ind]->name = xstrdup (name); + ics[ind]->is_class = is_class; + ics[ind]->orphan = 1; + + if (comment) + { + ics[ind]->comment = xstrdup (comment + 1); + ics[ind]->comment[strlen (ics[ind]->comment)-1] = 0; + } + + if (notestr) + ics[ind]->note = note; + + /* If it's a composite class, there's a comment or note, look for an + existing class or terminal with the same name. */ + if ((xsect || comment || notestr) && is_class) + { + /* First, populate with the class we're based on. */ + char *subname = name; + + if (xsect) + *xsect = 0; + else if (comment) + *comment = 0; + else if (notestr) + *notestr = 0; + + ics[ind]->nsubs = 1; + ics[ind]->subs = tmalloc(int); + ics[ind]->subs[0] = fetch_insn_class (subname, 1);; + } + + while (xsect) + { + char *subname = xsect + 1; + + xsect = strchr (subname, '\\'); + if (xsect) + *xsect = 0; + ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1); + ics[ind]->nxsubs++; + } + free (name); + + return ind; +} + +/* For sorting a class's sub-class list only; make sure classes appear before + terminals. */ +static int +sub_compare (const void *e1, const void *e2) +{ + struct iclass *ic1 = ics[*(int *)e1]; + struct iclass *ic2 = ics[*(int *)e2]; + + if (ic1->is_class) + { + if (!ic2->is_class) + return -1; + } + else if (ic2->is_class) + return 1; + + return strcmp (ic1->name, ic2->name); +} + +static void +load_insn_classes (void) +{ + FILE *fp = fopen ("ia64-ic.tbl", "r"); + char buf[2048]; + + if (fp == NULL) + fail (_("can't find ia64-ic.tbl for reading\n")); + + /* Discard first line. */ + fgets (buf, sizeof(buf), fp); + + while (!feof (fp)) + { + int iclass; + char *name; + char *tmp; + + if (fgets (buf, sizeof (buf), fp) == NULL) + break; + + while (ISSPACE (buf[strlen (buf) - 1])) + buf[strlen (buf) - 1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + { + ++tmp; + if (tmp == buf + sizeof (buf)) + abort (); + } + *tmp++ = '\0'; + + iclass = fetch_insn_class (name, 1); + ics[iclass]->is_class = 1; + + if (strcmp (name, "none") == 0) + { + ics[iclass]->is_class = 0; + ics[iclass]->terminal_resolved = 1; + continue; + } + + /* For this class, record all sub-classes. */ + while (*tmp) + { + char *subname; + int sub; + + while (*tmp && ISSPACE (*tmp)) + { + ++tmp; + if (tmp == buf + sizeof (buf)) + abort (); + } + subname = tmp; + while (*tmp && *tmp != ',') + { + ++tmp; + if (tmp == buf + sizeof (buf)) + abort (); + } + if (*tmp == ',') + *tmp++ = '\0'; + + ics[iclass]->subs = (int *) + xrealloc ((void *)ics[iclass]->subs, + (ics[iclass]->nsubs + 1) * sizeof (int)); + + sub = fetch_insn_class (subname, 1); + ics[iclass]->subs = (int *) + xrealloc (ics[iclass]->subs, (ics[iclass]->nsubs + 1) * sizeof (int)); + ics[iclass]->subs[ics[iclass]->nsubs++] = sub; + } + + /* Make sure classes come before terminals. */ + qsort ((void *)ics[iclass]->subs, + ics[iclass]->nsubs, sizeof(int), sub_compare); + } + fclose (fp); + + if (debug) + printf ("%d classes\n", iclen); +} + +/* Extract the insn classes from the given line. */ +static void +parse_resource_users (ref, usersp, nusersp, notesp) + const char *ref; + int **usersp; + int *nusersp; + int **notesp; +{ + int c; + char *line = xstrdup (ref); + char *tmp = line; + int *users = *usersp; + int count = *nusersp; + int *notes = *notesp; + + c = *tmp; + while (c != 0) + { + char *notestr; + int note; + char *xsect; + int iclass; + int create = 0; + char *name; + + while (ISSPACE (*tmp)) + ++tmp; + name = tmp; + while (*tmp && *tmp != ',') + ++tmp; + c = *tmp; + *tmp++ = '\0'; + + xsect = strchr (name, '\\'); + if ((notestr = strstr (name, "+")) != NULL) + { + char *nextnotestr; + + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + /* Note 13 always implies note 1. */ + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + warn (_("multiple note %s not handled\n"), notestr); + } + if (!xsect) + *notestr = '\0'; + } + else + note = 0; + + /* All classes are created when the insn class table is parsed; + Individual instructions might not appear until the dependency tables + are read. Only create new classes if it's *not* an insn class, + or if it's a composite class (which wouldn't necessarily be in the IC + table). */ + if (strncmp (name, "IC:", 3) != 0 || xsect != NULL) + create = 1; + + iclass = fetch_insn_class (name, create); + if (iclass != -1) + { + users = (int *) + xrealloc ((void *) users,(count + 1) * sizeof (int)); + notes = (int *) + xrealloc ((void *) notes,(count + 1) * sizeof (int)); + notes[count] = note; + users[count++] = iclass; + mark_used (ics[iclass], 0); + } + else if (debug) + printf("Class %s not found\n", name); + } + /* Update the return values. */ + *usersp = users; + *nusersp = count; + *notesp = notes; + + free (line); +} + +static int +parse_semantics (char *sem) +{ + if (strcmp (sem, "none") == 0) + return IA64_DVS_NONE; + else if (strcmp (sem, "implied") == 0) + return IA64_DVS_IMPLIED; + else if (strcmp (sem, "impliedF") == 0) + return IA64_DVS_IMPLIEDF; + else if (strcmp (sem, "data") == 0) + return IA64_DVS_DATA; + else if (strcmp (sem, "instr") == 0) + return IA64_DVS_INSTR; + else if (strcmp (sem, "specific") == 0) + return IA64_DVS_SPECIFIC; + else if (strcmp (sem, "stop") == 0) + return IA64_DVS_STOP; + else + return IA64_DVS_OTHER; +} + +static void +add_dep (const char *name, const char *chk, const char *reg, + int semantics, int mode, char *extra, int flag) +{ + struct rdep *rs; + + rs = insert_resource (name, mode); + + parse_resource_users (chk, &rs->chks, &rs->nchks, &rs->chknotes); + parse_resource_users (reg, &rs->regs, &rs->nregs, &rs->regnotes); + + rs->semantics = semantics; + rs->extra = extra; + rs->waw_special = flag; +} + +static void +load_depfile (const char *filename, enum ia64_dependency_mode mode) +{ + FILE *fp = fopen (filename, "r"); + char buf[1024]; + + if (fp == NULL) + fail (_("can't find %s for reading\n"), filename); + + fgets (buf, sizeof(buf), fp); + while (!feof (fp)) + { + char *name, *tmp; + int semantics; + char *extra; + char *regp, *chkp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (ISSPACE (buf[strlen (buf) - 1])) + buf[strlen (buf) - 1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + ++tmp; + *tmp++ = '\0'; + + while (ISSPACE (*tmp)) + ++tmp; + regp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (ISSPACE (*tmp)) + ++tmp; + chkp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (ISSPACE (*tmp)) + ++tmp; + semantics = parse_semantics (tmp); + extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; + + /* For WAW entries, if the chks and regs differ, we need to enter the + entries in both positions so that the tables will be parsed properly, + without a lot of extra work. */ + if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + add_dep (name, regp, chkp, semantics, mode, extra, 1); + } + else + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + } + } + fclose (fp); +} + +static void +load_dependencies (void) +{ + load_depfile ("ia64-raw.tbl", IA64_DV_RAW); + load_depfile ("ia64-waw.tbl", IA64_DV_WAW); + load_depfile ("ia64-war.tbl", IA64_DV_WAR); + + if (debug) + printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); +} + +/* Is the given operand an indirect register file operand? */ +static int +irf_operand (int op, const char *field) +{ + if (!field) + { + return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 + || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 + || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 + || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; + } + else + { + return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) + || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) + || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) + || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) + || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) + || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) + || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) + || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))); + } +} + +/* Handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and + mov_um insn classes. */ +static int +in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field) +{ + int plain_mov = strcmp (idesc->name, "mov") == 0; + + if (!format) + return 0; + + switch (ic->name[4]) + { + default: + abort (); + case 'a': + { + int i = strcmp (idesc->name, "mov.i") == 0; + int m = strcmp (idesc->name, "mov.m") == 0; + int i2627 = i && idesc->operands[0] == IA64_OPND_AR3; + int i28 = i && idesc->operands[1] == IA64_OPND_AR3; + int m2930 = m && idesc->operands[0] == IA64_OPND_AR3; + int m31 = m && idesc->operands[1] == IA64_OPND_AR3; + int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3; + int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3; + + /* IC:mov ar */ + if (i2627) + return strstr (format, "I26") || strstr (format, "I27"); + if (i28) + return strstr (format, "I28") != NULL; + if (m2930) + return strstr (format, "M29") || strstr (format, "M30"); + if (m31) + return strstr (format, "M31") != NULL; + if (pseudo0 || pseudo1) + return 1; + } + break; + case 'b': + { + int i21 = idesc->operands[0] == IA64_OPND_B1; + int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2; + if (i22) + return strstr (format, "I22") != NULL; + if (i21) + return strstr (format, "I21") != NULL; + } + break; + case 'c': + { + int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3; + int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3; + if (m32) + return strstr (format, "M32") != NULL; + if (m33) + return strstr (format, "M33") != NULL; + } + break; + case 'i': + if (ic->name[5] == 'n') + { + int m42 = plain_mov && irf_operand (idesc->operands[0], field); + int m43 = plain_mov && irf_operand (idesc->operands[1], field); + if (m42) + return strstr (format, "M42") != NULL; + if (m43) + return strstr (format, "M43") != NULL; + } + else if (ic->name[5] == 'p') + { + return idesc->operands[1] == IA64_OPND_IP; + } + else + abort (); + break; + case 'p': + if (ic->name[5] == 'r') + { + int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR; + int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR; + int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT; + if (i23) + return strstr (format, "I23") != NULL; + if (i24) + return strstr (format, "I24") != NULL; + if (i25) + return strstr (format, "I25") != NULL; + } + else if (ic->name[5] == 's') + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + else + abort (); + break; + case 'u': + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + break; + } + return 0; +} + +/* Is the given opcode in the given insn class? */ +static int +in_iclass (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field, int *notep) +{ + int i; + int resolved = 0; + + if (ic->comment) + { + if (!strncmp (ic->comment, "Format", 6)) + { + /* Assume that the first format seen is the most restrictive, and + only keep a later one if it looks like it's more restrictive. */ + if (format) + { + if (strlen (ic->comment) < strlen (format)) + { + warn (_("most recent format '%s'\nappears more restrictive than '%s'\n"), + ic->comment, format); + format = ic->comment; + } + } + else + format = ic->comment; + } + else if (!strncmp (ic->comment, "Field", 5)) + { + if (field) + warn (_("overlapping field %s->%s\n"), + ic->comment, field); + field = ic->comment; + } + } + + /* An insn class matches anything that is the same followed by completers, + except when the absence and presence of completers constitutes different + instructions. */ + if (ic->nsubs == 0 && ic->nxsubs == 0) + { + int is_mov = strncmp (idesc->name, "mov", 3) == 0; + int plain_mov = strcmp (idesc->name, "mov") == 0; + int len = strlen(ic->name); + + resolved = ((strncmp (ic->name, idesc->name, len) == 0) + && (idesc->name[len] == '\0' + || idesc->name[len] == '.')); + + /* All break, nop, and hint variations must match exactly. */ + if (resolved && + (strcmp (ic->name, "break") == 0 + || strcmp (ic->name, "nop") == 0 + || strcmp (ic->name, "hint") == 0)) + resolved = strcmp (ic->name, idesc->name) == 0; + + /* Assume restrictions in the FORMAT/FIELD negate resolution, + unless specifically allowed by clauses in this block. */ + if (resolved && field) + { + /* Check Field(sf)==sN against opcode sN. */ + if (strstr(field, "(sf)==") != NULL) + { + char *sf; + + if ((sf = strstr (idesc->name, ".s")) != 0) + resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; + } + /* Check Field(lftype)==XXX. */ + else if (strstr (field, "(lftype)") != NULL) + { + if (strstr (idesc->name, "fault") != NULL) + resolved = strstr (field, "fault") != NULL; + else + resolved = strstr (field, "fault") == NULL; + } + /* Handle Field(ctype)==XXX. */ + else if (strstr (field, "(ctype)") != NULL) + { + if (strstr (idesc->name, "or.andcm")) + resolved = strstr (field, "or.andcm") != NULL; + else if (strstr (idesc->name, "and.orcm")) + resolved = strstr (field, "and.orcm") != NULL; + else if (strstr (idesc->name, "orcm")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "or")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "andcm")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "and")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "unc")) + resolved = strstr (field, "unc") != NULL; + else + resolved = strcmp (field, "Field(ctype)==") == 0; + } + } + + if (resolved && format) + { + if (strncmp (idesc->name, "dep", 3) == 0 + && strstr (format, "I13") != NULL) + resolved = idesc->operands[1] == IA64_OPND_IMM8; + else if (strncmp (idesc->name, "chk", 3) == 0 + && strstr (format, "M21") != NULL) + resolved = idesc->operands[0] == IA64_OPND_F2; + else if (strncmp (idesc->name, "lfetch", 6) == 0) + resolved = (strstr (format, "M14 M15") != NULL + && (idesc->operands[1] == IA64_OPND_R2 + || idesc->operands[1] == IA64_OPND_IMM9b)); + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B5") != NULL) + resolved = idesc->operands[1] == IA64_OPND_B2; + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B3") != NULL) + resolved = idesc->operands[1] == IA64_OPND_TGT25c; + else if (strncmp (idesc->name, "brp", 3) == 0 + && strstr (format, "B7") != NULL) + resolved = idesc->operands[0] == IA64_OPND_B2; + else if (strcmp (ic->name, "invala") == 0) + resolved = strcmp (idesc->name, ic->name) == 0; + else if (strncmp (idesc->name, "st", 2) == 0 + && (strstr (format, "M5") != NULL + || strstr (format, "M10") != NULL)) + resolved = idesc->flags & IA64_OPCODE_POSTINC; + else if (strncmp (idesc->name, "ld", 2) == 0 + && (strstr (format, "M2 M3") != NULL + || strstr (format, "M12") != NULL + || strstr (format, "M7 M8") != NULL)) + resolved = idesc->flags & IA64_OPCODE_POSTINC; + else + resolved = 0; + } + + /* Misc brl variations ('.cond' is optional); + plain brl matches brl.cond. */ + if (!resolved + && (strcmp (idesc->name, "brl") == 0 + || strncmp (idesc->name, "brl.", 4) == 0) + && strcmp (ic->name, "brl.cond") == 0) + { + resolved = 1; + } + + /* Misc br variations ('.cond' is optional). */ + if (!resolved + && (strcmp (idesc->name, "br") == 0 + || strncmp (idesc->name, "br.", 3) == 0) + && strcmp (ic->name, "br.cond") == 0) + { + if (format) + resolved = (strstr (format, "B4") != NULL + && idesc->operands[0] == IA64_OPND_B2) + || (strstr (format, "B1") != NULL + && idesc->operands[0] == IA64_OPND_TGT25c); + else + resolved = 1; + } + + /* probe variations. */ + if (!resolved && strncmp (idesc->name, "probe", 5) == 0) + { + resolved = strcmp (ic->name, "probe") == 0 + && !((strstr (idesc->name, "fault") != NULL) + ^ (format && strstr (format, "M40") != NULL)); + } + + /* mov variations. */ + if (!resolved && is_mov) + { + if (plain_mov) + { + /* mov alias for fmerge. */ + if (strcmp (ic->name, "fmerge") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_F1 + && idesc->operands[1] == IA64_OPND_F3; + } + /* mov alias for adds (r3 or imm14). */ + else if (strcmp (ic->name, "adds") == 0) + { + resolved = (idesc->operands[0] == IA64_OPND_R1 + && (idesc->operands[1] == IA64_OPND_R3 + || (idesc->operands[1] == IA64_OPND_IMM14))); + } + /* mov alias for addl. */ + else if (strcmp (ic->name, "addl") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_R1 + && idesc->operands[1] == IA64_OPND_IMM22; + } + } + + /* Some variants of mov and mov.[im]. */ + if (!resolved && strncmp (ic->name, "mov_", 4) == 0) + resolved = in_iclass_mov_x (idesc, ic, format, field); + } + + /* Keep track of this so we can flag any insn classes which aren't + mapped onto at least one real insn. */ + if (resolved) + ic->terminal_resolved = 1; + } + else for (i = 0; i < ic->nsubs; i++) + { + if (in_iclass (idesc, ics[ic->subs[i]], format, field, notep)) + { + int j; + + for (j = 0; j < ic->nxsubs; j++) + if (in_iclass (idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) + return 0; + + if (debug > 1) + printf ("%s is in IC %s\n", idesc->name, ic->name); + + resolved = 1; + break; + } + } + + /* If it's in this IC, add the IC note (if any) to the insn. */ + if (resolved) + { + if (ic->note && notep) + { + if (*notep && *notep != ic->note) + warn (_("overwriting note %d with note %d (IC:%s)\n"), + *notep, ic->note, ic->name); + + *notep = ic->note; + } + } + + return resolved; +} + + +static int +lookup_regindex (const char *name, int specifier) +{ + switch (specifier) + { + case IA64_RS_ARX: + if (strstr (name, "[RSC]")) + return 16; + if (strstr (name, "[BSP]")) + return 17; + else if (strstr (name, "[BSPSTORE]")) + return 18; + else if (strstr (name, "[RNAT]")) + return 19; + else if (strstr (name, "[FCR]")) + return 21; + else if (strstr (name, "[EFLAG]")) + return 24; + else if (strstr (name, "[CSD]")) + return 25; + else if (strstr (name, "[SSD]")) + return 26; + else if (strstr (name, "[CFLG]")) + return 27; + else if (strstr (name, "[FSR]")) + return 28; + else if (strstr (name, "[FIR]")) + return 29; + else if (strstr (name, "[FDR]")) + return 30; + else if (strstr (name, "[CCV]")) + return 32; + else if (strstr (name, "[ITC]")) + return 44; + else if (strstr (name, "[PFS]")) + return 64; + else if (strstr (name, "[LC]")) + return 65; + else if (strstr (name, "[EC]")) + return 66; + abort (); + case IA64_RS_CRX: + if (strstr (name, "[DCR]")) + return 0; + else if (strstr (name, "[ITM]")) + return 1; + else if (strstr (name, "[IVA]")) + return 2; + else if (strstr (name, "[PTA]")) + return 8; + else if (strstr (name, "[GPTA]")) + return 9; + else if (strstr (name, "[IPSR]")) + return 16; + else if (strstr (name, "[ISR]")) + return 17; + else if (strstr (name, "[IIP]")) + return 19; + else if (strstr (name, "[IFA]")) + return 20; + else if (strstr (name, "[ITIR]")) + return 21; + else if (strstr (name, "[IIPA]")) + return 22; + else if (strstr (name, "[IFS]")) + return 23; + else if (strstr (name, "[IIM]")) + return 24; + else if (strstr (name, "[IHA]")) + return 25; + else if (strstr (name, "[LID]")) + return 64; + else if (strstr (name, "[IVR]")) + return 65; + else if (strstr (name, "[TPR]")) + return 66; + else if (strstr (name, "[EOI]")) + return 67; + else if (strstr (name, "[ITV]")) + return 72; + else if (strstr (name, "[PMV]")) + return 73; + else if (strstr (name, "[CMCV]")) + return 74; + abort (); + case IA64_RS_PSR: + if (strstr (name, ".be")) + return 1; + else if (strstr (name, ".up")) + return 2; + else if (strstr (name, ".ac")) + return 3; + else if (strstr (name, ".mfl")) + return 4; + else if (strstr (name, ".mfh")) + return 5; + else if (strstr (name, ".ic")) + return 13; + else if (strstr (name, ".i")) + return 14; + else if (strstr (name, ".pk")) + return 15; + else if (strstr (name, ".dt")) + return 17; + else if (strstr (name, ".dfl")) + return 18; + else if (strstr (name, ".dfh")) + return 19; + else if (strstr (name, ".sp")) + return 20; + else if (strstr (name, ".pp")) + return 21; + else if (strstr (name, ".di")) + return 22; + else if (strstr (name, ".si")) + return 23; + else if (strstr (name, ".db")) + return 24; + else if (strstr (name, ".lp")) + return 25; + else if (strstr (name, ".tb")) + return 26; + else if (strstr (name, ".rt")) + return 27; + else if (strstr (name, ".cpl")) + return 32; + else if (strstr (name, ".rs")) + return 34; + else if (strstr (name, ".mc")) + return 35; + else if (strstr (name, ".it")) + return 36; + else if (strstr (name, ".id")) + return 37; + else if (strstr (name, ".da")) + return 38; + else if (strstr (name, ".dd")) + return 39; + else if (strstr (name, ".ss")) + return 40; + else if (strstr (name, ".ri")) + return 41; + else if (strstr (name, ".ed")) + return 43; + else if (strstr (name, ".bn")) + return 44; + else if (strstr (name, ".ia")) + return 45; + else if (strstr (name, ".vm")) + return 46; + else + abort (); + default: + break; + } + return REG_NONE; +} + +static int +lookup_specifier (const char *name) +{ + if (strchr (name, '%')) + { + if (strstr (name, "AR[K%]") != NULL) + return IA64_RS_AR_K; + if (strstr (name, "AR[UNAT]") != NULL) + return IA64_RS_AR_UNAT; + if (strstr (name, "AR%, % in 8") != NULL) + return IA64_RS_AR; + if (strstr (name, "AR%, % in 48") != NULL) + return IA64_RS_ARb; + if (strstr (name, "BR%") != NULL) + return IA64_RS_BR; + if (strstr (name, "CR[IRR%]") != NULL) + return IA64_RS_CR_IRR; + if (strstr (name, "CR[LRR%]") != NULL) + return IA64_RS_CR_LRR; + if (strstr (name, "CR%") != NULL) + return IA64_RS_CR; + if (strstr (name, "FR%, % in 0") != NULL) + return IA64_RS_FR; + if (strstr (name, "FR%, % in 2") != NULL) + return IA64_RS_FRb; + if (strstr (name, "GR%") != NULL) + return IA64_RS_GR; + if (strstr (name, "PR%, % in 1 ") != NULL) + return IA64_RS_PR; + if (strstr (name, "PR%, % in 16 ") != NULL) + return IA64_RS_PRr; + + warn (_("don't know how to specify %% dependency %s\n"), + name); + } + else if (strchr (name, '#')) + { + if (strstr (name, "CPUID#") != NULL) + return IA64_RS_CPUID; + if (strstr (name, "DBR#") != NULL) + return IA64_RS_DBR; + if (strstr (name, "IBR#") != NULL) + return IA64_RS_IBR; + if (strstr (name, "MSR#") != NULL) + return IA64_RS_MSR; + if (strstr (name, "PKR#") != NULL) + return IA64_RS_PKR; + if (strstr (name, "PMC#") != NULL) + return IA64_RS_PMC; + if (strstr (name, "PMD#") != NULL) + return IA64_RS_PMD; + if (strstr (name, "RR#") != NULL) + return IA64_RS_RR; + + warn (_("Don't know how to specify # dependency %s\n"), + name); + } + else if (strncmp (name, "AR[FPSR]", 8) == 0) + return IA64_RS_AR_FPSR; + else if (strncmp (name, "AR[", 3) == 0) + return IA64_RS_ARX; + else if (strncmp (name, "CR[", 3) == 0) + return IA64_RS_CRX; + else if (strncmp (name, "PSR.", 4) == 0) + return IA64_RS_PSR; + else if (strcmp (name, "InService*") == 0) + return IA64_RS_INSERVICE; + else if (strcmp (name, "GR0") == 0) + return IA64_RS_GR0; + else if (strcmp (name, "CFM") == 0) + return IA64_RS_CFM; + else if (strcmp (name, "PR63") == 0) + return IA64_RS_PR63; + else if (strcmp (name, "RSE") == 0) + return IA64_RS_RSE; + + return IA64_RS_ANY; +} + +static void +print_dependency_table () +{ + int i, j; + + if (debug) + { + for (i=0;i < iclen;i++) + { + if (ics[i]->is_class) + { + if (!ics[i]->nsubs) + { + if (ics[i]->comment) + warn (_("IC:%s [%s] has no terminals or sub-classes\n"), + ics[i]->name, ics[i]->comment); + else + warn (_("IC:%s has no terminals or sub-classes\n"), + ics[i]->name); + } + } + else + { + if (!ics[i]->terminal_resolved && !ics[i]->orphan) + { + if (ics[i]->comment) + warn (_("no insns mapped directly to terminal IC %s [%s]"), + ics[i]->name, ics[i]->comment); + else + warn (_("no insns mapped directly to terminal IC %s\n"), + ics[i]->name); + } + } + } + + for (i = 0; i < iclen; i++) + { + if (ics[i]->orphan) + { + mark_used (ics[i], 1); + warn (_("class %s is defined but not used\n"), + ics[i]->name); + } + } + + if (debug > 1) + for (i = 0; i < rdepslen; i++) + { + static const char *mode_str[] = { "RAW", "WAW", "WAR" }; + + if (rdeps[i]->total_chks == 0) + warn (_("Warning: rsrc %s (%s) has no chks%s\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode], + rdeps[i]->total_regs ? "" : " or regs"); + else if (rdeps[i]->total_regs == 0) + warn (_("rsrc %s (%s) has no regs\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } + } + + /* The dependencies themselves. */ + printf ("static const struct ia64_dependency\ndependencies[] = {\n"); + for (i = 0; i < rdepslen; i++) + { + /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual + resource used. */ + int specifier = lookup_specifier (rdeps[i]->name); + int regindex = lookup_regindex (rdeps[i]->name, specifier); + + printf (" { \"%s\", %d, %d, %d, %d, ", + rdeps[i]->name, specifier, + (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); + if (rdeps[i]->semantics == IA64_DVS_OTHER) + { + const char *quote, *rest; + + putchar ('\"'); + rest = rdeps[i]->extra; + quote = strchr (rest, '\"'); + while (quote != NULL) + { + printf ("%.*s\\\"", (int) (quote - rest), rest); + rest = quote + 1; + quote = strchr (rest, '\"'); + } + printf ("%s\", ", rest); + } + else + printf ("NULL, "); + printf("},\n"); + } + printf ("};\n\n"); + + /* And dependency lists. */ + for (i=0;i < dlistlen;i++) + { + int len = 2; + printf ("static const unsigned short dep%d[] = {\n ", i); + for (j=0;j < dlists[i]->len; j++) + { + len += printf ("%d, ", dlists[i]->deps[j]); + if (len > 75) + { + printf("\n "); + len = 2; + } + } + printf ("\n};\n\n"); + } + + /* And opcode dependency list. */ + printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); + printf ("static const struct ia64_opcode_dependency\n"); + printf ("op_dependencies[] = {\n"); + for (i = 0; i < opdeplen; i++) + { + printf (" { "); + if (opdeps[i]->chk == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); + if (opdeps[i]->reg == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); + printf ("},\n"); + } + printf ("};\n\n"); +} + + +/* Add STR to the string table. */ +static struct string_entry * +insert_string (char *str) +{ + int start = 0, end = strtablen; + int i, x; + + if (strtablen == strtabtotlen) + { + strtabtotlen += 20; + string_table = (struct string_entry **) + xrealloc (string_table, + sizeof (struct string_entry **) * strtabtotlen); + } + + if (strtablen == 0) + { + strtablen = 1; + string_table[0] = tmalloc (struct string_entry); + string_table[0]->s = xstrdup (str); + string_table[0]->num = 0; + return string_table[0]; + } + + if (strcmp (str, string_table[strtablen - 1]->s) > 0) + i = end; + else if (strcmp (str, string_table[0]->s) < 0) + i = 0; + else + { + while (1) + { + int c; + + i = (start + end) / 2; + c = strcmp (str, string_table[i]->s); + + if (c < 0) + end = i - 1; + else if (c == 0) + return string_table[i]; + else + start = i + 1; + + if (start > end) + break; + } + } + + for (; i > 0 && i < strtablen; i--) + if (strcmp (str, string_table[i - 1]->s) > 0) + break; + + for (; i < strtablen; i++) + if (strcmp (str, string_table[i]->s) < 0) + break; + + for (x = strtablen - 1; x >= i; x--) + { + string_table[x + 1] = string_table[x]; + string_table[x + 1]->num = x + 1; + } + + string_table[i] = tmalloc (struct string_entry); + string_table[i]->s = xstrdup (str); + string_table[i]->num = i; + strtablen++; + + return string_table[i]; +} + +static struct bittree * +make_bittree_entry (void) +{ + struct bittree *res = tmalloc (struct bittree); + + res->disent = NULL; + res->bits[0] = NULL; + res->bits[1] = NULL; + res->bits[2] = NULL; + res->skip_flag = 0; + res->bits_to_skip = 0; + return res; +} + + +static struct disent * +add_dis_table_ent (which, insn, order, completer_index) + struct disent *which; + int insn; + int order; + int completer_index; +{ + int ci = 0; + struct disent *ent; + + if (which != NULL) + { + ent = which; + + ent->nextcnt++; + while (ent->nexte != NULL) + ent = ent->nexte; + + ent = (ent->nexte = tmalloc (struct disent)); + } + else + { + ent = tmalloc (struct disent); + ent->next_ent = disinsntable; + disinsntable = ent; + which = ent; + } + ent->nextcnt = 0; + ent->nexte = NULL; + ent->insn = insn; + ent->priority = order; + + while (completer_index != 1) + { + ci = (ci << 1) | (completer_index & 1); + completer_index >>= 1; + } + ent->completer_index = ci; + return which; +} + +static void +finish_distable () +{ + struct disent *ent = disinsntable; + struct disent *prev = ent; + + ent->ournum = 32768; + while ((ent = ent->next_ent) != NULL) + { + ent->ournum = prev->ournum + prev->nextcnt + 1; + prev = ent; + } +} + +static void +insert_bit_table_ent (curr_ent, bit, opcode, mask, + opcodenum, order, completer_index) + struct bittree *curr_ent; + int bit; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + int order; + int completer_index; +{ + ia64_insn m; + int b; + struct bittree *next; + + if (bit == -1) + { + struct disent *nent = add_dis_table_ent (curr_ent->disent, + opcodenum, order, + completer_index); + curr_ent->disent = nent; + return; + } + + m = ((ia64_insn) 1) << bit; + + if (mask & m) + b = (opcode & m) ? 1 : 0; + else + b = 2; + + next = curr_ent->bits[b]; + if (next == NULL) + { + next = make_bittree_entry (); + curr_ent->bits[b] = next; + } + insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, + completer_index); +} + +static void +add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) + struct bittree *first; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + struct completer_entry *ent; + int completer_index; +{ + if (completer_index & (1 << 20)) + abort (); + + while (ent != NULL) + { + ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; + add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, + (completer_index << 1) | 1); + + if (ent->is_terminal) + { + insert_bit_table_ent (bittree, 40, newopcode, mask, + opcodenum, opcode_count - ent->order - 1, + (completer_index << 1) | 1); + } + completer_index <<= 1; + ent = ent->alternative; + } +} + +/* This optimization pass combines multiple "don't care" nodes. */ +static void +compact_distree (ent) + struct bittree *ent; +{ +#define IS_SKIP(ent) \ + ((ent->bits[2] !=NULL) \ + && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0)) + + int bitcnt = 0; + struct bittree *nent = ent; + int x; + + while (IS_SKIP (nent)) + { + bitcnt++; + nent = nent->bits[2]; + } + + if (bitcnt) + { + struct bittree *next = ent->bits[2]; + + ent->bits[0] = nent->bits[0]; + ent->bits[1] = nent->bits[1]; + ent->bits[2] = nent->bits[2]; + ent->disent = nent->disent; + ent->skip_flag = 1; + ent->bits_to_skip = bitcnt; + while (next != nent) + { + struct bittree *b = next; + next = next->bits[2]; + free (b); + } + free (nent); + } + + for (x = 0; x < 3; x++) + { + struct bittree *i = ent->bits[x]; + + if (i != NULL) + compact_distree (i); + } +} + +static unsigned char *insn_list; +static int insn_list_len = 0; +static int tot_insn_list_len = 0; + +/* Generate the disassembler state machine corresponding to the tree + in ENT. */ +static void +gen_dis_table (ent) + struct bittree *ent; +{ + int x; + int our_offset = insn_list_len; + int bitsused = 5; + int totbits = bitsused; + int needed_bytes; + int zero_count = 0; + int zero_dest = 0; /* Initialize this with 0 to keep gcc quiet... */ + + /* If this is a terminal entry, there's no point in skipping any + bits. */ + if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && + ent->bits[2] == NULL) + { + if (ent->disent == NULL) + abort (); + else + ent->skip_flag = 0; + } + + /* Calculate the amount of space needed for this entry, or at least + a conservatively large approximation. */ + if (ent->skip_flag) + totbits += 5; + + for (x = 1; x < 3; x++) + if (ent->bits[x] != NULL) + totbits += 16; + + if (ent->disent != NULL) + { + if (ent->bits[2] != NULL) + abort (); + + totbits += 16; + } + + /* Now allocate the space. */ + needed_bytes = (totbits + 7) / 8; + if ((needed_bytes + insn_list_len) > tot_insn_list_len) + { + tot_insn_list_len += 256; + insn_list = (unsigned char *) xrealloc (insn_list, tot_insn_list_len); + } + our_offset = insn_list_len; + insn_list_len += needed_bytes; + memset (insn_list + our_offset, 0, needed_bytes); + + /* Encode the skip entry by setting bit 6 set in the state op field, + and store the # of bits to skip immediately after. */ + if (ent->skip_flag) + { + bitsused += 5; + insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf); + insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6); + } + +#define IS_ONLY_IFZERO(ENT) \ + ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \ + && (ENT)->disent == NULL && (ENT)->skip_flag == 0) + + /* Store an "if (bit is zero)" instruction by setting bit 7 in the + state op field. */ + if (ent->bits[0] != NULL) + { + struct bittree *nent = ent->bits[0]; + zero_count = 0; + + insn_list[our_offset] |= 0x80; + + /* We can encode sequences of multiple "if (bit is zero)" tests + by storing the # of zero bits to check in the lower 3 bits of + the instruction. However, this only applies if the state + solely tests for a zero bit. */ + + if (IS_ONLY_IFZERO (ent)) + { + while (IS_ONLY_IFZERO (nent) && zero_count < 7) + { + nent = nent->bits[0]; + zero_count++; + } + + insn_list[our_offset + 0] |= zero_count; + } + zero_dest = insn_list_len; + gen_dis_table (nent); + } + + /* Now store the remaining tests. We also handle a sole "termination + entry" by storing it as an "any bit" test. */ + + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL)) + { + struct bittree *i = ent->bits[x]; + int idest; + int currbits = 15; + + if (i != NULL) + { + /* If the instruction being branched to only consists of + a termination entry, use the termination entry as the + place to branch to instead. */ + if (i->bits[0] == NULL && i->bits[1] == NULL + && i->bits[2] == NULL && i->disent != NULL) + { + idest = i->disent->ournum; + i = NULL; + } + else + idest = insn_list_len - our_offset; + } + else + idest = ent->disent->ournum; + + /* If the destination offset for the if (bit is 1) test is less + than 256 bytes away, we can store it as 8-bits instead of 16; + the instruction has bit 5 set for the 16-bit address, and bit + 4 for the 8-bit address. Since we've already allocated 16 + bits for the address we need to deallocate the space. + + Note that branchings within the table are relative, and + there are no branches that branch past our instruction yet + so we do not need to adjust any other offsets. */ + if (x == 1) + { + if (idest <= 256) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 7; + totbits -= 8; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x10; + idest--; + } + else + insn_list[our_offset] |= 0x20; + } + else + { + /* An instruction which solely consists of a termination + marker and whose disassembly name index is < 4096 + can be stored in 16 bits. The encoding is slightly + odd; the upper 4 bits of the instruction are 0x3, and + bit 3 loses its normal meaning. */ + + if (ent->bits[0] == NULL && ent->bits[1] == NULL + && ent->bits[2] == NULL && ent->skip_flag == 0 + && ent->disent != NULL + && ent->disent->ournum < (32768 + 4096)) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 11; + totbits -= 5; + bitsused--; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x30; + idest &= ~32768; + } + else + insn_list[our_offset] |= 0x08; + } + + if (debug) + { + int id = idest; + + if (i == NULL) + id |= 32768; + else if (! (id & 32768)) + id += our_offset; + + if (x == 1) + printf ("%d: if (1) goto %d\n", our_offset, id); + else + printf ("%d: try %d\n", our_offset, id); + } + + /* Store the address of the entry being branched to. */ + while (currbits >= 0) + { + unsigned char *byte = insn_list + our_offset + bitsused / 8; + + if (idest & (1 << currbits)) + *byte |= (1 << (7 - (bitsused % 8))); + + bitsused++; + currbits--; + } + + /* Now generate the states for the entry being branched to. */ + if (i != NULL) + gen_dis_table (i); + } + } + + if (debug) + { + if (ent->skip_flag) + printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); + + if (ent->bits[0] != NULL) + printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, + zero_dest); + } + + if (bitsused != totbits) + abort (); +} + +static void +print_dis_table (void) +{ + int x; + struct disent *cent = disinsntable; + + printf ("static const char dis_table[] = {\n"); + for (x = 0; x < insn_list_len; x++) + { + if ((x > 0) && ((x % 12) == 0)) + printf ("\n"); + + printf ("0x%02x, ", insn_list[x]); + } + printf ("\n};\n\n"); + + printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n"); + while (cent != NULL) + { + struct disent *ent = cent; + + while (ent != NULL) + { + printf ("{ 0x%x, %d, %d, %d },\n", ent->completer_index, + ent->insn, (ent->nexte != NULL ? 1 : 0), + ent->priority); + ent = ent->nexte; + } + cent = cent->next_ent; + } + printf ("};\n\n"); +} + +static void +generate_disassembler (void) +{ + int i; + + bittree = make_bittree_entry (); + + for (i = 0; i < otlen; i++) + { + struct main_entry *ptr = ordered_table[i]; + + if (ptr->opcode->type != IA64_TYPE_DYN) + add_dis_entry (bittree, + ptr->opcode->opcode, ptr->opcode->mask, + ptr->main_index, + ptr->completers, 1); + } + + compact_distree (bittree); + finish_distable (); + gen_dis_table (bittree); + + print_dis_table (); +} + +static void +print_string_table (void) +{ + int x; + char lbuf[80], buf[80]; + int blen = 0; + + printf ("static const char * const ia64_strings[] = {\n"); + lbuf[0] = '\0'; + + for (x = 0; x < strtablen; x++) + { + int len; + + if (strlen (string_table[x]->s) > 75) + abort (); + + sprintf (buf, " \"%s\",", string_table[x]->s); + len = strlen (buf); + + if ((blen + len) > 75) + { + printf (" %s\n", lbuf); + lbuf[0] = '\0'; + blen = 0; + } + strcat (lbuf, buf); + blen += len; + } + + if (blen > 0) + printf (" %s\n", lbuf); + + printf ("};\n\n"); +} + +static struct completer_entry **glist; +static int glistlen = 0; +static int glisttotlen = 0; + +/* If the completer trees ENT1 and ENT2 are equal, return 1. */ + +static int +completer_entries_eq (ent1, ent2) + struct completer_entry *ent1, *ent2; +{ + while (ent1 != NULL && ent2 != NULL) + { + if (ent1->name->num != ent2->name->num + || ent1->bits != ent2->bits + || ent1->mask != ent2->mask + || ent1->is_terminal != ent2->is_terminal + || ent1->dependencies != ent2->dependencies + || ent1->order != ent2->order) + return 0; + + if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) + return 0; + + ent1 = ent1->alternative; + ent2 = ent2->alternative; + } + + return ent1 == ent2; +} + +/* Insert ENT into the global list of completers and return it. If an + equivalent entry (according to completer_entries_eq) already exists, + it is returned instead. */ +static struct completer_entry * +insert_gclist (struct completer_entry *ent) +{ + if (ent != NULL) + { + int i; + int x; + int start = 0, end; + + ent->addl_entries = insert_gclist (ent->addl_entries); + ent->alternative = insert_gclist (ent->alternative); + + i = glistlen / 2; + end = glistlen; + + if (glisttotlen == glistlen) + { + glisttotlen += 20; + glist = (struct completer_entry **) + xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); + } + + if (glistlen == 0) + { + glist[0] = ent; + glistlen = 1; + return ent; + } + + if (ent->name->num < glist[0]->name->num) + i = 0; + else if (ent->name->num > glist[end - 1]->name->num) + i = end; + else + { + int c; + + while (1) + { + i = (start + end) / 2; + c = ent->name->num - glist[i]->name->num; + + if (c < 0) + end = i - 1; + else if (c == 0) + { + while (i > 0 + && ent->name->num == glist[i - 1]->name->num) + i--; + + break; + } + else + start = i + 1; + + if (start > end) + break; + } + + if (c == 0) + { + while (i < glistlen) + { + if (ent->name->num != glist[i]->name->num) + break; + + if (completer_entries_eq (ent, glist[i])) + return glist[i]; + + i++; + } + } + } + + for (; i > 0 && i < glistlen; i--) + if (ent->name->num >= glist[i - 1]->name->num) + break; + + for (; i < glistlen; i++) + if (ent->name->num < glist[i]->name->num) + break; + + for (x = glistlen - 1; x >= i; x--) + glist[x + 1] = glist[x]; + + glist[i] = ent; + glistlen++; + } + return ent; +} + +static int +get_prefix_len (name) + const char *name; +{ + char *c; + + if (name[0] == '\0') + return 0; + + c = strchr (name, '.'); + if (c != NULL) + return c - name; + else + return strlen (name); +} + +static void +compute_completer_bits (ment, ent) + struct main_entry *ment; + struct completer_entry *ent; +{ + while (ent != NULL) + { + compute_completer_bits (ment, ent->addl_entries); + + if (ent->is_terminal) + { + ia64_insn mask = 0; + ia64_insn our_bits = ent->bits; + struct completer_entry *p = ent->parent; + ia64_insn p_bits; + int x; + + while (p != NULL && ! p->is_terminal) + p = p->parent; + + if (p != NULL) + p_bits = p->bits; + else + p_bits = ment->opcode->opcode; + + for (x = 0; x < 64; x++) + { + ia64_insn m = ((ia64_insn) 1) << x; + + if ((p_bits & m) != (our_bits & m)) + mask |= m; + else + our_bits &= ~m; + } + ent->bits = our_bits; + ent->mask = mask; + } + else + { + ent->bits = 0; + ent->mask = 0; + } + + ent = ent->alternative; + } +} + +/* Find identical completer trees that are used in different + instructions and collapse their entries. */ +static void +collapse_redundant_completers (void) +{ + struct main_entry *ptr; + int x; + + for (ptr = maintable; ptr != NULL; ptr = ptr->next) + { + if (ptr->completers == NULL) + abort (); + + compute_completer_bits (ptr, ptr->completers); + ptr->completers = insert_gclist (ptr->completers); + } + + /* The table has been finalized, now number the indexes. */ + for (x = 0; x < glistlen; x++) + glist[x]->num = x; +} + + +/* Attach two lists of dependencies to each opcode. + 1) all resources which, when already marked in use, conflict with this + opcode (chks) + 2) all resources which must be marked in use when this opcode is used + (regs). */ +static int +insert_opcode_dependencies (opc, cmp) + struct ia64_opcode *opc; + struct completer_entry *cmp ATTRIBUTE_UNUSED; +{ + /* Note all resources which point to this opcode. rfi has the most chks + (79) and cmpxchng has the most regs (54) so 100 here should be enough. */ + int i; + int nregs = 0; + unsigned short regs[256]; + int nchks = 0; + unsigned short chks[256]; + /* Flag insns for which no class matched; there should be none. */ + int no_class_found = 1; + + for (i = 0; i < rdepslen; i++) + { + struct rdep *rs = rdeps[i]; + int j; + + if (strcmp (opc->name, "cmp.eq.and") == 0 + && strncmp (rs->name, "PR%", 3) == 0 + && rs->mode == 1) + no_class_found = 99; + + for (j=0; j < rs->nregs;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources. */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->regnotes[j] != 0 + && ic_note != rs->regnotes[j] + && !(ic_note == 11 && rs->regnotes[j] == 1)) + warn (_("IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"), + ic_note, opc->name, ics[rs->regs[j]]->name, + rs->name, rs->regnotes[j]); + /* Instruction class notes override resource notes. + So far, only note 11 applies to an IC instead of a resource, + and note 11 implies note 1. */ + if (ic_note) + regs[nregs++] = RDEP(ic_note, i); + else + regs[nregs++] = RDEP(rs->regnotes[j], i); + no_class_found = 0; + ++rs->total_regs; + } + } + + for (j = 0; j < rs->nchks; j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources. */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->chknotes[j] != 0 + && ic_note != rs->chknotes[j] + && !(ic_note == 11 && rs->chknotes[j] == 1)) + warn (_("IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"), + ic_note, opc->name, ics[rs->chks[j]]->name, + rs->name, rs->chknotes[j]); + if (ic_note) + chks[nchks++] = RDEP(ic_note, i); + else + chks[nchks++] = RDEP(rs->chknotes[j], i); + no_class_found = 0; + ++rs->total_chks; + } + } + } + + if (no_class_found) + warn (_("opcode %s has no class (ops %d %d %d)\n"), + opc->name, + opc->operands[0], opc->operands[1], opc->operands[2]); + + return insert_dependencies (nchks, chks, nregs, regs); +} + +static void +insert_completer_entry (opc, tabent, order) + struct ia64_opcode *opc; + struct main_entry *tabent; + int order; +{ + struct completer_entry **ptr = &tabent->completers; + struct completer_entry *parent = NULL; + char pcopy[129], *prefix; + int at_end = 0; + + if (strlen (opc->name) > 128) + abort (); + + strcpy (pcopy, opc->name); + prefix = pcopy + get_prefix_len (pcopy); + + if (prefix[0] != '\0') + prefix++; + + while (! at_end) + { + int need_new_ent = 1; + int plen = get_prefix_len (prefix); + struct string_entry *sent; + + at_end = (prefix[plen] == '\0'); + prefix[plen] = '\0'; + sent = insert_string (prefix); + + while (*ptr != NULL) + { + int cmpres = sent->num - (*ptr)->name->num; + + if (cmpres == 0) + { + need_new_ent = 0; + break; + } + else + ptr = &((*ptr)->alternative); + } + + if (need_new_ent) + { + struct completer_entry *nent = tmalloc (struct completer_entry); + + nent->name = sent; + nent->parent = parent; + nent->addl_entries = NULL; + nent->alternative = *ptr; + *ptr = nent; + nent->is_terminal = 0; + nent->dependencies = -1; + } + + if (! at_end) + { + parent = *ptr; + ptr = &((*ptr)->addl_entries); + prefix += plen + 1; + } + } + + if ((*ptr)->is_terminal) + abort (); + + (*ptr)->is_terminal = 1; + (*ptr)->mask = (ia64_insn)-1; + (*ptr)->bits = opc->opcode; + (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); + (*ptr)->order = order; +} + +static void +print_completer_entry (ent) + struct completer_entry *ent; +{ + int moffset = 0; + ia64_insn mask = ent->mask, bits = ent->bits; + + if (mask != 0) + { + while (! (mask & 1)) + { + moffset++; + mask = mask >> 1; + bits = bits >> 1; + } + + if (bits & 0xffffffff00000000LL) + abort (); + } + + printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", + (int)bits, + (int)mask, + ent->name->num, + ent->alternative != NULL ? ent->alternative->num : -1, + ent->addl_entries != NULL ? ent->addl_entries->num : -1, + moffset, + ent->is_terminal ? 1 : 0, + ent->dependencies); +} + +static void +print_completer_table () +{ + int x; + + printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); + for (x = 0; x < glistlen; x++) + print_completer_entry (glist[x]); + printf ("};\n\n"); +} + +static int +opcodes_eq (opc1, opc2) + struct ia64_opcode *opc1; + struct ia64_opcode *opc2; +{ + int x; + int plen1, plen2; + + if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) + || (opc1->num_outputs != opc2->num_outputs) + || (opc1->flags != opc2->flags)) + return 0; + + for (x = 0; x < 5; x++) + if (opc1->operands[x] != opc2->operands[x]) + return 0; + + plen1 = get_prefix_len (opc1->name); + plen2 = get_prefix_len (opc2->name); + + if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) + return 1; + + return 0; +} + +static void +add_opcode_entry (opc) + struct ia64_opcode *opc; +{ + struct main_entry **place; + struct string_entry *name; + char prefix[129]; + int found_it = 0; + + if (strlen (opc->name) > 128) + abort (); + + place = &maintable; + strcpy (prefix, opc->name); + prefix[get_prefix_len (prefix)] = '\0'; + name = insert_string (prefix); + + /* Walk the list of opcode table entries. If it's a new + instruction, allocate and fill in a new entry. Note + the main table is alphabetical by opcode name. */ + + while (*place != NULL) + { + if ((*place)->name->num == name->num + && opcodes_eq ((*place)->opcode, opc)) + { + found_it = 1; + break; + } + if ((*place)->name->num > name->num) + break; + + place = &((*place)->next); + } + if (! found_it) + { + struct main_entry *nent = tmalloc (struct main_entry); + + nent->name = name; + nent->opcode = opc; + nent->next = *place; + nent->completers = 0; + *place = nent; + + if (otlen == ottotlen) + { + ottotlen += 20; + ordered_table = (struct main_entry **) + xrealloc (ordered_table, sizeof (struct main_entry *) * ottotlen); + } + ordered_table[otlen++] = nent; + } + + insert_completer_entry (opc, *place, opcode_count++); +} + +static void +print_main_table (void) +{ + struct main_entry *ptr = maintable; + int index = 0; + + printf ("static const struct ia64_main_table\nmain_table[] = {\n"); + while (ptr != NULL) + { + printf (" { %d, %d, %d, 0x", + ptr->name->num, + ptr->opcode->type, + ptr->opcode->num_outputs); + opcode_fprintf_vma (stdout, ptr->opcode->opcode); + printf ("ull, 0x"); + opcode_fprintf_vma (stdout, ptr->opcode->mask); + printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", + ptr->opcode->operands[0], + ptr->opcode->operands[1], + ptr->opcode->operands[2], + ptr->opcode->operands[3], + ptr->opcode->operands[4], + ptr->opcode->flags, + ptr->completers->num); + + ptr->main_index = index++; + + ptr = ptr->next; + } + printf ("};\n\n"); +} + +static void +shrink (table) + struct ia64_opcode *table; +{ + int curr_opcode; + + for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) + { + add_opcode_entry (table + curr_opcode); + if (table[curr_opcode].num_outputs == 2 + && ((table[curr_opcode].operands[0] == IA64_OPND_P1 + && table[curr_opcode].operands[1] == IA64_OPND_P2) + || (table[curr_opcode].operands[0] == IA64_OPND_P2 + && table[curr_opcode].operands[1] == IA64_OPND_P1))) + { + struct ia64_opcode *alias = tmalloc(struct ia64_opcode); + unsigned i; + + *alias = table[curr_opcode]; + for (i = 2; i < NELEMS (alias->operands); ++i) + alias->operands[i - 1] = alias->operands[i]; + alias->operands[NELEMS (alias->operands) - 1] = IA64_OPND_NIL; + --alias->num_outputs; + alias->flags |= PSEUDO; + add_opcode_entry (alias); + } + } +} + + +/* Program options. */ +#define OPTION_SRCDIR 200 + +struct option long_options[] = +{ + {"srcdir", required_argument, NULL, OPTION_SRCDIR}, + {"debug", no_argument, NULL, 'd'}, + {"version", no_argument, NULL, 'V'}, + {"help", no_argument, NULL, 'h'}, + {0, no_argument, NULL, 0} +}; + +static void +print_version (void) +{ + printf ("%s: version 1.0\n", program_name); + xexit (0); +} + +static void +usage (FILE * stream, int status) +{ + fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n", + program_name); + xexit (status); +} + +int +main (int argc, char **argv) +{ + extern int chdir (char *); + char *srcdir = NULL; + int c; + + program_name = *argv; + xmalloc_set_program_name (program_name); + + while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF) + switch (c) + { + case OPTION_SRCDIR: + srcdir = optarg; + break; + case 'V': + case 'v': + print_version (); + break; + case 'd': + debug = 1; + break; + case 'h': + case '?': + usage (stderr, 0); + default: + case 0: + break; + } + + if (optind != argc) + usage (stdout, 1); + + if (srcdir != NULL) + if (chdir (srcdir) != 0) + fail (_("unable to change directory to \"%s\", errno = %s\n"), + srcdir, strerror (errno)); + + load_insn_classes (); + load_dependencies (); + + shrink (ia64_opcodes_a); + shrink (ia64_opcodes_b); + shrink (ia64_opcodes_f); + shrink (ia64_opcodes_i); + shrink (ia64_opcodes_m); + shrink (ia64_opcodes_x); + shrink (ia64_opcodes_d); + + collapse_redundant_completers (); + + printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); + print_string_table (); + print_dependency_table (); + print_completer_table (); + print_main_table (); + + generate_disassembler (); + + exit (0); +} diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-a.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-a.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,419 @@ +/* ia64-opc-a.c -- IA-64 `A' opcode table. + Copyright 1998, 1999, 2000, 2001, 2002, 2004 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define A IA64_TYPE_A, 1 +#define A2 IA64_TYPE_A, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ + (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ + (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) +#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) +#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mImm14 bImm14 (-1) +#define mR3a bR3a (-1) +#define mR3b bR3b (-1) +#define mTa bTa (-1) +#define mTb bTb (-1) +#define mVe bVe (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX4 bX4 (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) +#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ + (mOp | mX2a | mVe) +#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ + (mOp | mX2a | mVe | mR3a) +#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \ + (mOp | mX2a | mVe | mImm14) +#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ + (mOp | mX2a | mVe | mX4) +#define OpX2aVeX4X2b(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ + (mOp | mX2a | mVe | mX4 | mX2b) +#define OpX2TbTaC(a,b,c,d,e) \ + (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ + (mOp | mX2 | mTb | mTa | mC) +#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ + (mOp | mX2 | mTa | mC) +#define OpX2aZaZbX4(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ + (mOp | mX2a | mZa | mZb | mX4) +#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ + (mOp | mX2a | mZa | mZb | mX4 | mX2b) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_a[] = + { + /* A-type instruction encodings (sorted according to major opcode). */ + + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY}, + {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY}, + {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY}, + {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY}, + {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY}, + /* A mov immediate pseudo for adds was deleted. It failed for immediate + operands requiring relocs, e.g. @pltoff(a). */ + {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY}, + {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY}, + {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMPTY}, + {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMPTY}, + {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMPTY}, + {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMPTY}, + {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMPTY}, + {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, + {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMPTY}, + {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMPTY}, + {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMPTY}, + {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMPTY}, + {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMPTY}, + {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY}, + {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY}, + {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMPTY}, + {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMPTY}, + {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, + {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPTY}, + {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPTY}, + {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPTY}, + {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPTY}, + {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMPTY}, + {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMPTY}, + + {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL}, + {"addl", A, Op (9), {R1, IMM22, R3_2}, EMPTY}, + + {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EMPTY}, + {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EMPTY}, + {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}, EMPTY}, + {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}, EMPTY}, + {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPTY}, + {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EMPTY}, + {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EMPTY}, + {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPTY}, + {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, EMPTY}, + {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}, EMPTY}, + {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}, EMPTY}, + {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, EMPTY}, + {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef A +#undef A2 +#undef bC +#undef bImm14 +#undef bR3a +#undef bR3b +#undef bTa +#undef bTb +#undef bVe +#undef bX +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX4 +#undef bZa +#undef bZb +#undef mC +#undef mImm14 +#undef mR3a +#undef mR3b +#undef mTa +#undef mTb +#undef mVe +#undef mX +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX4 +#undef mZa +#undef mZb +#undef OpR3a +#undef OpR3b +#undef OpX2aVe +#undef OpX2aVeImm14 +#undef OpX2aVeX4 +#undef OpX2aVeX4X2b +#undef OpX2TbTaC +#undef OpX2TaC +#undef OpX2aZaZbX4 +#undef OpX2aZaZbX4X2b +#undef EMPTY diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-b.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-b.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,512 @@ +/* ia64-opc-b.c -- IA-64 `B' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2006 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define B0 IA64_TYPE_B, 0 +#define B IA64_TYPE_B, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) +#define bWhc(x) (((ia64_insn) ((x) & 0x7)) << 32) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mIh bIh (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mWha bWha (-1) +#define mWhb bWhb (-1) +#define mWhc bWhc (-1) +#define mX6 bX6 (-1) + +#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpPaWhcD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWhc (c) | bD (d)), (mOp | mPa | mWhc | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) +#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD) +#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) +#define OpIhWhb(a,b,c) \ + (bOp (a) | bIh (b) | bWhb (c)), \ + (mOp | mIh | mWhb) +#define OpX6IhWhb(a,b,c,d) \ + (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ + (mOp | mX6 | mIh | mWhb) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_b[] = + { + /* B-type instruction encodings (sorted according to major opcode) */ + +#define BR(a,b) \ + B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO, 0, NULL + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, EMPTY +#define BRP(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, PSEUDO, 0, NULL +#define BRT(a,b,c,d,e,f) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, f, 0, NULL + {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk", BRP (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.cond.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, + {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt", BRP (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.cond.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, + {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk", BRP (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.cond.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, + {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt", BRP (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.cond.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, + {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.sptk", BRP (0x20, 0, 0, 0, 0)}, + {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, + {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.spnt", BRP (0x20, 0, 0, 1, 0)}, + {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, + {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.dptk", BRP (0x20, 0, 0, 2, 0)}, + {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, + {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.dpnt", BRP (0x20, 0, 0, 3, 0)}, + {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, + {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk", BRP (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, + {"br.ia.sptk.clr", BRP (0x20, 1, 0, 0, 1)}, + {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt", BRP (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, + {"br.ia.spnt.clr", BRP (0x20, 1, 0, 1, 1)}, + {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk", BRP (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, + {"br.ia.dptk.clr", BRP (0x20, 1, 0, 2, 1)}, + {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt", BRP (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, + {"br.ia.dpnt.clr", BRP (0x20, 1, 0, 3, 1)}, + {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, + {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, + {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, + {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, + {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, + {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, + {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, + {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, + {"br.ret.sptk.few", BRT (0x21, 4, 0, 0, 0, MOD_RRBS)}, + {"br.ret.sptk", BRT (0x21, 4, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.sptk.few.clr", BRT (0x21, 4, 0, 0, 1, MOD_RRBS)}, + {"br.ret.sptk.clr", BRT (0x21, 4, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.spnt.few", BRT (0x21, 4, 0, 1, 0, MOD_RRBS)}, + {"br.ret.spnt", BRT (0x21, 4, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.spnt.few.clr", BRT (0x21, 4, 0, 1, 1, MOD_RRBS)}, + {"br.ret.spnt.clr", BRT (0x21, 4, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.dptk.few", BRT (0x21, 4, 0, 2, 0, MOD_RRBS)}, + {"br.ret.dptk", BRT (0x21, 4, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.dptk.few.clr", BRT (0x21, 4, 0, 2, 1, MOD_RRBS)}, + {"br.ret.dptk.clr", BRT (0x21, 4, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.dpnt.few", BRT (0x21, 4, 0, 3, 0, MOD_RRBS)}, + {"br.ret.dpnt", BRT (0x21, 4, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.dpnt.few.clr", BRT (0x21, 4, 0, 3, 1, MOD_RRBS)}, + {"br.ret.dpnt.clr", BRT (0x21, 4, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.sptk.many", BRT (0x21, 4, 1, 0, 0, MOD_RRBS)}, + {"br.ret.sptk.many.clr", BRT (0x21, 4, 1, 0, 1, MOD_RRBS)}, + {"br.ret.spnt.many", BRT (0x21, 4, 1, 1, 0, MOD_RRBS)}, + {"br.ret.spnt.many.clr", BRT (0x21, 4, 1, 1, 1, MOD_RRBS)}, + {"br.ret.dptk.many", BRT (0x21, 4, 1, 2, 0, MOD_RRBS)}, + {"br.ret.dptk.many.clr", BRT (0x21, 4, 1, 2, 1, MOD_RRBS)}, + {"br.ret.dpnt.many", BRT (0x21, 4, 1, 3, 0, MOD_RRBS)}, + {"br.ret.dpnt.many.clr", BRT (0x21, 4, 1, 3, 1, MOD_RRBS)}, +#undef BR +#undef BRP +#undef BRT + + {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS, 0, NULL}, + {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, + {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, + {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED, 0, NULL}, + {"vmsw.0", B0, OpX6 (0, 0x18), {0, }, NO_PRED | PRIV, 0, NULL}, + {"vmsw.1", B0, OpX6 (0, 0x19), {0, }, NO_PRED | PRIV, 0, NULL}, + + {"break.b", B0, OpX6 (0, 0x00), {IMMU21}, EMPTY}, + + {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, EMPTY}, + {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, EMPTY}, + {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, EMPTY}, + {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, EMPTY}, + {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, EMPTY}, + {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, EMPTY}, + {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, EMPTY}, + {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, EMPTY}, + {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}, EMPTY}, + {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}, EMPTY}, + {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}, EMPTY}, + {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}, EMPTY}, + {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}, EMPTY}, + {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}, EMPTY}, + {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}, EMPTY}, + {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}, EMPTY}, + +#define BRP(a,b,c) \ + B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED, 0, NULL + {"brp.sptk", BRP (0x10, 0, 0)}, + {"brp.dptk", BRP (0x10, 0, 2)}, + {"brp.sptk.imp", BRP (0x10, 1, 0)}, + {"brp.dptk.imp", BRP (0x10, 1, 2)}, + {"brp.ret.sptk", BRP (0x11, 0, 0)}, + {"brp.ret.dptk", BRP (0x11, 0, 2)}, + {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, + {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, +#undef BRP + + {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY}, + {"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY}, + +#define BR(a,b) \ + B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, EMPTY +#define BRP(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, PSEUDO, 0, NULL + {"br.cond.sptk.few", BR (0, 0, 0)}, + {"br.cond.sptk", BRP (0, 0, 0)}, + {"br.cond.sptk.few.clr", BR (0, 0, 1)}, + {"br.cond.sptk.clr", BRP (0, 0, 1)}, + {"br.cond.spnt.few", BR (0, 1, 0)}, + {"br.cond.spnt", BRP (0, 1, 0)}, + {"br.cond.spnt.few.clr", BR (0, 1, 1)}, + {"br.cond.spnt.clr", BRP (0, 1, 1)}, + {"br.cond.dptk.few", BR (0, 2, 0)}, + {"br.cond.dptk", BRP (0, 2, 0)}, + {"br.cond.dptk.few.clr", BR (0, 2, 1)}, + {"br.cond.dptk.clr", BRP (0, 2, 1)}, + {"br.cond.dpnt.few", BR (0, 3, 0)}, + {"br.cond.dpnt", BRP (0, 3, 0)}, + {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, + {"br.cond.dpnt.clr", BRP (0, 3, 1)}, + {"br.cond.sptk.many", BR (1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (1, 0, 1)}, + {"br.cond.spnt.many", BR (1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (1, 1, 1)}, + {"br.cond.dptk.many", BR (1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (1, 2, 1)}, + {"br.cond.dpnt.many", BR (1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, + {"br.sptk.few", BR (0, 0, 0)}, + {"br.sptk", BRP (0, 0, 0)}, + {"br.sptk.few.clr", BR (0, 0, 1)}, + {"br.sptk.clr", BRP (0, 0, 1)}, + {"br.spnt.few", BR (0, 1, 0)}, + {"br.spnt", BRP (0, 1, 0)}, + {"br.spnt.few.clr", BR (0, 1, 1)}, + {"br.spnt.clr", BRP (0, 1, 1)}, + {"br.dptk.few", BR (0, 2, 0)}, + {"br.dptk", BRP (0, 2, 0)}, + {"br.dptk.few.clr", BR (0, 2, 1)}, + {"br.dptk.clr", BRP (0, 2, 1)}, + {"br.dpnt.few", BR (0, 3, 0)}, + {"br.dpnt", BRP (0, 3, 0)}, + {"br.dpnt.few.clr", BR (0, 3, 1)}, + {"br.dpnt.clr", BRP (0, 3, 1)}, + {"br.sptk.many", BR (1, 0, 0)}, + {"br.sptk.many.clr", BR (1, 0, 1)}, + {"br.spnt.many", BR (1, 1, 0)}, + {"br.spnt.many.clr", BR (1, 1, 1)}, + {"br.dptk.many", BR (1, 2, 0)}, + {"br.dptk.many.clr", BR (1, 2, 1)}, + {"br.dpnt.many", BR (1, 3, 0)}, + {"br.dpnt.many.clr", BR (1, 3, 1)}, +#undef BR +#undef BRP + +#define BR(a,b,c,d, e) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL + {"br.wexit.sptk.few", BR (2, 0, 0, 0, MOD_RRBS)}, + {"br.wexit.sptk", BR (2, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1, MOD_RRBS)}, + {"br.wexit.sptk.clr", BR (2, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.spnt.few", BR (2, 0, 1, 0, MOD_RRBS)}, + {"br.wexit.spnt", BR (2, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1, MOD_RRBS)}, + {"br.wexit.spnt.clr", BR (2, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.dptk.few", BR (2, 0, 2, 0, MOD_RRBS)}, + {"br.wexit.dptk", BR (2, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1, MOD_RRBS)}, + {"br.wexit.dptk.clr", BR (2, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.dpnt.few", BR (2, 0, 3, 0, MOD_RRBS)}, + {"br.wexit.dpnt", BR (2, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1, MOD_RRBS)}, + {"br.wexit.dpnt.clr", BR (2, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.sptk.many", BR (2, 1, 0, 0, MOD_RRBS)}, + {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1, MOD_RRBS)}, + {"br.wexit.spnt.many", BR (2, 1, 1, 0, MOD_RRBS)}, + {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1, MOD_RRBS)}, + {"br.wexit.dptk.many", BR (2, 1, 2, 0, MOD_RRBS)}, + {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1, MOD_RRBS)}, + {"br.wexit.dpnt.many", BR (2, 1, 3, 0, MOD_RRBS)}, + {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1, MOD_RRBS)}, + {"br.wtop.sptk.few", BR (3, 0, 0, 0, MOD_RRBS)}, + {"br.wtop.sptk", BR (3, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1, MOD_RRBS)}, + {"br.wtop.sptk.clr", BR (3, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.spnt.few", BR (3, 0, 1, 0, MOD_RRBS)}, + {"br.wtop.spnt", BR (3, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1, MOD_RRBS)}, + {"br.wtop.spnt.clr", BR (3, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.dptk.few", BR (3, 0, 2, 0, MOD_RRBS)}, + {"br.wtop.dptk", BR (3, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1, MOD_RRBS)}, + {"br.wtop.dptk.clr", BR (3, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.dpnt.few", BR (3, 0, 3, 0, MOD_RRBS)}, + {"br.wtop.dpnt", BR (3, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1, MOD_RRBS)}, + {"br.wtop.dpnt.clr", BR (3, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.sptk.many", BR (3, 1, 0, 0, MOD_RRBS)}, + {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1, MOD_RRBS)}, + {"br.wtop.spnt.many", BR (3, 1, 1, 0, MOD_RRBS)}, + {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1, MOD_RRBS)}, + {"br.wtop.dptk.many", BR (3, 1, 2, 0, MOD_RRBS)}, + {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1, MOD_RRBS)}, + {"br.wtop.dpnt.many", BR (3, 1, 3, 0, MOD_RRBS)}, + {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1, MOD_RRBS)}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL +#define BRT(a,b,c,d,e) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL + {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, + {"br.cloop.sptk", BRT (5, 0, 0, 0, PSEUDO)}, + {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, + {"br.cloop.sptk.clr", BRT (5, 0, 0, 1, PSEUDO)}, + {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, + {"br.cloop.spnt", BRT (5, 0, 1, 0, PSEUDO)}, + {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, + {"br.cloop.spnt.clr", BRT (5, 0, 1, 1, PSEUDO)}, + {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, + {"br.cloop.dptk", BRT (5, 0, 2, 0, PSEUDO)}, + {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, + {"br.cloop.dptk.clr", BRT (5, 0, 2, 1, PSEUDO)}, + {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, + {"br.cloop.dpnt", BRT (5, 0, 3, 0, PSEUDO)}, + {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, + {"br.cloop.dpnt.clr", BRT (5, 0, 3, 1, PSEUDO)}, + {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, + {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, + {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, + {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, + {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, + {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, + {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, + {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, + {"br.cexit.sptk.few", BRT (6, 0, 0, 0, MOD_RRBS)}, + {"br.cexit.sptk", BRT (6, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.sptk.few.clr", BRT (6, 0, 0, 1, MOD_RRBS)}, + {"br.cexit.sptk.clr", BRT (6, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.spnt.few", BRT (6, 0, 1, 0, MOD_RRBS)}, + {"br.cexit.spnt", BRT (6, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.spnt.few.clr", BRT (6, 0, 1, 1, MOD_RRBS)}, + {"br.cexit.spnt.clr", BRT (6, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.dptk.few", BRT (6, 0, 2, 0, MOD_RRBS)}, + {"br.cexit.dptk", BRT (6, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.dptk.few.clr", BRT (6, 0, 2, 1, MOD_RRBS)}, + {"br.cexit.dptk.clr", BRT (6, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.dpnt.few", BRT (6, 0, 3, 0, MOD_RRBS)}, + {"br.cexit.dpnt", BRT (6, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.dpnt.few.clr", BRT (6, 0, 3, 1, MOD_RRBS)}, + {"br.cexit.dpnt.clr", BRT (6, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.sptk.many", BRT (6, 1, 0, 0, MOD_RRBS)}, + {"br.cexit.sptk.many.clr", BRT (6, 1, 0, 1, MOD_RRBS)}, + {"br.cexit.spnt.many", BRT (6, 1, 1, 0, MOD_RRBS)}, + {"br.cexit.spnt.many.clr", BRT (6, 1, 1, 1, MOD_RRBS)}, + {"br.cexit.dptk.many", BRT (6, 1, 2, 0, MOD_RRBS)}, + {"br.cexit.dptk.many.clr", BRT (6, 1, 2, 1, MOD_RRBS)}, + {"br.cexit.dpnt.many", BRT (6, 1, 3, 0, MOD_RRBS)}, + {"br.cexit.dpnt.many.clr", BRT (6, 1, 3, 1, MOD_RRBS)}, + {"br.ctop.sptk.few", BRT (7, 0, 0, 0, MOD_RRBS)}, + {"br.ctop.sptk", BRT (7, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.sptk.few.clr", BRT (7, 0, 0, 1, MOD_RRBS)}, + {"br.ctop.sptk.clr", BRT (7, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.spnt.few", BRT (7, 0, 1, 0, MOD_RRBS)}, + {"br.ctop.spnt", BRT (7, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.spnt.few.clr", BRT (7, 0, 1, 1, MOD_RRBS)}, + {"br.ctop.spnt.clr", BRT (7, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.dptk.few", BRT (7, 0, 2, 0, MOD_RRBS)}, + {"br.ctop.dptk", BRT (7, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.dptk.few.clr", BRT (7, 0, 2, 1, MOD_RRBS)}, + {"br.ctop.dptk.clr", BRT (7, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.dpnt.few", BRT (7, 0, 3, 0, MOD_RRBS)}, + {"br.ctop.dpnt", BRT (7, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.dpnt.few.clr", BRT (7, 0, 3, 1, MOD_RRBS)}, + {"br.ctop.dpnt.clr", BRT (7, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.sptk.many", BRT (7, 1, 0, 0, MOD_RRBS)}, + {"br.ctop.sptk.many.clr", BRT (7, 1, 0, 1, MOD_RRBS)}, + {"br.ctop.spnt.many", BRT (7, 1, 1, 0, MOD_RRBS)}, + {"br.ctop.spnt.many.clr", BRT (7, 1, 1, 1, MOD_RRBS)}, + {"br.ctop.dptk.many", BRT (7, 1, 2, 0, MOD_RRBS)}, + {"br.ctop.dptk.many.clr", BRT (7, 1, 2, 1, MOD_RRBS)}, + {"br.ctop.dpnt.many", BRT (7, 1, 3, 0, MOD_RRBS)}, + {"br.ctop.dpnt.many.clr", BRT (7, 1, 3, 1, MOD_RRBS)}, +#undef BR +#undef BRT + + {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, EMPTY}, + {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, EMPTY}, + {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, EMPTY}, + {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}, EMPTY}, + {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}, EMPTY}, + + /* Branch predict. */ +#define BRP(a,b) \ + B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED, 0, NULL + {"brp.sptk", BRP (0, 0)}, + {"brp.loop", BRP (0, 1)}, + {"brp.dptk", BRP (0, 2)}, + {"brp.exit", BRP (0, 3)}, + {"brp.sptk.imp", BRP (1, 0)}, + {"brp.loop.imp", BRP (1, 1)}, + {"brp.dptk.imp", BRP (1, 2)}, + {"brp.exit.imp", BRP (1, 3)}, +#undef BRP + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef B0 +#undef B +#undef bBtype +#undef bD +#undef bIh +#undef bPa +#undef bPr +#undef bWha +#undef bWhb +#undef bWhc +#undef bX6 +#undef mBtype +#undef mD +#undef mIh +#undef mPa +#undef mPr +#undef mWha +#undef mWhb +#undef mWhc +#undef mX6 +#undef OpX6 +#undef OpPaWhaD +#undef OpPaWhcD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr +#undef OpX6BtypePaWhaD +#undef OpX6BtypePaWhaDPr +#undef OpIhWhb +#undef OpX6IhWhb +#undef EMPTY diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-d.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-d.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,34 @@ +/* ia64-opc-d.c -- IA-64 `D' opcode table. + Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +struct ia64_opcode ia64_opcodes_d[] = + { + {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}, 0, 0, NULL}, + {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}, 0, 0, NULL}, + {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0, 0, NULL}, + {"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0, NULL}, + {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-f.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-f.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,656 @@ +/* ia64-opc-f.c -- IA-64 `F' opcode table. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define f0 IA64_TYPE_F, 0 +#define f IA64_TYPE_F, 1 +#define f2 IA64_TYPE_F, 2 + +#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) +#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) +#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) + +#define mF2 bF2 (-1) +#define mF4 bF4 (-1) +#define mQ bQ (-1) +#define mRa bRa (-1) +#define mRb bRb (-1) +#define mSf bSf (-1) +#define mTa bTa (-1) +#define mXa bXa (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX6 bX6 (-1) +#define mY bY (-1) + +#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) +#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) +#define OpXaSfF2(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) +#define OpXaSfF4(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) +#define OpXaSfF2F4(a,b,c,d,e) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ + (mOp | mXa | mSf | mF2 | mF4) +#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) +#define OpXaX2F2(a,b,c,d) \ + (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) +#define OpRaRbTaSf(a,b,c,d,e) \ + (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ + (mOp | mRa | mRb | mTa | mSf) +#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) +#define OpXbQSf(a,b,c,d) \ + (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) +#define OpXbX6(a,b,c) \ + (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6Y(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY) +#define OpXbX6F2(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) +#define OpXbX6Sf(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_f[] = + { + /* F-type instruction encodings (sorted according to major opcode). */ + + {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, + {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, + {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, + {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, + + {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY}, + {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, + {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY}, + {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY}, + {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY}, + + {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, + {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, + {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, + {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, + {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, + {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, + {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, + {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, + {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, + {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, + {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, + {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, + {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, + {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, + {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, + {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, + + {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}, EMPTY}, + {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}, EMPTY}, + + {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}, EMPTY}, + {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}, EMPTY}, + {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}, EMPTY}, + {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}, EMPTY}, + {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}, EMPTY}, + {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}, EMPTY}, + {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}, EMPTY}, + {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}, EMPTY}, + {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}, EMPTY}, + {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}, EMPTY}, + {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}, EMPTY}, + {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}, EMPTY}, + {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}, EMPTY}, + {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}, EMPTY}, + + {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, EMPTY}, + {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}, EMPTY}, + {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}, EMPTY}, + {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}, EMPTY}, + {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, EMPTY}, + {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}, EMPTY}, + {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}, EMPTY}, + {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}, EMPTY}, + + {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}, EMPTY}, + + {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO, 0, NULL}, + {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}, EMPTY}, + {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0), {}, EMPTY}, + {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO, 0, NULL}, + {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1), {}, EMPTY}, + {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2), {}, EMPTY}, + {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3), {}, EMPTY}, + {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, EMPTY}, + {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO, 0, NULL}, + {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}, EMPTY}, + {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}, EMPTY}, + {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY}, + + {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY}, + {"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY}, + {"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY}, + + {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, + + {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, EMPTY}, + {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, + {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}, EMPTY}, + {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}, EMPTY}, + {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}, EMPTY}, + + {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, + {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, + {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, + {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, + {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, + {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, + {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, + {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, + {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, + {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, + {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, + {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, + {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, + {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, + {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, + {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, + + {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}, EMPTY}, + + {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}, EMPTY}, + {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}, EMPTY}, + {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}, EMPTY}, + + {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, EMPTY}, + {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}, EMPTY}, + {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}, EMPTY}, + {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, EMPTY}, + {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}, EMPTY}, + + {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, + + /* pseudo-ops of the above */ + {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, + + {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}, EMPTY}, + {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, + {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}, EMPTY}, + {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, + + /* note: fnorm and fcvt.xuf have identical encodings! */ + {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}, EMPTY}, + + {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}, EMPTY}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef f0 +#undef f +#undef f2 +#undef bF2 +#undef bF4 +#undef bQ +#undef bRa +#undef bRb +#undef bSf +#undef bTa +#undef bXa +#undef bXb +#undef bX2 +#undef bX6 +#undef mF2 +#undef mF4 +#undef mQ +#undef mRa +#undef mRb +#undef mSf +#undef mTa +#undef mXa +#undef mXb +#undef mX2 +#undef mX6 +#undef OpXa +#undef OpXaSf +#undef OpXaSfF2 +#undef OpXaSfF4 +#undef OpXaSfF2F4 +#undef OpXaX2 +#undef OpRaRbTaSf +#undef OpTa +#undef OpXbQSf +#undef OpXbX6 +#undef OpXbX6F2 +#undef OpXbX6Sf +#undef EMPTY diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-i.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-i.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,338 @@ +/* ia64-opc-i.c -- IA-64 `I' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2006 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define I0 IA64_TYPE_I, 0 +#define I IA64_TYPE_I, 1 +#define I2 IA64_TYPE_I, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) +#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) +#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) +#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) +#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mIh bIh (-1) +#define mTa bTa (-1) +#define mTag13 bTag13 (-1) +#define mTb bTb (-1) +#define mVc bVc (-1) +#define mVe bVe (-1) +#define mWh bWh (-1) +#define mX bX (-1) +#define mXb bXb (-1) +#define mXc bXc (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX2c bX2c (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mYa bYa (-1) +#define mYb bYb (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b) +#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) +#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) +#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ + (mOp | mX2 | mX | mYa) +#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ + (mOp | mX2 | mX | mYb) +#define OpX2TaTbYaC(a,b,c,d,e,f) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ + (mOp | mX2 | mTa | mTb | mYa | mC) +#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \ + (mOp | mX2 | mTa | mTb | mYa | mXc | mC) +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \ + (mOp | mX3 | mX6 | mYb) +#define OpX3XbIhWh(a,b,c,d,e) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ + (mOp | mX3 | mXb | mIh | mWh) +#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ + (mOp | mX3 | mXb | mIh | mWh | mTag13) + +#define FULL17 ((ia64_insn)0x10ff001fc0LL) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_i[] = + { + /* I-type instruction encodings (sorted according to major opcode). */ + + {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL}, + {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL}, + {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL}, + {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY}, + + {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL}, +#define MOV(a,b,c,d) \ + I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY + {"mov.sptk", MOV (7, 0, 0, 0)}, + {"mov.sptk.imp", MOV (7, 0, 1, 0)}, + {"mov", MOV (7, 0, 0, 1)}, + {"mov.imp", MOV (7, 0, 1, 1)}, + {"mov.dptk", MOV (7, 0, 0, 2)}, + {"mov.dptk.imp", MOV (7, 0, 1, 2)}, + {"mov.ret.sptk", MOV (7, 1, 0, 0)}, + {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, + {"mov.ret", MOV (7, 1, 0, 1)}, + {"mov.ret.imp", MOV (7, 1, 1, 1)}, + {"mov.ret.dptk", MOV (7, 1, 0, 2)}, + {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, +#undef MOV + {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY}, + {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY}, + /* Don't remove one of the seemingly redundant FULL17-s. */ + {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL}, + {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY}, + {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY}, + {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY}, + {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY}, + {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY}, + {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY}, + {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY}, + {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY}, + {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY}, + {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY}, + {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY}, + {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY}, + {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY}, + + {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY}, + + {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY}, + + {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY}, + + {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY}, + + {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY}, + {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY}, + {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY}, +#define TF(a,b,c) \ + I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY +#define TFCM(a,b,c) \ + I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL + {"tf.z", TF (0, 0, 0)}, + {"tf.nz", TFCM (0, 0, 0)}, + {"tf.z.unc", TF (0, 0, 1)}, + {"tf.nz.unc", TFCM (0, 0, 1)}, + {"tf.z.and", TF (0, 1, 0)}, + {"tf.nz.andcm", TFCM (0, 1, 0)}, + {"tf.nz.and", TF (0, 1, 1)}, + {"tf.z.andcm", TFCM (0, 1, 1)}, + {"tf.z.or", TF (1, 0, 0)}, + {"tf.nz.orcm", TFCM (1, 0, 0)}, + {"tf.nz.or", TF (1, 0, 1)}, + {"tf.z.orcm", TFCM (1, 0, 1)}, + {"tf.z.or.andcm", TF (1, 1, 0)}, + {"tf.nz.and.orcm", TFCM (1, 1, 0)}, + {"tf.nz.or.andcm", TF (1, 1, 1)}, + {"tf.z.and.orcm", TFCM (1, 1, 1)}, +#undef TF +#undef TFCM +#define TBIT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY +#define TBITCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL + {"tbit.z", TBIT (0, 0, 0, 0)}, + {"tbit.nz", TBITCM (0, 0, 0, 0)}, + {"tbit.z.unc", TBIT (0, 0, 0, 1)}, + {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, + {"tbit.z.and", TBIT (0, 1, 0, 0)}, + {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, + {"tbit.nz.and", TBIT (0, 1, 0, 1)}, + {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, + {"tbit.z.or", TBIT (1, 0, 0, 0)}, + {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, + {"tbit.nz.or", TBIT (1, 0, 0, 1)}, + {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, + {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, + {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, + {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, + {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, +#undef TBIT +#undef TBITCM +#define TNAT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY +#define TNATCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL + {"tnat.z", TNAT (0, 0, 1, 0)}, + {"tnat.nz", TNATCM (0, 0, 1, 0)}, + {"tnat.z.unc", TNAT (0, 0, 1, 1)}, + {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, + {"tnat.z.and", TNAT (0, 1, 1, 0)}, + {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, + {"tnat.nz.and", TNAT (0, 1, 1, 1)}, + {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, + {"tnat.z.or", TNAT (1, 0, 1, 0)}, + {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, + {"tnat.nz.or", TNAT (1, 0, 1, 1)}, + {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, + {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, + {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, + {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, + {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, +#undef TNAT +#undef TNATCM + + {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY}, + {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY}, + {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY}, + {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY}, + {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY}, + {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, + {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, + {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY}, + {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY}, + {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY}, + {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY}, + {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY}, + {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY}, + {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, + {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef I0 +#undef I +#undef I2 +#undef L +#undef bC +#undef bIh +#undef bTa +#undef bTag13 +#undef bTb +#undef bVc +#undef bVe +#undef bWh +#undef bX +#undef bXb +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX2c +#undef bX3 +#undef bX6 +#undef bY +#undef bZa +#undef bZb +#undef mC +#undef mIh +#undef mTa +#undef mTag13 +#undef mTb +#undef mVc +#undef mVe +#undef mWh +#undef mX +#undef mXb +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX2c +#undef mX3 +#undef mX6 +#undef mY +#undef mZa +#undef mZb +#undef OpZaZbVeX2aX2b +#undef OpZaZbVeX2aX2bX2c +#undef OpX2X +#undef OpX2XYa +#undef OpX2XYb +#undef OpX2TaTbYaC +#undef OpX3 +#undef OpX3X6 +#undef OpX3XbIhWh +#undef OpX3XbIhWhTag13 +#undef EMPTY diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-m.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-m.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,1118 @@ +/* ia64-opc-m.c -- IA-64 `M' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define M0 IA64_TYPE_M, 0 +#define M IA64_TYPE_M, 1 +#define M2 IA64_TYPE_M, 2 + +/* instruction bit fields: */ +#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) +#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) +#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bX7(x) (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */ +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) + +#define mM bM (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX3 bX3 (-1) +#define mX4 bX4 (-1) +#define mX6a bX6a (-1) +#define mX6b bX6b (-1) +#define mX7 bX7 (-1) +#define mY bY (-1) +#define mHint bHint (-1) + +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ + (mOp | mX3 | mX6b) +#define OpX3X6bX7(a,b,c,d) (bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \ + (mOp | mX3 | mX6b | mX7) +#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ + (mOp | mX3 | mX4) +#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ + (mOp | mX3 | mX4 | mX2) +#define OpX3X4X2Y(a,b,c,d,e) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (e)), \ + (mOp | mX3 | mX4 | mX2 | mY) +#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ + (mOp | mX6a | mHint) +#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ + (mOp | mX | mX6a | mHint) +#define OpMXX6a(a,b,c,d) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) +#define OpMXX6aHint(a,b,c,d,e) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ + (mOp | mM | mX | mX6a | mHint) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_m[] = + { + /* M-type instruction encodings (sorted according to major opcode). */ + + {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY}, + {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY}, + {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY}, + {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY}, + + {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY}, + {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY}, + {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY}, + {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY}, + {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY}, + {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3), {}, EMPTY}, + {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3), {}, EMPTY}, + {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {}, FIRST | NO_PRED, 0, NULL}, + {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {}, FIRST | NO_PRED, 0, NULL}, + {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY}, + {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}, EMPTY}, + {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY}, + + {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY}, + {"nop.m", M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY}, + {"hint.m", M0, OpX3X4X2Y (0, 0, 1, 0, 1), {IMMU21}, EMPTY}, + + {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY}, + {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY}, + {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV, 0, NULL}, + {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV, 0, NULL}, + + {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY}, + {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL}, + + {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL}, + {"alloc", M, OpX3 (1, 6), {R1, SOF, SOL, SOR}, PSEUDO|FIRST|NO_PRED|MOD_RRBS, 0, NULL}, + + {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}, EMPTY}, + {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY}, + {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY}, + {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY}, + {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY}, + {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY}, + {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY}, + {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY}, + {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL}, + {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL}, + + {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV, 0, NULL}, + {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV, 0, NULL}, + {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV, 0, NULL}, + + {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}, EMPTY}, + + {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL}, + {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL}, + {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL}, + {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV, 0, NULL}, + {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV, 0, NULL}, + + {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}, EMPTY}, + {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}, EMPTY}, + {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV, 0, NULL}, + {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV, 0, NULL}, + + {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY}, + {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY}, + + {"fc", M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY}, + {"fc.i", M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY}, + {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL}, + + /* integer load */ + {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY}, + {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}, EMPTY}, + {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}, EMPTY}, + {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}, EMPTY}, + {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}, EMPTY}, + {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}, EMPTY}, + {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}, EMPTY}, + {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}, EMPTY}, + {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}, EMPTY}, + {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}, EMPTY}, + {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY}, + {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY}, + {"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16", M, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.nt1", M, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.nta", M, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY}, + {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY}, + {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}, EMPTY}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}, EMPTY}, + {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}, EMPTY}, + {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}, EMPTY}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}, EMPTY}, + {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}, EMPTY}, + {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}, EMPTY}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}, EMPTY}, + {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}, EMPTY}, + {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}, EMPTY}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}, EMPTY}, + {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}, EMPTY}, + {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}, EMPTY}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}, EMPTY}, + {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}, EMPTY}, + {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}, EMPTY}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}, EMPTY}, + {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}, EMPTY}, + {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}, EMPTY}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}, EMPTY}, + {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}, EMPTY}, + {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}, EMPTY}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}, EMPTY}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}, EMPTY}, + {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}, EMPTY}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}, EMPTY}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}, EMPTY}, + {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}, EMPTY}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}, EMPTY}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}, EMPTY}, + {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}, EMPTY}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}, EMPTY}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}, EMPTY}, + {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}, EMPTY}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}, EMPTY}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}, EMPTY}, + {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}, EMPTY}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}, EMPTY}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}, EMPTY}, + {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}, EMPTY}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}, EMPTY}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}, EMPTY}, + {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}, EMPTY}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}, EMPTY}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}, EMPTY}, + {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}, EMPTY}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}, EMPTY}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}, EMPTY}, + {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}, EMPTY}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}, EMPTY}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}, EMPTY}, + {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}, EMPTY}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}, EMPTY}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}, EMPTY}, + {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}, EMPTY}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY}, + {"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq", M, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY}, + {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}, EMPTY}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}, EMPTY}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}, EMPTY}, + {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}, EMPTY}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}, EMPTY}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}, EMPTY}, + {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}, EMPTY}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}, EMPTY}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}, EMPTY}, + {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}, EMPTY}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}, EMPTY}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}, EMPTY}, + {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}, EMPTY}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}, EMPTY}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}, EMPTY}, + {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}, EMPTY}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}, EMPTY}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}, EMPTY}, + {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}, EMPTY}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}, EMPTY}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}, EMPTY}, + {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}, EMPTY}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}, EMPTY}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}, EMPTY}, + + /* Pseudo-op that generates ldxmov relocation. */ + {"ld8.mov", M, OpMXX6aHint (4, 0, 0, 0x03, 0), + {R1, MR3, IA64_OPND_LDXMOV}, EMPTY}, + + /* Integer load w/increment by register. */ +#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL + {"ld1", LDINCREG (0x00, 0)}, + {"ld1.nt1", LDINCREG (0x00, 1)}, + {"ld1.nta", LDINCREG (0x00, 3)}, + {"ld2", LDINCREG (0x01, 0)}, + {"ld2.nt1", LDINCREG (0x01, 1)}, + {"ld2.nta", LDINCREG (0x01, 3)}, + {"ld4", LDINCREG (0x02, 0)}, + {"ld4.nt1", LDINCREG (0x02, 1)}, + {"ld4.nta", LDINCREG (0x02, 3)}, + {"ld8", LDINCREG (0x03, 0)}, + {"ld8.nt1", LDINCREG (0x03, 1)}, + {"ld8.nta", LDINCREG (0x03, 3)}, + {"ld1.s", LDINCREG (0x04, 0)}, + {"ld1.s.nt1", LDINCREG (0x04, 1)}, + {"ld1.s.nta", LDINCREG (0x04, 3)}, + {"ld2.s", LDINCREG (0x05, 0)}, + {"ld2.s.nt1", LDINCREG (0x05, 1)}, + {"ld2.s.nta", LDINCREG (0x05, 3)}, + {"ld4.s", LDINCREG (0x06, 0)}, + {"ld4.s.nt1", LDINCREG (0x06, 1)}, + {"ld4.s.nta", LDINCREG (0x06, 3)}, + {"ld8.s", LDINCREG (0x07, 0)}, + {"ld8.s.nt1", LDINCREG (0x07, 1)}, + {"ld8.s.nta", LDINCREG (0x07, 3)}, + {"ld1.a", LDINCREG (0x08, 0)}, + {"ld1.a.nt1", LDINCREG (0x08, 1)}, + {"ld1.a.nta", LDINCREG (0x08, 3)}, + {"ld2.a", LDINCREG (0x09, 0)}, + {"ld2.a.nt1", LDINCREG (0x09, 1)}, + {"ld2.a.nta", LDINCREG (0x09, 3)}, + {"ld4.a", LDINCREG (0x0a, 0)}, + {"ld4.a.nt1", LDINCREG (0x0a, 1)}, + {"ld4.a.nta", LDINCREG (0x0a, 3)}, + {"ld8.a", LDINCREG (0x0b, 0)}, + {"ld8.a.nt1", LDINCREG (0x0b, 1)}, + {"ld8.a.nta", LDINCREG (0x0b, 3)}, + {"ld1.sa", LDINCREG (0x0c, 0)}, + {"ld1.sa.nt1", LDINCREG (0x0c, 1)}, + {"ld1.sa.nta", LDINCREG (0x0c, 3)}, + {"ld2.sa", LDINCREG (0x0d, 0)}, + {"ld2.sa.nt1", LDINCREG (0x0d, 1)}, + {"ld2.sa.nta", LDINCREG (0x0d, 3)}, + {"ld4.sa", LDINCREG (0x0e, 0)}, + {"ld4.sa.nt1", LDINCREG (0x0e, 1)}, + {"ld4.sa.nta", LDINCREG (0x0e, 3)}, + {"ld8.sa", LDINCREG (0x0f, 0)}, + {"ld8.sa.nt1", LDINCREG (0x0f, 1)}, + {"ld8.sa.nta", LDINCREG (0x0f, 3)}, + {"ld1.bias", LDINCREG (0x10, 0)}, + {"ld1.bias.nt1", LDINCREG (0x10, 1)}, + {"ld1.bias.nta", LDINCREG (0x10, 3)}, + {"ld2.bias", LDINCREG (0x11, 0)}, + {"ld2.bias.nt1", LDINCREG (0x11, 1)}, + {"ld2.bias.nta", LDINCREG (0x11, 3)}, + {"ld4.bias", LDINCREG (0x12, 0)}, + {"ld4.bias.nt1", LDINCREG (0x12, 1)}, + {"ld4.bias.nta", LDINCREG (0x12, 3)}, + {"ld8.bias", LDINCREG (0x13, 0)}, + {"ld8.bias.nt1", LDINCREG (0x13, 1)}, + {"ld8.bias.nta", LDINCREG (0x13, 3)}, + {"ld1.acq", LDINCREG (0x14, 0)}, + {"ld1.acq.nt1", LDINCREG (0x14, 1)}, + {"ld1.acq.nta", LDINCREG (0x14, 3)}, + {"ld2.acq", LDINCREG (0x15, 0)}, + {"ld2.acq.nt1", LDINCREG (0x15, 1)}, + {"ld2.acq.nta", LDINCREG (0x15, 3)}, + {"ld4.acq", LDINCREG (0x16, 0)}, + {"ld4.acq.nt1", LDINCREG (0x16, 1)}, + {"ld4.acq.nta", LDINCREG (0x16, 3)}, + {"ld8.acq", LDINCREG (0x17, 0)}, + {"ld8.acq.nt1", LDINCREG (0x17, 1)}, + {"ld8.acq.nta", LDINCREG (0x17, 3)}, + {"ld8.fill", LDINCREG (0x1b, 0)}, + {"ld8.fill.nt1", LDINCREG (0x1b, 1)}, + {"ld8.fill.nta", LDINCREG (0x1b, 3)}, + {"ld1.c.clr", LDINCREG (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCREG (0x20, 1)}, + {"ld1.c.clr.nta", LDINCREG (0x20, 3)}, + {"ld2.c.clr", LDINCREG (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCREG (0x21, 1)}, + {"ld2.c.clr.nta", LDINCREG (0x21, 3)}, + {"ld4.c.clr", LDINCREG (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCREG (0x22, 1)}, + {"ld4.c.clr.nta", LDINCREG (0x22, 3)}, + {"ld8.c.clr", LDINCREG (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCREG (0x23, 1)}, + {"ld8.c.clr.nta", LDINCREG (0x23, 3)}, + {"ld1.c.nc", LDINCREG (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCREG (0x24, 1)}, + {"ld1.c.nc.nta", LDINCREG (0x24, 3)}, + {"ld2.c.nc", LDINCREG (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCREG (0x25, 1)}, + {"ld2.c.nc.nta", LDINCREG (0x25, 3)}, + {"ld4.c.nc", LDINCREG (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCREG (0x26, 1)}, + {"ld4.c.nc.nta", LDINCREG (0x26, 3)}, + {"ld8.c.nc", LDINCREG (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCREG (0x27, 1)}, + {"ld8.c.nc.nta", LDINCREG (0x27, 3)}, + {"ld1.c.clr.acq", LDINCREG (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)}, + {"ld2.c.clr.acq", LDINCREG (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)}, + {"ld4.c.clr.acq", LDINCREG (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCREG (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, +#undef LDINCREG + + {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY}, + {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}, EMPTY}, + {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}, EMPTY}, + {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}, EMPTY}, + {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}, EMPTY}, + {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}, EMPTY}, + {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY}, + {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY}, + {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY}, + {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2}, PSEUDO, 0, NULL}, + {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2}, PSEUDO, 0, NULL}, + {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY}, + {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY}, + {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY}, + {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}, EMPTY}, + {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}, EMPTY}, + {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}, EMPTY}, + {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY}, + {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY}, + {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2}, PSEUDO, 0, NULL}, + {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2}, PSEUDO, 0, NULL}, + {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY}, + {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY}, + +#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY +#define CMPXCHG_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL +#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY +#define CMPXCHG16_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL +#define CMPXCHG_acq 0 +#define CMPXCHG_rel 4 +#define CMPXCHG_1 0 +#define CMPXCHG_2 1 +#define CMPXCHG_4 2 +#define CMPXCHG_8 3 +#define CMPXCHGn(n, s) \ + {"cmpxchg"#n"."#s, CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 0)}, \ + {"cmpxchg"#n"."#s, CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 0)}, \ + {"cmpxchg"#n"."#s".nt1", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 1)}, \ + {"cmpxchg"#n"."#s".nt1", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 1)}, \ + {"cmpxchg"#n"."#s".nta", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 3)}, \ + {"cmpxchg"#n"."#s".nta", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 3)} +#define CMP8XCHG16(s) \ + {"cmp8xchg16."#s, CMPXCHG16 (0x20|CMPXCHG_##s, 0)}, \ + {"cmp8xchg16."#s, CMPXCHG16_P (0x20|CMPXCHG_##s, 0)}, \ + {"cmp8xchg16."#s".nt1", CMPXCHG16 (0x20|CMPXCHG_##s, 1)}, \ + {"cmp8xchg16."#s".nt1", CMPXCHG16_P (0x20|CMPXCHG_##s, 1)}, \ + {"cmp8xchg16."#s".nta", CMPXCHG16 (0x20|CMPXCHG_##s, 3)}, \ + {"cmp8xchg16."#s".nta", CMPXCHG16_P (0x20|CMPXCHG_##s, 3)} +#define CMPXCHG_ALL(s) CMPXCHGn(1, s), \ + CMPXCHGn(2, s), \ + CMPXCHGn(4, s), \ + CMPXCHGn(8, s), \ + CMP8XCHG16(s) + CMPXCHG_ALL(acq), + CMPXCHG_ALL(rel), +#undef CMPXCHG +#undef CMPXCHG_P +#undef CMPXCHG16 +#undef CMPXCHG16_P +#undef CMPXCHG_acq +#undef CMPXCHG_rel +#undef CMPXCHG_1 +#undef CMPXCHG_2 +#undef CMPXCHG_4 +#undef CMPXCHG_8 +#undef CMPXCHGn +#undef CMPXCHG16 +#undef CMPXCHG_ALL + {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY}, + {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPTY}, + {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPTY}, + {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}, EMPTY}, + {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}, EMPTY}, + {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}, EMPTY}, + {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}, EMPTY}, + {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}, EMPTY}, + {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}, EMPTY}, + {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}, EMPTY}, + {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}, EMPTY}, + {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}, EMPTY}, + + {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}, EMPTY}, + + {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}, EMPTY}, + {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}, EMPTY}, + {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}, EMPTY}, + {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}, EMPTY}, + + /* Integer load w/increment by immediate. */ +#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL + {"ld1", LDINCIMMED (0x00, 0)}, + {"ld1.nt1", LDINCIMMED (0x00, 1)}, + {"ld1.nta", LDINCIMMED (0x00, 3)}, + {"ld2", LDINCIMMED (0x01, 0)}, + {"ld2.nt1", LDINCIMMED (0x01, 1)}, + {"ld2.nta", LDINCIMMED (0x01, 3)}, + {"ld4", LDINCIMMED (0x02, 0)}, + {"ld4.nt1", LDINCIMMED (0x02, 1)}, + {"ld4.nta", LDINCIMMED (0x02, 3)}, + {"ld8", LDINCIMMED (0x03, 0)}, + {"ld8.nt1", LDINCIMMED (0x03, 1)}, + {"ld8.nta", LDINCIMMED (0x03, 3)}, + {"ld1.s", LDINCIMMED (0x04, 0)}, + {"ld1.s.nt1", LDINCIMMED (0x04, 1)}, + {"ld1.s.nta", LDINCIMMED (0x04, 3)}, + {"ld2.s", LDINCIMMED (0x05, 0)}, + {"ld2.s.nt1", LDINCIMMED (0x05, 1)}, + {"ld2.s.nta", LDINCIMMED (0x05, 3)}, + {"ld4.s", LDINCIMMED (0x06, 0)}, + {"ld4.s.nt1", LDINCIMMED (0x06, 1)}, + {"ld4.s.nta", LDINCIMMED (0x06, 3)}, + {"ld8.s", LDINCIMMED (0x07, 0)}, + {"ld8.s.nt1", LDINCIMMED (0x07, 1)}, + {"ld8.s.nta", LDINCIMMED (0x07, 3)}, + {"ld1.a", LDINCIMMED (0x08, 0)}, + {"ld1.a.nt1", LDINCIMMED (0x08, 1)}, + {"ld1.a.nta", LDINCIMMED (0x08, 3)}, + {"ld2.a", LDINCIMMED (0x09, 0)}, + {"ld2.a.nt1", LDINCIMMED (0x09, 1)}, + {"ld2.a.nta", LDINCIMMED (0x09, 3)}, + {"ld4.a", LDINCIMMED (0x0a, 0)}, + {"ld4.a.nt1", LDINCIMMED (0x0a, 1)}, + {"ld4.a.nta", LDINCIMMED (0x0a, 3)}, + {"ld8.a", LDINCIMMED (0x0b, 0)}, + {"ld8.a.nt1", LDINCIMMED (0x0b, 1)}, + {"ld8.a.nta", LDINCIMMED (0x0b, 3)}, + {"ld1.sa", LDINCIMMED (0x0c, 0)}, + {"ld1.sa.nt1", LDINCIMMED (0x0c, 1)}, + {"ld1.sa.nta", LDINCIMMED (0x0c, 3)}, + {"ld2.sa", LDINCIMMED (0x0d, 0)}, + {"ld2.sa.nt1", LDINCIMMED (0x0d, 1)}, + {"ld2.sa.nta", LDINCIMMED (0x0d, 3)}, + {"ld4.sa", LDINCIMMED (0x0e, 0)}, + {"ld4.sa.nt1", LDINCIMMED (0x0e, 1)}, + {"ld4.sa.nta", LDINCIMMED (0x0e, 3)}, + {"ld8.sa", LDINCIMMED (0x0f, 0)}, + {"ld8.sa.nt1", LDINCIMMED (0x0f, 1)}, + {"ld8.sa.nta", LDINCIMMED (0x0f, 3)}, + {"ld1.bias", LDINCIMMED (0x10, 0)}, + {"ld1.bias.nt1", LDINCIMMED (0x10, 1)}, + {"ld1.bias.nta", LDINCIMMED (0x10, 3)}, + {"ld2.bias", LDINCIMMED (0x11, 0)}, + {"ld2.bias.nt1", LDINCIMMED (0x11, 1)}, + {"ld2.bias.nta", LDINCIMMED (0x11, 3)}, + {"ld4.bias", LDINCIMMED (0x12, 0)}, + {"ld4.bias.nt1", LDINCIMMED (0x12, 1)}, + {"ld4.bias.nta", LDINCIMMED (0x12, 3)}, + {"ld8.bias", LDINCIMMED (0x13, 0)}, + {"ld8.bias.nt1", LDINCIMMED (0x13, 1)}, + {"ld8.bias.nta", LDINCIMMED (0x13, 3)}, + {"ld1.acq", LDINCIMMED (0x14, 0)}, + {"ld1.acq.nt1", LDINCIMMED (0x14, 1)}, + {"ld1.acq.nta", LDINCIMMED (0x14, 3)}, + {"ld2.acq", LDINCIMMED (0x15, 0)}, + {"ld2.acq.nt1", LDINCIMMED (0x15, 1)}, + {"ld2.acq.nta", LDINCIMMED (0x15, 3)}, + {"ld4.acq", LDINCIMMED (0x16, 0)}, + {"ld4.acq.nt1", LDINCIMMED (0x16, 1)}, + {"ld4.acq.nta", LDINCIMMED (0x16, 3)}, + {"ld8.acq", LDINCIMMED (0x17, 0)}, + {"ld8.acq.nt1", LDINCIMMED (0x17, 1)}, + {"ld8.acq.nta", LDINCIMMED (0x17, 3)}, + {"ld8.fill", LDINCIMMED (0x1b, 0)}, + {"ld8.fill.nt1", LDINCIMMED (0x1b, 1)}, + {"ld8.fill.nta", LDINCIMMED (0x1b, 3)}, + {"ld1.c.clr", LDINCIMMED (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)}, + {"ld1.c.clr.nta", LDINCIMMED (0x20, 3)}, + {"ld2.c.clr", LDINCIMMED (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)}, + {"ld2.c.clr.nta", LDINCIMMED (0x21, 3)}, + {"ld4.c.clr", LDINCIMMED (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)}, + {"ld4.c.clr.nta", LDINCIMMED (0x22, 3)}, + {"ld8.c.clr", LDINCIMMED (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)}, + {"ld8.c.clr.nta", LDINCIMMED (0x23, 3)}, + {"ld1.c.nc", LDINCIMMED (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)}, + {"ld1.c.nc.nta", LDINCIMMED (0x24, 3)}, + {"ld2.c.nc", LDINCIMMED (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)}, + {"ld2.c.nc.nta", LDINCIMMED (0x25, 3)}, + {"ld4.c.nc", LDINCIMMED (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)}, + {"ld4.c.nc.nta", LDINCIMMED (0x26, 3)}, + {"ld8.c.nc", LDINCIMMED (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)}, + {"ld8.c.nc.nta", LDINCIMMED (0x27, 3)}, + {"ld1.c.clr.acq", LDINCIMMED (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)}, + {"ld2.c.clr.acq", LDINCIMMED (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)}, + {"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, +#undef LDINCIMMED + + /* Store w/increment by immediate. */ +#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL + {"st1", STINCIMMED (0x30, 0)}, + {"st1.nta", STINCIMMED (0x30, 3)}, + {"st2", STINCIMMED (0x31, 0)}, + {"st2.nta", STINCIMMED (0x31, 3)}, + {"st4", STINCIMMED (0x32, 0)}, + {"st4.nta", STINCIMMED (0x32, 3)}, + {"st8", STINCIMMED (0x33, 0)}, + {"st8.nta", STINCIMMED (0x33, 3)}, + {"st1.rel", STINCIMMED (0x34, 0)}, + {"st1.rel.nta", STINCIMMED (0x34, 3)}, + {"st2.rel", STINCIMMED (0x35, 0)}, + {"st2.rel.nta", STINCIMMED (0x35, 3)}, + {"st4.rel", STINCIMMED (0x36, 0)}, + {"st4.rel.nta", STINCIMMED (0x36, 3)}, + {"st8.rel", STINCIMMED (0x37, 0)}, + {"st8.rel.nta", STINCIMMED (0x37, 3)}, + {"st8.spill", STINCIMMED (0x3b, 0)}, + {"st8.spill.nta", STINCIMMED (0x3b, 3)}, +#undef STINCIMMED + + /* Floating-point load. */ + {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY}, + {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}, EMPTY}, + {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}, EMPTY}, + {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}, EMPTY}, + {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}, EMPTY}, + {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}, EMPTY}, + {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}, EMPTY}, + {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}, EMPTY}, + {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}, EMPTY}, + {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}, EMPTY}, + {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}, EMPTY}, + {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}, EMPTY}, + {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}, EMPTY}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}, EMPTY}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}, EMPTY}, + {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}, EMPTY}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}, EMPTY}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}, EMPTY}, + {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}, EMPTY}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}, EMPTY}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}, EMPTY}, + {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}, EMPTY}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}, EMPTY}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}, EMPTY}, + {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}, EMPTY}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}, EMPTY}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}, EMPTY}, + {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}, EMPTY}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}, EMPTY}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}, EMPTY}, + {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}, EMPTY}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}, EMPTY}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}, EMPTY}, + {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}, EMPTY}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}, EMPTY}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}, EMPTY}, + {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}, EMPTY}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}, EMPTY}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}, EMPTY}, + {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}, EMPTY}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}, EMPTY}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}, EMPTY}, + {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}, EMPTY}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}, EMPTY}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}, EMPTY}, + {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}, EMPTY}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}, EMPTY}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}, EMPTY}, + {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}, EMPTY}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}, EMPTY}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}, EMPTY}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}, EMPTY}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}, EMPTY}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}, EMPTY}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}, EMPTY}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}, EMPTY}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}, EMPTY}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}, EMPTY}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}, EMPTY}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}, EMPTY}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}, EMPTY}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}, EMPTY}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}, EMPTY}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}, EMPTY}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}, EMPTY}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}, EMPTY}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}, EMPTY}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}, EMPTY}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}, EMPTY}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}, EMPTY}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}, EMPTY}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}, EMPTY}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}, EMPTY}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}, EMPTY}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}, EMPTY}, + + /* Floating-point load w/increment by register. */ +#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL + {"ldfs", FLDINCREG (0x02, 0)}, + {"ldfs.nt1", FLDINCREG (0x02, 1)}, + {"ldfs.nta", FLDINCREG (0x02, 3)}, + {"ldfd", FLDINCREG (0x03, 0)}, + {"ldfd.nt1", FLDINCREG (0x03, 1)}, + {"ldfd.nta", FLDINCREG (0x03, 3)}, + {"ldf8", FLDINCREG (0x01, 0)}, + {"ldf8.nt1", FLDINCREG (0x01, 1)}, + {"ldf8.nta", FLDINCREG (0x01, 3)}, + {"ldfe", FLDINCREG (0x00, 0)}, + {"ldfe.nt1", FLDINCREG (0x00, 1)}, + {"ldfe.nta", FLDINCREG (0x00, 3)}, + {"ldfs.s", FLDINCREG (0x06, 0)}, + {"ldfs.s.nt1", FLDINCREG (0x06, 1)}, + {"ldfs.s.nta", FLDINCREG (0x06, 3)}, + {"ldfd.s", FLDINCREG (0x07, 0)}, + {"ldfd.s.nt1", FLDINCREG (0x07, 1)}, + {"ldfd.s.nta", FLDINCREG (0x07, 3)}, + {"ldf8.s", FLDINCREG (0x05, 0)}, + {"ldf8.s.nt1", FLDINCREG (0x05, 1)}, + {"ldf8.s.nta", FLDINCREG (0x05, 3)}, + {"ldfe.s", FLDINCREG (0x04, 0)}, + {"ldfe.s.nt1", FLDINCREG (0x04, 1)}, + {"ldfe.s.nta", FLDINCREG (0x04, 3)}, + {"ldfs.a", FLDINCREG (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCREG (0x0a, 1)}, + {"ldfs.a.nta", FLDINCREG (0x0a, 3)}, + {"ldfd.a", FLDINCREG (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCREG (0x0b, 1)}, + {"ldfd.a.nta", FLDINCREG (0x0b, 3)}, + {"ldf8.a", FLDINCREG (0x09, 0)}, + {"ldf8.a.nt1", FLDINCREG (0x09, 1)}, + {"ldf8.a.nta", FLDINCREG (0x09, 3)}, + {"ldfe.a", FLDINCREG (0x08, 0)}, + {"ldfe.a.nt1", FLDINCREG (0x08, 1)}, + {"ldfe.a.nta", FLDINCREG (0x08, 3)}, + {"ldfs.sa", FLDINCREG (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCREG (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCREG (0x0e, 3)}, + {"ldfd.sa", FLDINCREG (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCREG (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCREG (0x0f, 3)}, + {"ldf8.sa", FLDINCREG (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCREG (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCREG (0x0d, 3)}, + {"ldfe.sa", FLDINCREG (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCREG (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCREG (0x0c, 3)}, + {"ldf.fill", FLDINCREG (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCREG (0x1b, 1)}, + {"ldf.fill.nta", FLDINCREG (0x1b, 3)}, + {"ldfs.c.clr", FLDINCREG (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCREG (0x22, 3)}, + {"ldfd.c.clr", FLDINCREG (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCREG (0x23, 3)}, + {"ldf8.c.clr", FLDINCREG (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCREG (0x21, 3)}, + {"ldfe.c.clr", FLDINCREG (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCREG (0x20, 3)}, + {"ldfs.c.nc", FLDINCREG (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCREG (0x26, 3)}, + {"ldfd.c.nc", FLDINCREG (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCREG (0x27, 3)}, + {"ldf8.c.nc", FLDINCREG (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCREG (0x25, 3)}, + {"ldfe.c.nc", FLDINCREG (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, +#undef FLDINCREG + + /* Floating-point store. */ + {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY}, + {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}, EMPTY}, + {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}, EMPTY}, + {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}, EMPTY}, + {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}, EMPTY}, + {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}, EMPTY}, + {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}, EMPTY}, + {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}, EMPTY}, + {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}, EMPTY}, + {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}, EMPTY}, + + /* Floating-point load pair. */ + {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}, EMPTY}, + + /* Floating-point load pair w/increment by immediate. */ +#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL + {"ldfps", LD (0x02, 0, C8)}, + {"ldfps.nt1", LD (0x02, 1, C8)}, + {"ldfps.nta", LD (0x02, 3, C8)}, + {"ldfpd", LD (0x03, 0, C16)}, + {"ldfpd.nt1", LD (0x03, 1, C16)}, + {"ldfpd.nta", LD (0x03, 3, C16)}, + {"ldfp8", LD (0x01, 0, C16)}, + {"ldfp8.nt1", LD (0x01, 1, C16)}, + {"ldfp8.nta", LD (0x01, 3, C16)}, + {"ldfps.s", LD (0x06, 0, C8)}, + {"ldfps.s.nt1", LD (0x06, 1, C8)}, + {"ldfps.s.nta", LD (0x06, 3, C8)}, + {"ldfpd.s", LD (0x07, 0, C16)}, + {"ldfpd.s.nt1", LD (0x07, 1, C16)}, + {"ldfpd.s.nta", LD (0x07, 3, C16)}, + {"ldfp8.s", LD (0x05, 0, C16)}, + {"ldfp8.s.nt1", LD (0x05, 1, C16)}, + {"ldfp8.s.nta", LD (0x05, 3, C16)}, + {"ldfps.a", LD (0x0a, 0, C8)}, + {"ldfps.a.nt1", LD (0x0a, 1, C8)}, + {"ldfps.a.nta", LD (0x0a, 3, C8)}, + {"ldfpd.a", LD (0x0b, 0, C16)}, + {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, + {"ldfpd.a.nta", LD (0x0b, 3, C16)}, + {"ldfp8.a", LD (0x09, 0, C16)}, + {"ldfp8.a.nt1", LD (0x09, 1, C16)}, + {"ldfp8.a.nta", LD (0x09, 3, C16)}, + {"ldfps.sa", LD (0x0e, 0, C8)}, + {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, + {"ldfps.sa.nta", LD (0x0e, 3, C8)}, + {"ldfpd.sa", LD (0x0f, 0, C16)}, + {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, + {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, + {"ldfp8.sa", LD (0x0d, 0, C16)}, + {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, + {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, + {"ldfps.c.clr", LD (0x22, 0, C8)}, + {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, + {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, + {"ldfpd.c.clr", LD (0x23, 0, C16)}, + {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, + {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, + {"ldfp8.c.clr", LD (0x21, 0, C16)}, + {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, + {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, + {"ldfps.c.nc", LD (0x26, 0, C8)}, + {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, + {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, + {"ldfpd.c.nc", LD (0x27, 0, C16)}, + {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, + {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, + {"ldfp8.c.nc", LD (0x25, 0, C16)}, + {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, + {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, +#undef LD + + /* Line prefetch. */ + {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}, EMPTY}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}, EMPTY}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}, EMPTY}, + {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}, EMPTY}, + {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}, EMPTY}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}, EMPTY}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}, EMPTY}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}, EMPTY}, + {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}, EMPTY}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}, EMPTY}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}, EMPTY}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}, EMPTY}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}, EMPTY}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}, EMPTY}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}, EMPTY}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}, EMPTY}, + + /* Line prefetch w/increment by register. */ +#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL + {"lfetch", LFETCHINCREG (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCREG (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCREG (0x2c, 2)}, + {"lfetch.nta", LFETCHINCREG (0x2c, 3)}, + {"lfetch.excl", LFETCHINCREG (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCREG (0x2d, 3)}, + {"lfetch.fault", LFETCHINCREG (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCREG (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCREG (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)}, +#undef LFETCHINCREG + + /* Semaphore operations. */ + {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}, EMPTY}, + {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}, EMPTY}, + {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}, EMPTY}, + {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}, EMPTY}, + + /* Floating-point load w/increment by immediate. */ +#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL + {"ldfs", FLDINCIMMED (0x02, 0)}, + {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, + {"ldfs.nta", FLDINCIMMED (0x02, 3)}, + {"ldfd", FLDINCIMMED (0x03, 0)}, + {"ldfd.nt1", FLDINCIMMED (0x03, 1)}, + {"ldfd.nta", FLDINCIMMED (0x03, 3)}, + {"ldf8", FLDINCIMMED (0x01, 0)}, + {"ldf8.nt1", FLDINCIMMED (0x01, 1)}, + {"ldf8.nta", FLDINCIMMED (0x01, 3)}, + {"ldfe", FLDINCIMMED (0x00, 0)}, + {"ldfe.nt1", FLDINCIMMED (0x00, 1)}, + {"ldfe.nta", FLDINCIMMED (0x00, 3)}, + {"ldfs.s", FLDINCIMMED (0x06, 0)}, + {"ldfs.s.nt1", FLDINCIMMED (0x06, 1)}, + {"ldfs.s.nta", FLDINCIMMED (0x06, 3)}, + {"ldfd.s", FLDINCIMMED (0x07, 0)}, + {"ldfd.s.nt1", FLDINCIMMED (0x07, 1)}, + {"ldfd.s.nta", FLDINCIMMED (0x07, 3)}, + {"ldf8.s", FLDINCIMMED (0x05, 0)}, + {"ldf8.s.nt1", FLDINCIMMED (0x05, 1)}, + {"ldf8.s.nta", FLDINCIMMED (0x05, 3)}, + {"ldfe.s", FLDINCIMMED (0x04, 0)}, + {"ldfe.s.nt1", FLDINCIMMED (0x04, 1)}, + {"ldfe.s.nta", FLDINCIMMED (0x04, 3)}, + {"ldfs.a", FLDINCIMMED (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)}, + {"ldfs.a.nta", FLDINCIMMED (0x0a, 3)}, + {"ldfd.a", FLDINCIMMED (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)}, + {"ldfd.a.nta", FLDINCIMMED (0x0b, 3)}, + {"ldf8.a", FLDINCIMMED (0x09, 0)}, + {"ldf8.a.nt1", FLDINCIMMED (0x09, 1)}, + {"ldf8.a.nta", FLDINCIMMED (0x09, 3)}, + {"ldfe.a", FLDINCIMMED (0x08, 0)}, + {"ldfe.a.nt1", FLDINCIMMED (0x08, 1)}, + {"ldfe.a.nta", FLDINCIMMED (0x08, 3)}, + {"ldfs.sa", FLDINCIMMED (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)}, + {"ldfd.sa", FLDINCIMMED (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)}, + {"ldf8.sa", FLDINCIMMED (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)}, + {"ldfe.sa", FLDINCIMMED (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)}, + {"ldf.fill", FLDINCIMMED (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)}, + {"ldf.fill.nta", FLDINCIMMED (0x1b, 3)}, + {"ldfs.c.clr", FLDINCIMMED (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)}, + {"ldfd.c.clr", FLDINCIMMED (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)}, + {"ldf8.c.clr", FLDINCIMMED (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)}, + {"ldfe.c.clr", FLDINCIMMED (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)}, + {"ldfs.c.nc", FLDINCIMMED (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)}, + {"ldfd.c.nc", FLDINCIMMED (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)}, + {"ldf8.c.nc", FLDINCIMMED (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)}, + {"ldfe.c.nc", FLDINCIMMED (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, +#undef FLDINCIMMED + + /* Floating-point store w/increment by immediate. */ +#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL + {"stfs", FSTINCIMMED (0x32, 0)}, + {"stfs.nta", FSTINCIMMED (0x32, 3)}, + {"stfd", FSTINCIMMED (0x33, 0)}, + {"stfd.nta", FSTINCIMMED (0x33, 3)}, + {"stf8", FSTINCIMMED (0x31, 0)}, + {"stf8.nta", FSTINCIMMED (0x31, 3)}, + {"stfe", FSTINCIMMED (0x30, 0)}, + {"stfe.nta", FSTINCIMMED (0x30, 3)}, + {"stf.spill", FSTINCIMMED (0x3b, 0)}, + {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, +#undef FSTINCIMMED + + /* Line prefetch w/increment by immediate. */ +#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL + {"lfetch", LFETCHINCIMMED (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)}, + {"lfetch.nta", LFETCHINCIMMED (0x2c, 3)}, + {"lfetch.excl", LFETCHINCIMMED (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3)}, + {"lfetch.fault", LFETCHINCIMMED (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)}, +#undef LFETCHINCIMMED + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef M0 +#undef M +#undef M2 +#undef bM +#undef bX +#undef bX2 +#undef bX3 +#undef bX4 +#undef bX6a +#undef bX6b +#undef bHint +#undef mM +#undef mX +#undef mX2 +#undef mX3 +#undef mX4 +#undef mX6a +#undef mX6b +#undef mHint +#undef OpX3 +#undef OpX3X6b +#undef OpX3X4 +#undef OpX3X4X2 +#undef OpX6aHint +#undef OpXX6aHint +#undef OpMXX6a +#undef OpMXX6aHint +#undef EMPTY diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc-x.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc-x.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,188 @@ +/* ia64-opc-x.c -- IA-64 `X' opcode table. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + Contributed by Timothy Wall + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-opc.h" + +/* Identify the specific X-unit type. */ +#define X0 IA64_TYPE_X, 0 +#define X IA64_TYPE_X, 1 + +/* Instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mVc bVc (-1) +#define mWha bWha (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mY bY (-1) + +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \ + (mOp | mX3 | mX6 | mY) +#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) + +struct ia64_opcode ia64_opcodes_x[] = + { + {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL}, + {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL}, + {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL}, + {"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL}, +#define BRL(a,b) \ + X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL + {"brl.few", BRL (0, 0)}, + {"brl", BRL (0, 0)}, + {"brl.few.clr", BRL (0, 1)}, + {"brl.clr", BRL (0, 1)}, + {"brl.many", BRL (1, 0)}, + {"brl.many.clr", BRL (1, 1)}, +#undef BRL +#define BRL(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL +#define BRLP(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL + {"brl.cond.sptk.few", BRL (0, 0, 0)}, + {"brl.cond.sptk", BRLP (0, 0, 0)}, + {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.cond.sptk.clr", BRLP (0, 0, 1)}, + {"brl.cond.spnt.few", BRL (0, 1, 0)}, + {"brl.cond.spnt", BRLP (0, 1, 0)}, + {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.cond.spnt.clr", BRLP (0, 1, 1)}, + {"brl.cond.dptk.few", BRL (0, 2, 0)}, + {"brl.cond.dptk", BRLP (0, 2, 0)}, + {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.cond.dptk.clr", BRLP (0, 2, 1)}, + {"brl.cond.dpnt.few", BRL (0, 3, 0)}, + {"brl.cond.dpnt", BRLP (0, 3, 0)}, + {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.cond.dpnt.clr", BRLP (0, 3, 1)}, + {"brl.cond.sptk.many", BRL (1, 0, 0)}, + {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.cond.spnt.many", BRL (1, 1, 0)}, + {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.cond.dptk.many", BRL (1, 2, 0)}, + {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.cond.dpnt.many", BRL (1, 3, 0)}, + {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, + {"brl.sptk.few", BRL (0, 0, 0)}, + {"brl.sptk", BRLP (0, 0, 0)}, + {"brl.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.sptk.clr", BRLP (0, 0, 1)}, + {"brl.spnt.few", BRL (0, 1, 0)}, + {"brl.spnt", BRLP (0, 1, 0)}, + {"brl.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.spnt.clr", BRLP (0, 1, 1)}, + {"brl.dptk.few", BRL (0, 2, 0)}, + {"brl.dptk", BRLP (0, 2, 0)}, + {"brl.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.dptk.clr", BRLP (0, 2, 1)}, + {"brl.dpnt.few", BRL (0, 3, 0)}, + {"brl.dpnt", BRLP (0, 3, 0)}, + {"brl.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.dpnt.clr", BRLP (0, 3, 1)}, + {"brl.sptk.many", BRL (1, 0, 0)}, + {"brl.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.spnt.many", BRL (1, 1, 0)}, + {"brl.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.dptk.many", BRL (1, 2, 0)}, + {"brl.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.dpnt.many", BRL (1, 3, 0)}, + {"brl.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#undef BRLP +#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0, 0, NULL +#define BRLP(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, PSEUDO, 0, NULL + {"brl.call.sptk.few", BRL (0, 0, 0)}, + {"brl.call.sptk", BRLP (0, 0, 0)}, + {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.call.sptk.clr", BRLP (0, 0, 1)}, + {"brl.call.spnt.few", BRL (0, 1, 0)}, + {"brl.call.spnt", BRLP (0, 1, 0)}, + {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.call.spnt.clr", BRLP (0, 1, 1)}, + {"brl.call.dptk.few", BRL (0, 2, 0)}, + {"brl.call.dptk", BRLP (0, 2, 0)}, + {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.call.dptk.clr", BRLP (0, 2, 1)}, + {"brl.call.dpnt.few", BRL (0, 3, 0)}, + {"brl.call.dpnt", BRLP (0, 3, 0)}, + {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.call.dpnt.clr", BRLP (0, 3, 1)}, + {"brl.call.sptk.many", BRL (1, 0, 0)}, + {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.call.spnt.many", BRL (1, 1, 0)}, + {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.call.dptk.many", BRL (1, 2, 0)}, + {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.call.dpnt.many", BRL (1, 3, 0)}, + {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#undef BRLP + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef X0 +#undef X + +#undef bBtype +#undef bD +#undef bPa +#undef bPr +#undef bVc +#undef bWha +#undef bX3 +#undef bX6 + +#undef mBtype +#undef mD +#undef mPa +#undef mPr +#undef mVc +#undef mWha +#undef mX3 +#undef mX6 + +#undef OpX3X6 +#undef OpVc +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,727 @@ +/* ia64-opc.c -- Functions to access the compacted opcode table + Copyright 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc. + Written by Bob Manson of Cygnus Solutions, + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "ia64-asmtab.h" +#include "ia64-asmtab.c" + +static void get_opc_prefix (const char **, char *); +static short int find_string_ent (const char *); +static short int find_main_ent (short int); +static short int find_completer (short int, short int, const char *); +static ia64_insn apply_completer (ia64_insn, int); +static int extract_op_bits (int, int, int); +static int extract_op (int, int *, unsigned int *); +static int opcode_verify (ia64_insn, int, enum ia64_insn_type); +static int locate_opcode_ent (ia64_insn, enum ia64_insn_type); +static struct ia64_opcode *make_ia64_opcode + (ia64_insn, const char *, int, int); +static struct ia64_opcode *ia64_find_matching_opcode + (const char *, short int); + +const struct ia64_templ_desc ia64_templ_desc[16] = + { + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ + { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, + { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, + { 0, { 0, }, "-3-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ + { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ + { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, + { 0, { 0, }, "-a-" }, + { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ + { 0, { 0, }, "-d-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, + { 0, { 0, }, "-f-" }, + }; + + +/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. + PTR will be adjusted to point to the start of the next portion + of the opcode, or at the NUL character. */ + +static void +get_opc_prefix (const char **ptr, char *dest) +{ + char *c = strchr (*ptr, '.'); + if (c != NULL) + { + memcpy (dest, *ptr, c - *ptr); + dest[c - *ptr] = '\0'; + *ptr = c + 1; + } + else + { + int l = strlen (*ptr); + memcpy (dest, *ptr, l); + dest[l] = '\0'; + *ptr += l; + } +} + +/* Find the index of the entry in the string table corresponding to + STR; return -1 if one does not exist. */ + +static short +find_string_ent (const char *str) +{ + short start = 0; + short end = sizeof (ia64_strings) / sizeof (const char *); + short i = (start + end) / 2; + + if (strcmp (str, ia64_strings[end - 1]) > 0) + { + return -1; + } + while (start <= end) + { + int c = strcmp (str, ia64_strings[i]); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the opcode in the main opcode table whose name is STRINGINDEX, or + return -1 if one does not exist. */ + +static short +find_main_ent (short nameindex) +{ + short start = 0; + short end = sizeof (main_table) / sizeof (struct ia64_main_table); + short i = (start + end) / 2; + + if (nameindex < main_table[0].name_index + || nameindex > main_table[end - 1].name_index) + { + return -1; + } + while (start <= end) + { + if (nameindex < main_table[i].name_index) + { + end = i - 1; + } + else if (nameindex == main_table[i].name_index) + { + while (i > 0 && main_table[i - 1].name_index == nameindex) + { + i--; + } + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the index of the entry in the completer table that is part of + MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or + return -1 if one does not exist. */ + +static short +find_completer (short main_ent, short prev_completer, const char *name) +{ + short name_index = find_string_ent (name); + + if (name_index < 0) + { + return -1; + } + + if (prev_completer == -1) + { + prev_completer = main_table[main_ent].completers; + } + else + { + prev_completer = completer_table[prev_completer].subentries; + } + + while (prev_completer != -1) + { + if (completer_table[prev_completer].name_index == name_index) + { + return prev_completer; + } + prev_completer = completer_table[prev_completer].alternative; + } + return -1; +} + +/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and + return the result. */ + +static ia64_insn +apply_completer (ia64_insn opcode, int completer_index) +{ + ia64_insn mask = completer_table[completer_index].mask; + ia64_insn bits = completer_table[completer_index].bits; + int shiftamt = (completer_table[completer_index].offset & 63); + + mask = mask << shiftamt; + bits = bits << shiftamt; + opcode = (opcode & ~mask) | bits; + return opcode; +} + +/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in + the dis_table array, and return its value. (BITOFFSET is numbered + starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the + first byte in OP_POINTER.) */ + +static int +extract_op_bits (int op_pointer, int bitoffset, int bits) +{ + int res = 0; + + op_pointer += (bitoffset / 8); + + if (bitoffset % 8) + { + unsigned int op = dis_table[op_pointer++]; + int numb = 8 - (bitoffset % 8); + int mask = (1 << numb) - 1; + int bata = (bits < numb) ? bits : numb; + int delta = numb - bata; + + res = (res << bata) | ((op & mask) >> delta); + bitoffset += bata; + bits -= bata; + } + while (bits >= 8) + { + res = (res << 8) | (dis_table[op_pointer++] & 255); + bits -= 8; + } + if (bits > 0) + { + unsigned int op = (dis_table[op_pointer++] & 255); + res = (res << bits) | (op >> (8 - bits)); + } + return res; +} + +/* Examine the state machine entry at OP_POINTER in the dis_table + array, and extract its values into OPVAL and OP. The length of the + state entry in bits is returned. */ + +static int +extract_op (int op_pointer, int *opval, unsigned int *op) +{ + int oplen = 5; + + *op = dis_table[op_pointer]; + + if ((*op) & 0x40) + { + opval[0] = extract_op_bits (op_pointer, oplen, 5); + oplen += 5; + } + switch ((*op) & 0x30) + { + case 0x10: + { + opval[1] = extract_op_bits (op_pointer, oplen, 8); + oplen += 8; + opval[1] += op_pointer; + break; + } + case 0x20: + { + opval[1] = extract_op_bits (op_pointer, oplen, 16); + if (! (opval[1] & 32768)) + { + opval[1] += op_pointer; + } + oplen += 16; + break; + } + case 0x30: + { + oplen--; + opval[2] = extract_op_bits (op_pointer, oplen, 12); + oplen += 12; + opval[2] |= 32768; + break; + } + } + if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) + { + opval[2] = extract_op_bits (op_pointer, oplen, 16); + oplen += 16; + if (! (opval[2] & 32768)) + { + opval[2] += op_pointer; + } + } + return oplen; +} + +/* Returns a non-zero value if the opcode in the main_table list at + PLACE matches OPCODE and is of type TYPE. */ + +static int +opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) +{ + if (main_table[place].opcode_type != type) + { + return 0; + } + if (main_table[place].flags + & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) + { + const struct ia64_operand *o1, *o2; + ia64_insn f2, f3; + + if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) + { + o1 = elf64_ia64_operands + IA64_OPND_F2; + o2 = elf64_ia64_operands + IA64_OPND_F3; + (*o1->extract) (o1, opcode, &f2); + (*o2->extract) (o2, opcode, &f3); + if (f2 != f3) + return 0; + } + else + { + ia64_insn len, count; + + /* length must equal 64-count: */ + o1 = elf64_ia64_operands + IA64_OPND_LEN6; + o2 = elf64_ia64_operands + main_table[place].operands[2]; + (*o1->extract) (o1, opcode, &len); + (*o2->extract) (o2, opcode, &count); + if (len != 64 - count) + return 0; + } + } + return 1; +} + +/* Find an instruction entry in the ia64_dis_names array that matches + opcode OPCODE and is of type TYPE. Returns either a positive index + into the array, or a negative value if an entry for OPCODE could + not be found. Checks all matches and returns the one with the highest + priority. */ + +static int +locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) +{ + int currtest[41]; + int bitpos[41]; + int op_ptr[41]; + int currstatenum = 0; + short found_disent = -1; + short found_priority = -1; + + currtest[currstatenum] = 0; + op_ptr[currstatenum] = 0; + bitpos[currstatenum] = 40; + + while (1) + { + int op_pointer = op_ptr[currstatenum]; + unsigned int op; + int currbitnum = bitpos[currstatenum]; + int oplen; + int opval[3] = {0}; + int next_op; + int currbit; + + oplen = extract_op (op_pointer, opval, &op); + + bitpos[currstatenum] = currbitnum; + + /* Skip opval[0] bits in the instruction. */ + if (op & 0x40) + { + currbitnum -= opval[0]; + } + + /* The value of the current bit being tested. */ + currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; + next_op = -1; + + /* We always perform the tests specified in the current state in + a particular order, falling through to the next test if the + previous one failed. */ + switch (currtest[currstatenum]) + { + case 0: + currtest[currstatenum]++; + if (currbit == 0 && (op & 0x80)) + { + /* Check for a zero bit. If this test solely checks for + a zero bit, we can check for up to 8 consecutive zero + bits (the number to check is specified by the lower 3 + bits in the state code.) + + If the state instruction matches, we go to the very + next state instruction; otherwise, try the next test. */ + + if ((op & 0xf8) == 0x80) + { + int count = op & 0x7; + int x; + + for (x = 0; x <= count; x++) + { + int i = + opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; + if (i) + { + break; + } + } + if (x > count) + { + next_op = op_pointer + ((oplen + 7) / 8); + currbitnum -= count; + break; + } + } + else if (! currbit) + { + next_op = op_pointer + ((oplen + 7) / 8); + break; + } + } + /* FALLTHROUGH */ + case 1: + /* If the bit in the instruction is one, go to the state + instruction specified by opval[1]. */ + currtest[currstatenum]++; + if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) + { + next_op = opval[1]; + break; + } + /* FALLTHROUGH */ + case 2: + /* Don't care. Skip the current bit and go to the state + instruction specified by opval[2]. + + An encoding of 0x30 is special; this means that a 12-bit + offset into the ia64_dis_names[] array is specified. */ + currtest[currstatenum]++; + if ((op & 0x08) || ((op & 0x30) == 0x30)) + { + next_op = opval[2]; + break; + } + } + + /* If bit 15 is set in the address of the next state, an offset + in the ia64_dis_names array was specified instead. We then + check to see if an entry in the list of opcodes matches the + opcode we were given; if so, we have succeeded. */ + + if ((next_op >= 0) && (next_op & 32768)) + { + short disent = next_op & 32767; + short priority = -1; + + if (next_op > 65535) + { + abort (); + } + + /* Run through the list of opcodes to check, trying to find + one that matches. */ + while (disent >= 0) + { + int place = ia64_dis_names[disent].insn_index; + + priority = ia64_dis_names[disent].priority; + + if (opcode_verify (opcode, place, type) + && priority > found_priority) + { + break; + } + if (ia64_dis_names[disent].next_flag) + { + disent++; + } + else + { + disent = -1; + } + } + + if (disent >= 0) + { + found_disent = disent; + found_priority = priority; + } + /* Try the next test in this state, regardless of whether a match + was found. */ + next_op = -2; + } + + /* next_op == -1 is "back up to the previous state". + next_op == -2 is "stay in this state and try the next test". + Otherwise, transition to the state indicated by next_op. */ + + if (next_op == -1) + { + currstatenum--; + if (currstatenum < 0) + { + return found_disent; + } + } + else if (next_op >= 0) + { + currstatenum++; + bitpos[currstatenum] = currbitnum - 1; + op_ptr[currstatenum] = next_op; + currtest[currstatenum] = 0; + } + } +} + +/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ + +static struct ia64_opcode * +make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind) +{ + struct ia64_opcode *res = + (struct ia64_opcode *) malloc (sizeof (struct ia64_opcode)); + res->name = strdup (name); + res->type = main_table[place].opcode_type; + res->num_outputs = main_table[place].num_outputs; + res->opcode = opcode; + res->mask = main_table[place].mask; + res->operands[0] = main_table[place].operands[0]; + res->operands[1] = main_table[place].operands[1]; + res->operands[2] = main_table[place].operands[2]; + res->operands[3] = main_table[place].operands[3]; + res->operands[4] = main_table[place].operands[4]; + res->flags = main_table[place].flags; + res->ent_index = place; + res->dependencies = &op_dependencies[depind]; + return res; +} + +/* Determine the ia64_opcode entry for the opcode specified by INSN + and TYPE. If a valid entry is not found, return NULL. */ +struct ia64_opcode * +ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) +{ + int disent = locate_opcode_ent (insn, type); + + if (disent < 0) + { + return NULL; + } + else + { + unsigned int cb = ia64_dis_names[disent].completer_index; + static char name[128]; + int place = ia64_dis_names[disent].insn_index; + int ci = main_table[place].completers; + ia64_insn tinsn = main_table[place].opcode; + + strcpy (name, ia64_strings [main_table[place].name_index]); + + while (cb) + { + if (cb & 1) + { + int cname = completer_table[ci].name_index; + + tinsn = apply_completer (tinsn, ci); + + if (ia64_strings[cname][0] != '\0') + { + strcat (name, "."); + strcat (name, ia64_strings[cname]); + } + if (cb != 1) + { + ci = completer_table[ci].subentries; + } + } + else + { + ci = completer_table[ci].alternative; + } + if (ci < 0) + { + abort (); + } + cb = cb >> 1; + } + if (tinsn != (insn & main_table[place].mask)) + { + abort (); + } + return make_ia64_opcode (insn, name, place, + completer_table[ci].dependencies); + } +} + +/* Search the main_opcode table starting from PLACE for an opcode that + matches NAME. Return NULL if one is not found. */ + +static struct ia64_opcode * +ia64_find_matching_opcode (const char *name, short place) +{ + char op[129]; + const char *suffix; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + while (main_table[place].name_index == name_index) + { + const char *curr_suffix = suffix; + ia64_insn curr_insn = main_table[place].opcode; + short completer = -1; + + do { + if (suffix[0] == '\0') + { + completer = find_completer (place, completer, suffix); + } + else + { + get_opc_prefix (&curr_suffix, op); + completer = find_completer (place, completer, op); + } + if (completer != -1) + { + curr_insn = apply_completer (curr_insn, completer); + } + } while (completer != -1 && curr_suffix[0] != '\0'); + + if (completer != -1 && curr_suffix[0] == '\0' + && completer_table[completer].terminal_completer) + { + int depind = completer_table[completer].dependencies; + return make_ia64_opcode (curr_insn, name, place, depind); + } + else + { + place++; + } + } + return NULL; +} + +/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL + if one does not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_next_opcode (struct ia64_opcode *prev_ent) +{ + return ia64_find_matching_opcode (prev_ent->name, + prev_ent->ent_index + 1); +} + +/* Find the first opcode that matches NAME, or return NULL if it does + not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_opcode (const char *name) +{ + char op[129]; + const char *suffix; + short place; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + place = find_main_ent (name_index); + + if (place < 0) + { + return NULL; + } + return ia64_find_matching_opcode (name, place); +} + +/* Free any resources used by ENT. */ +void +ia64_free_opcode (struct ia64_opcode *ent) +{ + free ((void *)ent->name); + free (ent); +} + +const struct ia64_dependency * +ia64_find_dependency (int index) +{ + index = DEP(index); + + if (index < 0 + || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0]))) + return NULL; + + return &dependencies[index]; +} diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64-opc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64-opc.h Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,133 @@ +/* ia64-opc.h -- IA-64 opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2006 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef IA64_OPC_H +#define IA64_OPC_H + +#include "ia64.h" + +/* define a couple of abbreviations: */ + +#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) +#define mOp bOp (-1) +#define Op(x) bOp (x), mOp + +#define FIRST IA64_OPCODE_FIRST +#define X_IN_MLX IA64_OPCODE_X_IN_MLX +#define LAST IA64_OPCODE_LAST +#define PRIV IA64_OPCODE_PRIV +#define NO_PRED IA64_OPCODE_NO_PRED +#define SLOT2 IA64_OPCODE_SLOT2 +#define PSEUDO IA64_OPCODE_PSEUDO +#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 +#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT +#define MOD_RRBS IA64_OPCODE_MOD_RRBS +#define POSTINC IA64_OPCODE_POSTINC + +#define AR_CCV IA64_OPND_AR_CCV +#define AR_PFS IA64_OPND_AR_PFS +#define AR_CSD IA64_OPND_AR_CSD +#define C1 IA64_OPND_C1 +#define C8 IA64_OPND_C8 +#define C16 IA64_OPND_C16 +#define GR0 IA64_OPND_GR0 +#define IP IA64_OPND_IP +#define PR IA64_OPND_PR +#define PR_ROT IA64_OPND_PR_ROT +#define PSR IA64_OPND_PSR +#define PSR_L IA64_OPND_PSR_L +#define PSR_UM IA64_OPND_PSR_UM + +#define AR3 IA64_OPND_AR3 +#define B1 IA64_OPND_B1 +#define B2 IA64_OPND_B2 +#define CR3 IA64_OPND_CR3 +#define F1 IA64_OPND_F1 +#define F2 IA64_OPND_F2 +#define F3 IA64_OPND_F3 +#define F4 IA64_OPND_F4 +#define P1 IA64_OPND_P1 +#define P2 IA64_OPND_P2 +#define R1 IA64_OPND_R1 +#define R2 IA64_OPND_R2 +#define R3 IA64_OPND_R3 +#define R3_2 IA64_OPND_R3_2 + +#define CPUID_R3 IA64_OPND_CPUID_R3 +#define DBR_R3 IA64_OPND_DBR_R3 +#define DTR_R3 IA64_OPND_DTR_R3 +#define ITR_R3 IA64_OPND_ITR_R3 +#define IBR_R3 IA64_OPND_IBR_R3 +#define MR3 IA64_OPND_MR3 +#define MSR_R3 IA64_OPND_MSR_R3 +#define PKR_R3 IA64_OPND_PKR_R3 +#define PMC_R3 IA64_OPND_PMC_R3 +#define PMD_R3 IA64_OPND_PMD_R3 +#define RR_R3 IA64_OPND_RR_R3 + +#define CCNT5 IA64_OPND_CCNT5 +#define CNT2a IA64_OPND_CNT2a +#define CNT2b IA64_OPND_CNT2b +#define CNT2c IA64_OPND_CNT2c +#define CNT5 IA64_OPND_CNT5 +#define CNT6 IA64_OPND_CNT6 +#define CPOS6a IA64_OPND_CPOS6a +#define CPOS6b IA64_OPND_CPOS6b +#define CPOS6c IA64_OPND_CPOS6c +#define IMM1 IA64_OPND_IMM1 +#define IMM14 IA64_OPND_IMM14 +#define IMM17 IA64_OPND_IMM17 +#define IMM22 IA64_OPND_IMM22 +#define IMM44 IA64_OPND_IMM44 +#define SOF IA64_OPND_SOF +#define SOL IA64_OPND_SOL +#define SOR IA64_OPND_SOR +#define IMM8 IA64_OPND_IMM8 +#define IMM8U4 IA64_OPND_IMM8U4 +#define IMM8M1 IA64_OPND_IMM8M1 +#define IMM8M1U4 IA64_OPND_IMM8M1U4 +#define IMM8M1U8 IA64_OPND_IMM8M1U8 +#define IMM9a IA64_OPND_IMM9a +#define IMM9b IA64_OPND_IMM9b +#define IMMU2 IA64_OPND_IMMU2 +#define IMMU21 IA64_OPND_IMMU21 +#define IMMU24 IA64_OPND_IMMU24 +#define IMMU62 IA64_OPND_IMMU62 +#define IMMU64 IA64_OPND_IMMU64 +#define IMMU5b IA64_OPND_IMMU5b +#define IMMU7a IA64_OPND_IMMU7a +#define IMMU7b IA64_OPND_IMMU7b +#define IMMU9 IA64_OPND_IMMU9 +#define INC3 IA64_OPND_INC3 +#define LEN4 IA64_OPND_LEN4 +#define LEN6 IA64_OPND_LEN6 +#define MBTYPE4 IA64_OPND_MBTYPE4 +#define MHTYPE8 IA64_OPND_MHTYPE8 +#define POS6 IA64_OPND_POS6 +#define TAG13 IA64_OPND_TAG13 +#define TAG13b IA64_OPND_TAG13b +#define TGT25 IA64_OPND_TGT25 +#define TGT25b IA64_OPND_TGT25b +#define TGT25c IA64_OPND_TGT25c +#define TGT64 IA64_OPND_TGT64 + +#endif diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/ia64.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/ia64.h Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,396 @@ +/* ia64.h -- Header file for ia64 opcode table + Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang */ + +#ifndef opcode_ia64_h +#define opcode_ia64_h + +#include + +#include "dis-asm.h" + + +typedef BFD_HOST_U_64_BIT ia64_insn; + +enum ia64_insn_type + { + IA64_TYPE_NIL = 0, /* illegal type */ + IA64_TYPE_A, /* integer alu (I- or M-unit) */ + IA64_TYPE_I, /* non-alu integer (I-unit) */ + IA64_TYPE_M, /* memory (M-unit) */ + IA64_TYPE_B, /* branch (B-unit) */ + IA64_TYPE_F, /* floating-point (F-unit) */ + IA64_TYPE_X, /* long encoding (X-unit) */ + IA64_TYPE_DYN, /* Dynamic opcode */ + IA64_NUM_TYPES + }; + +enum ia64_unit + { + IA64_UNIT_NIL = 0, /* illegal unit */ + IA64_UNIT_I, /* integer unit */ + IA64_UNIT_M, /* memory unit */ + IA64_UNIT_B, /* branching unit */ + IA64_UNIT_F, /* floating-point unit */ + IA64_UNIT_L, /* long "unit" */ + IA64_UNIT_X, /* may be integer or branch unit */ + IA64_NUM_UNITS + }; + +/* Changes to this enumeration must be propagated to the operand table in + bfd/cpu-ia64-opc.c + */ +enum ia64_opnd + { + IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ + + /* constants */ + IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ + IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ + IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ + IA64_OPND_C1, /* the constant 1 */ + IA64_OPND_C8, /* the constant 8 */ + IA64_OPND_C16, /* the constant 16 */ + IA64_OPND_GR0, /* gr0 */ + IA64_OPND_IP, /* instruction pointer (ip) */ + IA64_OPND_PR, /* predicate register (pr) */ + IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ + IA64_OPND_PSR, /* processor status register (psr) */ + IA64_OPND_PSR_L, /* processor status register L (psr.l) */ + IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ + + /* register operands: */ + IA64_OPND_AR3, /* third application register # (bits 20-26) */ + IA64_OPND_B1, /* branch register # (bits 6-8) */ + IA64_OPND_B2, /* branch register # (bits 13-15) */ + IA64_OPND_CR3, /* third control register # (bits 20-26) */ + IA64_OPND_F1, /* first floating-point register # */ + IA64_OPND_F2, /* second floating-point register # */ + IA64_OPND_F3, /* third floating-point register # */ + IA64_OPND_F4, /* fourth floating-point register # */ + IA64_OPND_P1, /* first predicate # */ + IA64_OPND_P2, /* second predicate # */ + IA64_OPND_R1, /* first register # */ + IA64_OPND_R2, /* second register # */ + IA64_OPND_R3, /* third register # */ + IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + + /* memory operands: */ + IA64_OPND_MR3, /* memory at addr of third register # */ + + /* indirect operands: */ + IA64_OPND_CPUID_R3, /* cpuid[reg] */ + IA64_OPND_DBR_R3, /* dbr[reg] */ + IA64_OPND_DTR_R3, /* dtr[reg] */ + IA64_OPND_ITR_R3, /* itr[reg] */ + IA64_OPND_IBR_R3, /* ibr[reg] */ + IA64_OPND_MSR_R3, /* msr[reg] */ + IA64_OPND_PKR_R3, /* pkr[reg] */ + IA64_OPND_PMC_R3, /* pmc[reg] */ + IA64_OPND_PMD_R3, /* pmd[reg] */ + IA64_OPND_RR_R3, /* rr[reg] */ + + /* immediate operands: */ + IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ + IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ + IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ + IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ + IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ + IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ + IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ + IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ + IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ + IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ + IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ + IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ + IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ + IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ + IA64_OPND_SOF, /* 8-bit stack frame size */ + IA64_OPND_SOL, /* 8-bit size of locals */ + IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ + IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ + IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ + IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ + IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ + IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ + IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ + IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ + IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ + IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ + IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ + IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ + IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ + IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ + IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ + IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ + IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ + IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ + IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ + IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ + IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ + IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ + IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ + IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ + IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ + IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ + IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ + IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ + IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ + IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ + + IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ + }; + +enum ia64_dependency_mode +{ + IA64_DV_RAW, + IA64_DV_WAW, + IA64_DV_WAR, +}; + +enum ia64_dependency_semantics +{ + IA64_DVS_NONE, + IA64_DVS_IMPLIED, + IA64_DVS_IMPLIEDF, + IA64_DVS_DATA, + IA64_DVS_INSTR, + IA64_DVS_SPECIFIC, + IA64_DVS_STOP, + IA64_DVS_OTHER, +}; + +enum ia64_resource_specifier +{ + IA64_RS_ANY, + IA64_RS_AR_K, + IA64_RS_AR_UNAT, + IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ + IA64_RS_ARb, /* 48-63, 112-127 */ + IA64_RS_BR, + IA64_RS_CFM, + IA64_RS_CPUID, + IA64_RS_CR_IRR, + IA64_RS_CR_LRR, + IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */ + IA64_RS_DBR, + IA64_RS_FR, + IA64_RS_FRb, + IA64_RS_GR0, + IA64_RS_GR, + IA64_RS_IBR, + IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ + IA64_RS_MSR, + IA64_RS_PKR, + IA64_RS_PMC, + IA64_RS_PMD, + IA64_RS_PR, /* non-rotating, 1-15 */ + IA64_RS_PRr, /* rotating, 16-62 */ + IA64_RS_PR63, + IA64_RS_RR, + + IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ + IA64_RS_CRX, /* CRs not in RS_CR */ + IA64_RS_PSR, /* PSR bits */ + IA64_RS_RSE, /* implementation-specific RSE resources */ + IA64_RS_AR_FPSR, +}; + +enum ia64_rse_resource +{ + IA64_RSE_N_STACKED_PHYS, + IA64_RSE_BOF, + IA64_RSE_STORE_REG, + IA64_RSE_LOAD_REG, + IA64_RSE_BSPLOAD, + IA64_RSE_RNATBITINDEX, + IA64_RSE_CFLE, + IA64_RSE_NDIRTY, +}; + +/* Information about a given resource dependency */ +struct ia64_dependency +{ + /* Name of the resource */ + const char *name; + /* Does this dependency need further specification? */ + enum ia64_resource_specifier specifier; + /* Mode of dependency */ + enum ia64_dependency_mode mode; + /* Dependency semantics */ + enum ia64_dependency_semantics semantics; + /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ +#define REG_NONE (-1) + int regindex; + /* Special info on semantics */ + const char *info; +}; + +/* Two arrays of indexes into the ia64_dependency table. + chks are dependencies to check for conflicts when an opcode is + encountered; regs are dependencies to register (mark as used) when an + opcode is used. chks correspond to readers (RAW) or writers (WAW or + WAR) of a resource, while regs correspond to writers (RAW or WAW) and + readers (WAR) of a resource. */ +struct ia64_opcode_dependency +{ + int nchks; + const unsigned short *chks; + int nregs; + const unsigned short *regs; +}; + +/* encode/extract the note/index for a dependency */ +#define RDEP(N,X) (((N)<<11)|(X)) +#define NOTE(X) (((X)>>11)&0x1F) +#define DEP(X) ((X)&0x7FF) + +/* A template descriptor describes the execution units that are active + for each of the three slots. It also specifies the location of + instruction group boundaries that may be present between two slots. */ +struct ia64_templ_desc + { + int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ + enum ia64_unit exec_unit[3]; + const char *name; + }; + +/* The opcode table is an array of struct ia64_opcode. */ + +struct ia64_opcode + { + /* The opcode name. */ + const char *name; + + /* The type of the instruction: */ + enum ia64_insn_type type; + + /* Number of output operands: */ + int num_outputs; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + ia64_insn opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + ia64_insn mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + enum ia64_opnd operands[5]; + + /* One bit flags for the opcode. These are primarily used to + indicate specific processors and environments support the + instructions. The defined values are listed below. */ + unsigned int flags; + + /* Used by ia64_find_next_opcode (). */ + short ent_index; + + /* Opcode dependencies. */ + const struct ia64_opcode_dependency *dependencies; + }; + +/* Values defined for the flags field of a struct ia64_opcode. */ + +#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ +#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ +#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ +#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ +#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ +#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ +#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ +#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ +#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ +#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ +#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ + +/* A macro to extract the major opcode from an instruction. */ +#define IA64_OP(i) (((i) >> 37) & 0xf) + +enum ia64_operand_class + { + IA64_OPND_CLASS_CST, /* constant */ + IA64_OPND_CLASS_REG, /* register */ + IA64_OPND_CLASS_IND, /* indirect register */ + IA64_OPND_CLASS_ABS, /* absolute value */ + IA64_OPND_CLASS_REL, /* IP-relative value */ + }; + +/* The operands table is an array of struct ia64_operand. */ + +struct ia64_operand +{ + enum ia64_operand_class class; + + /* Set VALUE as the operand bits for the operand of type SELF in the + instruction pointed to by CODE. If an error occurs, *CODE is not + modified and the returned string describes the cause of the + error. If no error occurs, NULL is returned. */ + const char *(*insert) (const struct ia64_operand *self, ia64_insn value, + ia64_insn *code); + + /* Extract the operand bits for an operand of type SELF from + instruction CODE store them in *VALUE. If an error occurs, the + cause of the error is described by the string returned. If no + error occurs, NULL is returned. */ + const char *(*extract) (const struct ia64_operand *self, ia64_insn code, + ia64_insn *value); + + /* A string whose meaning depends on the operand class. */ + + const char *str; + + struct bit_field + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + } + field[4]; /* no operand has more than this many bit-fields */ + + unsigned int flags; + + const char *desc; /* brief description */ +}; + +/* Values defined for the flags field of a struct ia64_operand. */ + +/* Disassemble as signed decimal (instead of hex): */ +#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) +/* Disassemble as unsigned decimal (instead of hex): */ +#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) + +extern const struct ia64_templ_desc ia64_templ_desc[16]; + +/* The tables are sorted by major opcode number and are otherwise in + the order in which the disassembler should consider instructions. */ +extern struct ia64_opcode ia64_opcodes_a[]; +extern struct ia64_opcode ia64_opcodes_i[]; +extern struct ia64_opcode ia64_opcodes_m[]; +extern struct ia64_opcode ia64_opcodes_b[]; +extern struct ia64_opcode ia64_opcodes_f[]; +extern struct ia64_opcode ia64_opcodes_d[]; + + +extern struct ia64_opcode *ia64_find_opcode (const char *name); +extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent); + +extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn, + enum ia64_insn_type type); + +extern void ia64_free_opcode (struct ia64_opcode *ent); +extern const struct ia64_dependency *ia64_find_dependency (int index); + +/* To avoid circular library dependencies, this array is implemented + in bfd/cpu-ia64-opc.c: */ +extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; + +#endif /* opcode_ia64_h */ diff -r 09b45357e492 -r 109ef655c591 tools/debugger/xenitp/xenitp.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tools/debugger/xenitp/xenitp.c Sat Sep 22 14:49:55 2007 +0200 @@ -0,0 +1,1523 @@ +/* tools/debugger/xenitp.c - A low-level debugger. + + Based on xenctxt.c, but heavily modified. + Copyright 2007 Tristan Gingold + + Xenitp is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Xenitp is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xenctrl.h" +#include +#include "dis-asm.h" + +#ifdef __HYPERVISOR_ia64_debug_op +#define HAVE_DEBUG_OP +#endif + +static int xc_handle = 0; +static int domid = 0; +static vcpu_guest_context_t *cur_ctx; +static int cur_vcpu; + +#define PSR_BN (1UL << 44) +#define PSR_SS (1UL << 40) +#define PSR_DB (1UL << 24) +#define PSR_TB (1UL << 26) +#define PSR_DD (1UL << 39) +#define PSR_ID (1UL << 37) +#define PSR_IT (1UL << 36) +#define PSR_DT (1UL << 17) +#define PSR_RI_SHIFT 41 +#define CFM_SOF_MASK 0x3f + +int virt_to_phys (int is_inst, unsigned long vaddr, unsigned long *paddr); + +inline unsigned int ctx_slot (vcpu_guest_context_t *ctx) +{ + return (ctx->regs.psr >> PSR_RI_SHIFT) & 3; +} + +unsigned char * +target_map_memory (unsigned long paddr) +{ + static unsigned long cur_page = -1; + static unsigned char *cur_map = NULL; + + if ((paddr >> XC_PAGE_SHIFT) != cur_page) { + if (cur_map) { + munmap(cur_map, XC_PAGE_SIZE); + cur_map = NULL; + } + cur_page = paddr >> XC_PAGE_SHIFT; + cur_map = xc_map_foreign_range(xc_handle, domid, XC_PAGE_SIZE, + PROT_READ, cur_page); + if (cur_map == NULL) { + perror("cannot map page"); + cur_page = -1; + return NULL; + } + } + return cur_map + (paddr & (XC_PAGE_SIZE - 1)); +} + +/* Get LENGTH bytes from info's buffer, at target address memaddr. + Transfer them to myaddr. */ +int +target_read_memory (bfd_vma memaddr, bfd_byte *myaddr, + unsigned int length, struct disassemble_info *info) +{ + int i; + unsigned long paddr; + + if (cur_ctx->regs.psr & PSR_IT) { + if (virt_to_phys (1, memaddr, &paddr) != 0) + return EIO; + } + else { + /* Clear UC. */ + paddr = memaddr & ~(1UL << 63); + } + + for(i = 0; i < length; i++) { + unsigned char *p = target_map_memory (paddr + i); + if (p == NULL) + return EIO; + myaddr[i] = *p; + } + return 0; +} + +/* Print an error message. We can assume that this is in response to + an error return from buffer_read_memory. */ +void +perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info) +{ + if (status != EIO) + /* Can't happen. */ + (*info->fprintf_func) (info->stream, "Unknown error %d\n", status); + else + /* Actually, address between memaddr and memaddr + len was + out of bounds. */ + (*info->fprintf_func) (info->stream, + "Address 0x%" PRIx64 " is out of bounds.\n", memaddr); +} + +/* This could be in a separate file, to save miniscule amounts of space + in statically linked executables. */ + +/* Just print the address is hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ + +void +generic_print_address (bfd_vma addr, struct disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr); +} + +/* Just return the given address. */ + +int +generic_symbol_at_address (bfd_vma addr, struct disassemble_info * info) +{ + return 1; +} + +bfd_boolean +generic_symbol_is_valid (asymbol * sym ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) +{ + return 1; +} + +bfd_vma bfd_getl32 (const bfd_byte *addr) +{ + unsigned long v; + + v = (unsigned long) addr[0]; + v |= (unsigned long) addr[1] << 8; + v |= (unsigned long) addr[2] << 16; + v |= (unsigned long) addr[3] << 24; + return (bfd_vma) v; +} + +bfd_vma bfd_getl64 (const bfd_byte *addr) +{ + unsigned long v; + + v = (unsigned long) addr[0]; + v |= (unsigned long) addr[1] << 8; + v |= (unsigned long) addr[2] << 16; + v |= (unsigned long) addr[3] << 24; + v |= (unsigned long) addr[4] << 32; + v |= (unsigned long) addr[5] << 40; + v |= (unsigned long) addr[6] << 48; + v |= (unsigned long) addr[7] << 56; + return (bfd_vma) v; +} + +bfd_vma bfd_getb32 (const bfd_byte *addr) +{ + unsigned long v; + + v = (unsigned long) addr[0] << 24; + v |= (unsigned long) addr[1] << 16; + v |= (unsigned long) addr[2] << 8; + v |= (unsigned long) addr[3]; + return (bfd_vma) v; +} + +bfd_vma bfd_getl16 (const bfd_byte *addr) +{ + unsigned long v; + + v = (unsigned long) addr[0]; + v |= (unsigned long) addr[1] << 8; + return (bfd_vma) v; +} + +bfd_vma bfd_getb16 (const bfd_byte *addr) +{ + unsigned long v; + + v = (unsigned long) addr[0] << 24; + v |= (unsigned long) addr[1] << 16; + return (bfd_vma) v; +} + +void +init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func) +{ + memset (info, 0, sizeof (*info)); + + info->flavour = bfd_target_unknown_flavour; + info->arch = bfd_arch_unknown; + info->endian = BFD_ENDIAN_UNKNOWN; + info->octets_per_byte = 1; + info->fprintf_func = fprintf_func; + info->stream = stream; + info->read_memory_func = target_read_memory; + info->memory_error_func = perror_memory; + info->print_address_func = generic_print_address; + info->symbol_at_address_func = generic_symbol_at_address; + info->symbol_is_valid = generic_symbol_is_valid; + info->display_endian = BFD_ENDIAN_UNKNOWN; +} + + +void target_disas(FILE *out, unsigned long code, unsigned long size) +{ + unsigned long pc; + int count; + struct disassemble_info disasm_info; + int slot; + int (*print_insn)(bfd_vma pc, disassemble_info *info); + + INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); + + disasm_info.read_memory_func = target_read_memory; +#if 0 + disasm_info.buffer = NULL; + disasm_info.buffer_vma = (unsigned long)code; + disasm_info.buffer_length = size; +#endif + + disasm_info.endian = BFD_ENDIAN_LITTLE; + disasm_info.mach = 0; //bfd_mach_ia64; + print_insn = print_insn_ia64; + + for (pc = code, slot = 0; pc < code + size; pc += count, slot++) { + fprintf(out, "0x%016lx+%d:%c ", code, slot, + ((pc & ~0x0fUL) == cur_ctx->regs.ip + && slot == ctx_slot (cur_ctx)) ? '*' : ' '); + + count = print_insn(pc, &disasm_info); +#if 0 + { + int i; + uint8_t b; + fprintf(out, " {"); + for(i = 0; i < count; i++) { + target_read_memory(pc + i, &b, 1, &disasm_info); + fprintf(out, " %02x", b); + } + fprintf(out, " }"); + } +#endif + fprintf(out, "\n"); + if (count < 0) + break; + } +} + + +#define PTE_ED_SHIFT 52 +#define PTE_ED_MASK 1 +#define PTE_PPN_SHIFT 12 +#define PTE_PPN_MASK 0x3fffffffff +#define PTE_AR_SHIFT 9 +#define PTE_AR_MASK 7 +#define PTE_PL_SHIFT 7 +#define PTE_PL_MASK 3 +#define PTE_D_SHIFT 6 +#define PTE_D_MASK 1 +#define PTE_A_SHIFT 5 +#define PTE_A_MASK 1 +#define PTE_MA_SHIFT 2 +#define PTE_MA_MASK 7 +#define PTE_P_SHIFT 0 +#define PTE_P_MASK 1 +#define ITIR_KEY_SHIFT 8 +#define ITIR_KEY_MASK 0xffffff +#define ITIR_PS_SHIFT 2 +#define ITIR_PS_MASK 0x3f +#define ITIR_PS_MIN 12 +#define ITIR_PS_MAX 28 +#define RR_RID_SHIFT 8 +#define RR_RID_MASK 0xffffff +#define RR_PS_SHIFT 2 +#define RR_PS_MASK 0x3f +#define RR_VE_MASK 1 + +static const char *get_ps (int ps_val) +{ + static const char ps[][5] = {" 4K", " 8K", " 16K", " ", + " 64K", " ", "256K", " ", + " 1M", " ", " 4M", " ", + " 16M", " ", " 64M", " ", + "256M"}; + return ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ? + ps[ps_val - ITIR_PS_MIN] : " "); + +} + +static void print_a_tr(int i, const struct ia64_tr_entry *tr) +{ + int ps_val, ma_val; + unsigned long pa; + + static const char ma[][4] = {"WB ", " ", " ", " ", + "UC ", "UCE", "WC ", "Nat"}; + + ps_val = tr->itir >> ITIR_PS_SHIFT & ITIR_PS_MASK; + ma_val = tr->pte >> PTE_MA_SHIFT & PTE_MA_MASK; + pa = (tr->pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) << PTE_PPN_SHIFT; + pa = (pa >> ps_val) << ps_val; + printf(" [%d] %ld %06lx %016lx %013lx %02d %s %ld %ld %ld %ld " + "%ld %d %s %06lx\n", i, + tr->pte >> PTE_P_SHIFT & PTE_P_MASK, + tr->rid >> RR_RID_SHIFT & RR_RID_MASK, + tr->vadr, pa, ps_val, get_ps(ps_val), + tr->pte >> PTE_ED_SHIFT & PTE_ED_MASK, + tr->pte >> PTE_PL_SHIFT & PTE_PL_MASK, + tr->pte >> PTE_AR_SHIFT & PTE_AR_MASK, + tr->pte >> PTE_A_SHIFT & PTE_A_MASK, + tr->pte >> PTE_D_SHIFT & PTE_D_MASK, + ma_val, ma[ma_val], + tr->itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK); +} + +void print_ctx(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + int i; + unsigned int rbs_size, cfm_sof; + + rbs_size = (regs->ar.bsp - regs->ar.bspstore) / 8; + cfm_sof = (regs->cfm & CFM_SOF_MASK); + printf ("bspstore: %016lx bsp: %016lx rbs_size=%d, sof=%d\n", + regs->ar.bspstore, regs->ar.bsp, rbs_size, cfm_sof); + for (i = 0; i < cfm_sof; i++) { + int off = cfm_sof - i; + unsigned int rbs_off = + (((62 - ((rbs_size + regs->rbs_voff) % 64) + off)) / 63) + off; + if (rbs_off > rbs_size) + break; + printf(" r%02d: %016lx%s", 32 + i, + regs->rbs[rbs_size - rbs_off], + (i % 3) != 2 ? " " : "\n"); + } + if ((i % 3) != 0) + printf ("\n"); + + printf("\n"); + printf(" r1: %016lx ", regs->r[1]); + printf(" r2: %016lx ", regs->r[2]); + printf(" r3: %016lx\n", regs->r[3]); + printf(" r4: %016lx ", regs->r[4]); + printf(" r5: %016lx ", regs->r[5]); + printf(" r6: %016lx\n", regs->r[6]); + printf(" r7: %016lx ", regs->r[7]); + printf(" r8: %016lx ", regs->r[8]); + printf(" r9: %016lx\n", regs->r[9]); + printf(" r10: %016lx ", regs->r[10]); + printf(" r11: %016lx ", regs->r[11]); + printf(" sp: %016lx\n", regs->r[12]); + printf(" tp: %016lx ", regs->r[13]); + printf(" r14: %016lx ", regs->r[14]); + printf(" r15: %016lx\n", regs->r[15]); + printf(" r16: %016lx ", regs->r[16]); + printf(" r17: %016lx ", regs->r[17]); + printf(" r18: %016lx\n", regs->r[18]); + printf(" r19: %016lx ", regs->r[19]); + printf(" r20: %016lx ", regs->r[20]); + printf(" r21: %016lx\n", regs->r[21]); + printf(" r22: %016lx ", regs->r[22]); + printf(" r23: %016lx ", regs->r[23]); + printf(" r24: %016lx\n", regs->r[24]); + printf(" r25: %016lx ", regs->r[25]); + printf(" r26: %016lx ", regs->r[26]); + printf(" r27: %016lx\n", regs->r[27]); + printf(" r28: %016lx ", regs->r[28]); + printf(" r29: %016lx ", regs->r[29]); + printf(" r30: %016lx\n", regs->r[30]); + printf(" r31: %016lx ", regs->r[31]); + printf(" "); + printf(" b0: %016lx\n", regs->b[0]); + + printf("\n"); + printf(" psr: %016lx ", regs->psr); + printf(" cfm: %016lx ", regs->cfm); + printf(" pr: %016lx\n", regs->pr); + + printf("\n"); + printf(" ip: %016lx+%d", regs->ip, (int)(regs->psr >> PSR_RI_SHIFT) & 3); + printf("\n"); + target_disas(stdout, regs->ip, 16); +} + +void print_br(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + + printf(" b0: %016lx ", regs->b[0]); + printf(" b1: %016lx ", regs->b[1]); + printf(" b2: %016lx\n", regs->b[2]); + printf(" b3: %016lx ", regs->b[3]); + printf(" b4: %016lx ", regs->b[4]); + printf(" b5: %016lx\n", regs->b[5]); + printf(" b6: %016lx ", regs->b[6]); + printf(" b7: %016lx\n", regs->b[7]); +} + +void print_regs(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + + printf(" r1: %016lx ", regs->r[1]); + printf(" r2: %016lx ", regs->r[2]); + printf(" r3: %016lx\n", regs->r[3]); + printf(" r4: %016lx ", regs->r[4]); + printf(" r5: %016lx ", regs->r[5]); + printf(" r6: %016lx\n", regs->r[6]); + printf(" r7: %016lx ", regs->r[7]); + printf(" r8: %016lx ", regs->r[8]); + printf(" r9: %016lx\n", regs->r[9]); + printf(" r10: %016lx ", regs->r[10]); + printf(" r11: %016lx ", regs->r[11]); + printf(" sp: %016lx\n", regs->r[12]); + printf(" tp: %016lx ", regs->r[13]); + printf(" r14: %016lx ", regs->r[14]); + printf(" r15: %016lx\n", regs->r[15]); + + printf(" Bank %d (current) Bank %d\n", + (regs->psr & PSR_BN) ? 1 : 0, (regs->psr & PSR_BN) ? 0 : 1); + printf ("16:%016lx ", regs->r[16]); + printf ("17:%016lx ", regs->r[17]); + printf ("16:%016lx ", regs->bank[0]); + printf ("17:%016lx\n", regs->bank[1]); + printf ("18:%016lx ", regs->r[18]); + printf ("19:%016lx ", regs->r[19]); + printf ("18:%016lx ", regs->bank[2]); + printf ("19:%016lx\n", regs->bank[3]); + printf ("20:%016lx ", regs->r[20]); + printf ("21:%016lx ", regs->r[21]); + printf ("20:%016lx ", regs->bank[4]); + printf ("21:%016lx\n", regs->bank[5]); + printf ("22:%016lx ", regs->r[22]); + printf ("23:%016lx ", regs->r[23]); + printf ("22:%016lx ", regs->bank[6]); + printf ("23:%016lx\n", regs->bank[7]); + printf ("24:%016lx ", regs->r[24]); + printf ("25:%016lx ", regs->r[25]); + printf ("24:%016lx ", regs->bank[8]); + printf ("25:%016lx\n", regs->bank[9]); + printf ("26:%016lx ", regs->r[26]); + printf ("27:%016lx ", regs->r[27]); + printf ("26:%016lx ", regs->bank[10]); + printf ("27:%016lx\n", regs->bank[11]); + printf ("28:%016lx ", regs->r[28]); + printf ("29:%016lx ", regs->r[29]); + printf ("28:%016lx ", regs->bank[12]); + printf ("29:%016lx\n", regs->bank[13]); + printf ("30:%016lx ", regs->r[30]); + printf ("31:%016lx ", regs->r[31]); + printf ("30:%016lx ", regs->bank[14]); + printf ("31:%016lx\n", regs->bank[15]); + printf("\n"); +} + +void print_cr(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + + printf(" dcr: %016lx ", regs->cr.dcr); + printf(" itm: %016lx ", regs->cr.itm); + printf(" iva: %016lx\n", regs->cr.iva); + printf(" pta: %016lx ", regs->cr.pta); + printf(" ipsr: %016lx ", regs->cr.ipsr); + printf(" isr: %016lx\n", regs->cr.isr); + printf(" iip: %016lx ", regs->cr.iip); + printf(" ifa: %016lx ", regs->cr.ifa); + printf(" itir: %016lx\n", regs->cr.itir); + printf(" iipa: %016lx ", regs->cr.iipa); + printf(" ifs: %016lx ", regs->cr.ifs); + printf(" iim: %016lx\n", regs->cr.iim); + printf(" iha: %016lx ", regs->cr.iha); + printf(" lid: %016lx ", regs->cr.lid); + printf(" ivr: %016lx\n", regs->cr.ivr); + printf(" tpr: %016lx ", regs->cr.tpr); + printf(" eoi: %016lx ", regs->cr.eoi); + printf(" irr0: %016lx\n", regs->cr.irr[0]); + printf(" irr1: %016lx ", regs->cr.irr[1]); + printf(" irr2: %016lx ", regs->cr.irr[2]); + printf(" irr3: %016lx\n", regs->cr.irr[3]); + printf(" itv: %016lx ", regs->cr.itv); + printf(" pmv: %016lx ", regs->cr.pmv); + printf(" cmcv: %016lx\n", regs->cr.cmcv); + printf(" lrr0: %016lx ", regs->cr.lrr0); + printf(" lrr1: %016lx ", regs->cr.lrr1); + printf(" ev_cb:%016lx\n", ctx->event_callback_ip); +} + +void print_ar(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + + printf(" kr0: %016lx ", regs->ar.kr[0]); + printf(" kr1: %016lx ", regs->ar.kr[1]); + printf(" kr2: %016lx\n", regs->ar.kr[2]); + printf(" kr3: %016lx ", regs->ar.kr[3]); + printf(" kr4: %016lx ", regs->ar.kr[4]); + printf(" kr5: %016lx\n", regs->ar.kr[5]); + printf(" kr6: %016lx ", regs->ar.kr[6]); + printf(" kr7: %016lx ", regs->ar.kr[7]); + printf(" rsc: %016lx\n", regs->ar.rsc); + printf(" bsp: %016lx ", regs->ar.bsp); + printf(" bsps: %016lx ", regs->ar.bspstore); + printf(" rnat: %016lx\n", regs->ar.rnat); + printf(" csd: %016lx ", regs->ar.csd); + printf(" ccv: %016lx ", regs->ar.ccv); + printf(" unat: %016lx\n", regs->ar.unat); + printf(" fpsr: %016lx ", regs->ar.fpsr); + printf(" itc: %016lx\n", regs->ar.itc); + printf(" pfs: %016lx ", regs->ar.pfs); + printf(" lc: %016lx ", regs->ar.lc); + printf(" ec: %016lx\n", regs->ar.ec); +} + +void print_a_rr (int num, unsigned long rr) +{ + int ps_val = (rr >> RR_PS_SHIFT) & RR_PS_MASK; + printf(" [%d] %06lx %02x %s %ld\n", + num, + (rr >> RR_RID_SHIFT) & RR_RID_MASK, + ps_val, get_ps (ps_val), + rr & RR_VE_MASK); +} + +void print_rr(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + int i; + + printf (" rr: rid ps ve\n"); + for (i = 0; i < 8; i++) + print_a_rr (i, regs->rr[i]); +} + +void print_db(vcpu_guest_context_t *ctx) +{ + struct vcpu_guest_context_regs *regs = &ctx->regs; + int i; + + for (i = 0; i < 7; i += 2) + printf (" ibr[%d]: %016lx ibr[%d]: %016lx\n", + i, regs->ibr[i], i + 1, regs->ibr[i + 1]); + printf ("\n"); + for (i = 0; i < 7; i += 2) + printf (" dbr[%d]: %016lx dbr[%d]: %016lx\n", + i, regs->dbr[i], i + 1, regs->dbr[i + 1]); +} + +struct bit_descr { + const char *name; + unsigned char sz; +}; + +const struct bit_descr psr_bits[] = + { + {"", 1 }, {"be", 1 }, {"up", 1 }, {"ac", 1 }, + {"mfl", 1 }, {"mfh", 1 }, {"", 7 }, + {"ic", 1 }, {"i", 1 }, {"pk", 1 }, + {"", 1 }, {"dt", 1 }, {"dfl", 1 }, {"dfh", 1 }, + {"sp", 1 }, {"pp", 1 }, {"di", 1 }, {"si", 1 }, + {"db", 1 }, {"lp", 1 }, {"tb", 1 }, {"rt", 1 }, + {"", 4 }, + {"cpl", 2 }, {"is", 1 }, {"mc", 1 }, + {"it", 1 }, {"id", 1 }, {"da", 1 }, {"dd", 1 }, + {"ss", 1 }, {"ri", 2 }, {"ed", 1 }, + {"bn", 1 }, {"ia", 1 }, {"vm", 1 }, + {NULL, 0 } + }; + +void print_bits(const struct bit_descr *desc, unsigned long val) +{ + const struct bit_descr *d; + unsigned int off; + + /* Reverse order. */ + for (d = desc, off = 0; d->name; d++) + off += d->sz; + d--; + + while (1) { + off -= d->sz; + if (*d->name) { + if (d->sz != 1 || ((val >> off) & 1)) + printf(" %s", d->name); + if (d->sz != 1) + printf("=%lx", (val >> off) & ((1 << d->sz) - 1)); + } + if (d == desc) + break; + d--; + } +} + +void print_tr(vcpu_guest_context_t *ctx) +{ + struct vcpu_tr_regs *tr = &ctx->regs.tr; + int i; + + printf("\n itr: P rid va pa ps ed pl " + "ar a d ma key\n"); + for (i = 0; i < 8; i++) + print_a_tr(i, &tr->itrs[i]); + printf("\n dtr: P rid va pa ps ed pl " + "ar a d ma key\n"); + for (i = 0; i < 8; i++) + print_a_tr(i, &tr->dtrs[i]); +} + +int lock_pages(void *addr, size_t len); +void unlock_pages(void *addr, size_t len); +int do_xen_hypercall(int xc_handle, privcmd_hypercall_t *hypercall); + +#ifdef HAVE_DEBUG_OP +static int do_ia64_debug_op(int xc_handle, + unsigned long cmd, unsigned long domain, + xen_ia64_debug_op_t *op) +{ + int ret = -1; + privcmd_hypercall_t hypercall; + + hypercall.op = __HYPERVISOR_ia64_debug_op; + hypercall.arg[0] = cmd; + hypercall.arg[1] = domain; + hypercall.arg[2] = (unsigned long)op; + + if ( lock_pages(op, sizeof(*op)) != 0 ) + { + perror("Could not lock memory for Xen hypercall"); + goto out1; + } + + if ( (ret = do_xen_hypercall(xc_handle, &hypercall)) < 0 ) + { + if ( errno == EACCES ) + fprintf(stderr,"domctl operation failed -- need to" + " rebuild the user-space tool set?\n"); + } + + unlock_pages(op, sizeof(*op)); + + out1: + return ret; +} +#endif + +static volatile int ctrl_c_hit; + +void ctrl_c_handler (int sig) +{ + fflush (stdout); + ctrl_c_hit = 1; +} + +int wait_domain(int vcpu, vcpu_guest_context_t *ctx) +{ + struct timespec ts; + xc_dominfo_t dominfo; + int ret; + int cnt = 0; + + ts.tv_sec = 0; + ts.tv_nsec = 10*1000*1000; + + ret = xc_domain_unpause(xc_handle, domid); + if (ret < 0) { + perror("xc_domain_unpause"); + } + ctrl_c_hit = 0; + while (1) { + ret = xc_domain_getinfo(xc_handle, domid, 1, &dominfo); + if (ret < 0) { + perror("xc_domain_getinfo"); + } + if (dominfo.paused) + break; + if (ctrl_c_hit) { + /* Force pause. */ + ret = xc_domain_pause(xc_handle, domid); + if (ret < 0) { + perror("xc_domain_pause"); + } + break; + } + + printf ("%c\b", "/-\\|"[(cnt++) % 4]); + fflush (stdout); + nanosleep(&ts,NULL); + } + return xc_vcpu_getcontext(xc_handle, domid, vcpu, ctx); +} + +int virt_to_phys (int is_inst, unsigned long vaddr, unsigned long *paddr) +{ + struct ia64_tr_entry *tr; + int i; + + /* Search in tr. */ + if (is_inst) + tr = cur_ctx->regs.tr.itrs; + else + tr = cur_ctx->regs.tr.dtrs; + for (i = 0; i < 8; i++, tr++) { + int ps_val = (tr->itir >> ITIR_PS_SHIFT) & ITIR_PS_MASK; + unsigned long ps_mask = (-1L) << ps_val; + if ((tr->vadr & ps_mask) == (vaddr & ps_mask)) { + *paddr = ((tr->pte & (PTE_PPN_MASK << PTE_PPN_SHIFT)) & ps_mask) + | (vaddr & ~ps_mask); + return 0; + } + } + return -1; +} + +unsigned long * +get_reg_addr (const char *name) +{ + if (strcmp (name, "ip") == 0) + return &cur_ctx->regs.ip; + else if (strcmp (name, "psr") == 0) + return &cur_ctx->regs.psr; + else + return 0; +} + +enum prio_expr {EXPR_BASE, EXPR_SUM, EXPR_LOGIC, EXPR_PROD}; + +int parse_expr (unsigned char **buf, unsigned long *res, enum prio_expr prio); + +int next_char (unsigned char **buf) +{ + unsigned char *b; + + b = *buf; + while (isspace (*b)) + b++; + *buf = b; + return *b; +} + +int parse_unary (unsigned char **buf, unsigned long *res) +{ + unsigned char c; + + c = next_char (buf); + switch (c) { + case '0' ... '9': + { + char *e; + *res = strtoul (*buf, &e, 0); + if (e == (char *)*buf) { + printf ("bad literal\n"); + return -1; + } + *buf = e; + } + break; + case '+': + (*buf)++; + return parse_unary (buf, res); + case '$': + { + unsigned char *b; + unsigned char *e; + unsigned char c; + unsigned long *reg; + int len; + + b = *buf; + e = b + 1; + while ((*e >= 'a' && *e <= 'z') + || (*e >= 'A' && *e <= 'Z') + || (*e >= '0' && *e <= '9') + || (*e == '_' || *e == '.')) + e++; + if (b == e) { + printf ("identifier missing after '$'\n"); + return -1; + } + b++; + len = e - b; + + c = b[len]; + b[len] = 0; + reg = get_reg_addr (b); + b[len] = c; + + if (reg != NULL) + *res = *reg; + else if (strncmp (b, "d2p", len) == 0 + || strncmp (b, "i2p", len) == 0) { + unsigned long vaddr; + *buf = e; + if (parse_unary (buf, &vaddr) != 0) + return -1; + if (virt_to_phys (*b == 'i', vaddr, res) != 0) { + printf ("cannot find vaddr %016lx in tr\n", vaddr); + return -1; + } + return 0; + } + else { + printf ("unknown symbol\n"); + return -1; + } + *buf = e; + } + break; + case '(': + (*buf)++; + if (parse_expr (buf, res, EXPR_BASE) != 0) + return -1; + if (next_char (buf) != ')') { + printf ("missing ')'\n"); + return -1; + } + else + (*buf)++; + break; + default: + printf ("unknown operand '%c' in expression\n", c); + return -1; + } + return 0; +} + +int parse_expr (unsigned char **buf, unsigned long *res, enum prio_expr prio) +{ + unsigned long val = 0; + unsigned long val1; + + if (parse_unary (buf, &val) != 0) + return -1; + + while (1) { + switch (next_char(buf)) { + case '+': + if (prio > EXPR_SUM) + return 0; + (*buf)++; + if (parse_expr (buf, &val1, EXPR_SUM) < 0) + return -1; + val += val1; + break; + case '*': + if (prio > EXPR_PROD) + return 0; + (*buf)++; + if (parse_expr (buf, &val1, EXPR_SUM) < 0) + return -1; + val *= val1; + break; + default: + *res = val; + return 0; + } + } +} + +unsigned char *parse_arg (unsigned char **buf) +{ + unsigned char *res; + unsigned char *b = *buf; + + /* Eat leading spaces. */ + while (isspace (*b)) + b++; + + res = b; + while (*b && !isspace (*b)) + b++; + + /* Set the NUL terminator. */ + if (*b) + *b++ = 0; + + *buf = b; + return res; +} + +vcpu_guest_context_t vcpu_ctx[1]; + +int vcpu_setcontext (int vcpu) +{ + int ret; + + ret = xc_vcpu_setcontext(xc_handle, domid, vcpu, &vcpu_ctx[vcpu]); + if (ret < 0) + perror("xc_vcpu_setcontext"); + return ret; +} + +struct command_desc +{ + const char *name; + const char *help; + int (*cmd)(unsigned char *line); +}; + +static int +cmd_registers (unsigned char *line) +{ + print_ctx (cur_ctx); + return 0; +} + +static int +cmd_sstep (unsigned char *line) +{ + if ((cur_ctx->regs.psr & (PSR_SS | PSR_TB)) != PSR_SS) { + cur_ctx->regs.psr |= PSR_SS; + cur_ctx->regs.psr &= ~PSR_TB; + if (vcpu_setcontext(cur_vcpu) < 0) + return -1; + } + if (wait_domain (cur_vcpu, cur_ctx) < 0) { + perror("wait_domain"); + return -1; + } + print_ctx (cur_ctx); + return 0; +} + +static int +cmd_go (unsigned char *line) +{ + if ((cur_ctx->regs.psr & (PSR_SS | PSR_TB | PSR_DB)) != 0) { + cur_ctx->regs.psr &= ~(PSR_SS | PSR_TB); + cur_ctx->regs.psr |= PSR_DD | PSR_ID; + if (vcpu_setcontext(cur_vcpu) < 0) + return -1; + } + if (wait_domain (cur_vcpu, cur_ctx) < 0) { + perror("wait_domain"); + return -1; + } + print_ctx (cur_ctx); + return 0; +} + +static int +cmd_cb (unsigned char *line) +{ + if ((cur_ctx->regs.psr & (PSR_SS | PSR_TB)) != PSR_TB) { + cur_ctx->regs.psr &= ~PSR_SS; + cur_ctx->regs.psr |= PSR_TB; + if (vcpu_setcontext(cur_vcpu) < 0) + return -1; + } + if (wait_domain (cur_vcpu, cur_ctx) < 0) { + perror("wait_domain"); + return -1; + } + print_ctx (cur_ctx); + return 0; +} + +static int +cmd_quit (unsigned char *line) +{ + return -2; +} + +static int +cmd_echo (unsigned char *line) +{ + printf ("%s", line); + return 0; +} + +static int +cmd_disassemble (unsigned char *args) +{ + static unsigned long addr; + if (*args != 0) + if (parse_expr (&args, &addr, 0) < 0) + return -1; + target_disas(stdout, addr, 16); + addr += 16; + return 0; +} + +static int +cmd_break (unsigned char *args) +{ + unsigned long addr; + int i; + for (i = 0; i < 4; i++) + if (cur_ctx->regs.ibr[2 * i] == 0 + && cur_ctx->regs.ibr[2 * i + 1] == 0) + break; + if (i == 4) { + printf ("no availabe break points\n"); + return -1; + } + if (parse_expr (&args, &addr, 0) < 0) + return -1; + cur_ctx->regs.ibr[2 * i] = addr; + cur_ctx->regs.ibr[2 * i + 1] = 0x87fffffffffffff0UL; + cur_ctx->regs.psr |= PSR_DB; + return vcpu_setcontext(cur_vcpu); +} + +static int +cmd_watch (unsigned char *args) +{ + unsigned long addr; + unsigned long mask; + int i; + for (i = 0; i < 4; i++) + if (cur_ctx->regs.dbr[2 * i] == 0 + && cur_ctx->regs.dbr[2 * i + 1] == 0) + break; + if (i == 4) { + printf ("no availabe watch points\n"); + return -1; + } + if (parse_expr (&args, &addr, 0) < 0) + return -1; + if (parse_expr (&args, &mask, 0) < 0) + mask = 3; + cur_ctx->regs.dbr[2 * i] = addr; + cur_ctx->regs.dbr[2 * i + 1] = ~((1UL << mask) - 1) | (0xc7UL << 56); + cur_ctx->regs.psr |= PSR_DB; + return vcpu_setcontext(cur_vcpu); +} + +static int +cmd_delete (unsigned char *args) +{ + unsigned long num; + if (parse_expr (&args, &num, 0) < 0) + return -1; + if (num < 4) { + cur_ctx->regs.ibr[2 * num] = 0; + cur_ctx->regs.ibr[2 * num + 1] = 0; + } + else if (num < 8) { + num -= 4; + cur_ctx->regs.dbr[2 * num] = 0; + cur_ctx->regs.dbr[2 * num + 1] = 0; + } + else { + printf ("breakpoint out of range\n"); + return -1; + } + cur_ctx->regs.psr |= PSR_DB; + return vcpu_setcontext(cur_vcpu); +} + +static int +cmd_disable (unsigned char *args) +{ + unsigned long num; + if (parse_expr (&args, &num, 0) < 0) + return -1; + if (num >= 4) { + printf ("breakpoint out of range\n"); + return -1; + } + cur_ctx->regs.ibr[2 * num + 1] &= ~(1UL << 63); + return vcpu_setcontext(cur_vcpu); +} + +static int +cmd_enable (unsigned char *args) +{ + unsigned long num; + if (parse_expr (&args, &num, 0) < 0) + return -1; + if (num >= 4) { + printf ("breakpoint out of range\n"); + return -1; + } + cur_ctx->regs.ibr[2 * num + 1] |= 1UL << 63; + return vcpu_setcontext(cur_vcpu); +} + +static int +cmd_print (unsigned char *args) +{ + unsigned long addr; + if (parse_expr (&args, &addr, 0) < 0) + return -1; + printf ("res: 0x%016lx = %ld\n", addr, addr); + return 0; +} + +struct bit_xlat { + unsigned int bit; + const char *name; +}; + +static const struct bit_xlat debug_flags[] = { + { XEN_IA64_DEBUG_ON_KERN_SSTEP, "sstep" }, + { XEN_IA64_DEBUG_ON_KERN_DEBUG, "debug" }, + { XEN_IA64_DEBUG_ON_KERN_TBRANCH, "tbranch" }, + { XEN_IA64_DEBUG_ON_EXTINT, "extint" }, + { XEN_IA64_DEBUG_ON_EXCEPT, "except" }, + { XEN_IA64_DEBUG_ON_EVENT, "event" }, + { XEN_IA64_DEBUG_ON_PRIVOP, "privop" }, + { XEN_IA64_DEBUG_ON_PAL, "pal" }, + { XEN_IA64_DEBUG_ON_SAL, "sal" }, + { XEN_IA64_DEBUG_ON_EFI, "efi" }, + { XEN_IA64_DEBUG_ON_RFI, "rfi" }, + { XEN_IA64_DEBUG_ON_MMU, "mmu" }, + { XEN_IA64_DEBUG_ON_BAD_MPA, "mpa" }, + { XEN_IA64_DEBUG_FORCE_SS, "ss" }, + { XEN_IA64_DEBUG_FORCE_DB, "db" }, + { XEN_IA64_DEBUG_ON_TR, "tr" }, + { XEN_IA64_DEBUG_ON_TC, "tc" }, + { 0, NULL } +}; + +static int +cmd_disp (unsigned char *arg) +{ + if (strcmp (arg, "br") == 0) + print_br (cur_ctx); + else if (strcmp (arg, "regs") == 0) + print_regs (cur_ctx); + else if (strcmp (arg, "cr") == 0) + print_cr (cur_ctx); + else if (strcmp (arg, "ar") == 0) + print_ar (cur_ctx); + else if (strcmp (arg, "tr") == 0) + print_tr (cur_ctx); + else if (strcmp (arg, "rr") == 0) + print_rr (cur_ctx); + else if (strcmp (arg, "db") == 0) + print_db (cur_ctx); + else if (strcmp (arg, "psr") == 0) { + printf ("psr:"); + print_bits(psr_bits, cur_ctx->regs.psr); + printf ("\n"); + } + else if (strcmp (arg, "ipsr") == 0) { + printf ("ipsr:"); + print_bits(psr_bits, cur_ctx->regs.cr.ipsr); + printf ("\n"); + } + else if (strcmp (arg, "break") == 0) { + int i; + for (i = 0; i < 4; i++) + if (cur_ctx->regs.ibr[2 * i + 1]) + printf ("%d: 0x%016lx %s\n", i, cur_ctx->regs.ibr[2 * i], + (cur_ctx->regs.ibr[2 * i + 1] & (1UL << 63)) ? + "enabled" : "disabled"); + } + else if (strcmp (arg, "domain") == 0) { + xc_dominfo_t dominfo; +#ifdef HAVE_DEBUG_OP + xen_ia64_debug_op_t debug_op; + int i; +#endif + if (xc_domain_getinfo(xc_handle, domid, 1, &dominfo) < 0) { + perror("xc_domain_getinfo"); + return 0; + } + printf ("id=%d nr_pages=%lu shared_info_frame=%lu max_mem=%luKB\n", + dominfo.domid, dominfo.nr_pages, dominfo.shared_info_frame, + dominfo.max_memkb); + printf (" nr_online_vcpu=%u max_vcpu_id=%u\n", + dominfo.nr_online_vcpus, dominfo.max_vcpu_id); + printf (" status:"); + if (dominfo.dying) + printf (" dying"); + if (dominfo.crashed) + printf (" crashed"); + if (dominfo.shutdown) + printf (" shutdown(%u)", dominfo.shutdown_reason); + if (dominfo.paused) + printf (" paused"); + if (dominfo.blocked) + printf (" blocked"); + if (dominfo.running) + printf (" running"); + if (dominfo.hvm) + printf (" hvm"); + printf ("\n"); + +#ifdef HAVE_DEBUG_OP + if (do_ia64_debug_op(xc_handle, XEN_IA64_DEBUG_OP_GET_FLAGS, + domid, &debug_op) < 0) { + perror("xc_domain_getinfo"); + return 0; + } + printf ("debug flags: %08lx: ", debug_op.flags); + for (i = 0; debug_flags[i].name; i++) + if (debug_flags[i].bit & debug_op.flags) + printf (" %s", debug_flags[i].name); + printf ("\n"); +#endif + } + else if (*arg == 0) + printf ("choose among br, regs, cr, ar, tr, rr, dbg\n"); + else + printf ("cannot disp '%s'\n", arg); + return 0; +} + +static int +cmd_bev (unsigned char *arg) +{ + xen_ia64_debug_op_t debug_op; + int i; + + if (do_ia64_debug_op(xc_handle, XEN_IA64_DEBUG_OP_GET_FLAGS, + domid, &debug_op) < 0) { + perror("get debug flags"); + return 0; + } + if (arg == NULL || arg[0] == 0) { + printf ("debug flags: %08lx:\n", debug_op.flags); + for (i = 0; debug_flags[i].name; i++) + printf (" %c%s\n", + (debug_flags[i].bit & debug_op.flags) ? '+' : '-', + debug_flags[i].name); + return 0; + } + else { + char *p = strtok (arg, " "); + while (p != NULL) { + unsigned int flag = 0; + for (i = 0; debug_flags[i].name; i++) + if (strcmp (p, debug_flags[i].name) == 0 + || ((p[0] == '-' || p[0] == '+') + && strcmp (p + 1, debug_flags[i].name) == 0)) { + flag = debug_flags[i].bit; + break; + } + if (flag == 0) { + printf ("unknown event %s\n", p); + return 0; + } + if (p[0] == '-') + debug_op.flags &= ~flag; + else + debug_op.flags |= flag; + + p = strtok (NULL, " "); + } + if (do_ia64_debug_op(xc_handle, XEN_IA64_DEBUG_OP_SET_FLAGS, + domid, &debug_op) < 0) { + perror("set debug flags"); + return -1; + } + /* Disabling force_SS and force_DB requires setting psr. */ + return vcpu_setcontext(cur_vcpu); + } +} + +static int +cmd_set (unsigned char *line) +{ + unsigned char *reg; + unsigned long *addr; + unsigned long val; + + reg = parse_arg (&line); + + addr = get_reg_addr (reg); + if (addr == NULL) { + printf ("unknown register %s\n", reg); + return -1; + } + if (parse_expr (&line, &val, 0) < 0) + return -1; + *addr = val; + return vcpu_setcontext(cur_vcpu); +} + +const struct command_desc commands[]; + +static int +cmd_help (unsigned char *line) +{ + int i; + + for (i = 0; commands[i].name; i++) + printf ("%s -- %s\n", commands[i].name, commands[i].help); + return 0; +} + +const struct command_desc commands[] = { + { "registers", "display current registers", cmd_registers }, + { "sstep", "single step", cmd_sstep }, + { "go", "resume execution", cmd_go }, + { "quit", "quit debugger", cmd_quit }, + { "echo", "display parameters", cmd_echo }, + { "disassemble", "disassemble memory", cmd_disassemble }, + { "break", "set a break point", cmd_break }, + { "watch", "set a watch point", cmd_watch }, + { "cb", "resume until branch", cmd_cb }, + { "delete", "delete a break point", cmd_delete }, + { "disable", "disable a break point", cmd_disable }, + { "enable", "enable a break point", cmd_enable }, + { "print", "print an expression", cmd_print }, + { "disp", "disp br/regs/cr/ar/tr/rr/db/psr/break/domain", cmd_disp}, + { "bev", "break on event", cmd_bev}, + { "set", "set reg val", cmd_set}, + { "help", "disp help", cmd_help }, + { NULL, NULL } +}; + + +int do_command (int vcpu, unsigned char *line) +{ + unsigned char *cmd; + unsigned char *args; + int i; + const struct command_desc *desc; + int flag_ambiguous; + + cur_vcpu = vcpu; + cur_ctx = &vcpu_ctx[vcpu]; + + cmd = parse_arg (&line); + args = line; + + desc = NULL; + flag_ambiguous = 0; + for (i = 0; commands[i].name; i++) { + const char *n = commands[i].name; + unsigned char *c = cmd; + while (*n == *c && *n) + n++, c++; + if (*c == 0) { + /* Match. */ + if (desc != NULL) { + if (!flag_ambiguous) + printf ("ambiguous command: %s", desc->name); + printf (", %s", commands[i].name); + flag_ambiguous = 1; + } + else + desc = &commands[i]; + } + } + if (flag_ambiguous) { + printf ("\n"); + return -3; + } + else if (!desc) { + printf ("command not found, try help\n"); + return -3; + } + + return (*desc->cmd)(args); +} + +void xenitp(int vcpu) +{ + int ret; + xc_dominfo_t dominfo; + struct sigaction sa; + + cur_ctx = &vcpu_ctx[vcpu]; + + xc_handle = xc_interface_open(); /* for accessing control interface */ + + ret = xc_domain_getinfo(xc_handle, domid, 1, &dominfo); + if (ret < 0) { + perror("xc_domain_getinfo"); + exit(-1); + } + + if (xc_domain_setdebugging (xc_handle, domid, 1) != 0) + perror("setdebugging"); + + ret = xc_domain_pause(xc_handle, domid); + if (ret < 0) { + perror("xc_domain_pause"); + exit(-1); + } + + ret = xc_vcpu_getcontext(xc_handle, domid, vcpu, cur_ctx); + if (ret < 0) { + if (!dominfo.paused) + xc_domain_unpause(xc_handle, domid); + perror("xc_vcpu_getcontext"); + exit(-1); + } + + print_ctx(cur_ctx); + + /* Catch ctrl-c. */ + sa.sa_handler = &ctrl_c_handler; + sa.sa_flags = 0; + sigemptyset (&sa.sa_mask); + if (sigaction (SIGINT, &sa, NULL) != 0) + perror ("sigaction"); + + while (1) { + unsigned char buf[128]; + int len; + printf ("XenITP> "); + + if (fgets (buf, sizeof (buf), stdin) == NULL) + break; + len = strlen (buf); + if (len > 1 && buf[len - 1] == '\n') + buf[len - 1] = 0; + + ret = do_command (vcpu, buf); + if (ret == -2) + break; + } + + /* Clear debug bits. */ + if ((cur_ctx->regs.psr & (PSR_SS | PSR_TB | PSR_DB)) != 0) { + cur_ctx->regs.psr &= ~(PSR_SS | PSR_TB | PSR_DB); + cur_ctx->regs.psr |= PSR_DD | PSR_ID; + vcpu_setcontext(cur_vcpu); + } + + /* Disable debugging. */ + if (xc_domain_setdebugging (xc_handle, domid, 0) != 0) + perror("setdebugging"); + + if (!dominfo.paused) { + ret = xc_domain_unpause(xc_handle, domid); + if (ret < 0) { + perror("xc_domain_unpause"); + exit(-1); + } + } + + xc_interface_close(xc_handle); + if (ret < 0) { + perror("xc_interface_close"); + exit(-1); + } +} + +static void usage(void) +{ + printf("usage:\n"); + printf(" xenitp [VCPU]\n"); + +} + +int main(int argc, char **argv) +{ + int ch; + static const char *sopts = "h" + ; + static const struct option lopts[] = { + {"help", 0, NULL, 'h'}, + {0, 0, 0, 0} + }; + int vcpu = 0; + + while ((ch = getopt_long(argc, argv, sopts, lopts, NULL)) != -1) { + switch(ch) { + case 'h': + usage(); + exit(-1); + case '?': + fprintf(stderr, "%s --help for more options\n", argv[0]); + exit(-1); + } + } + + argv += optind; argc -= optind; + + if (argc < 1 || argc > 2) { + usage (); + exit(-1); + } + + domid = atoi(argv[0]); + if (domid == 0) { + fprintf(stderr, "cannot trace dom0\n"); + exit(-1); + } + + if (argc == 2) + vcpu = atoi(argv[1]); + + xenitp(vcpu); + + return 0; +} + +/* + * Local variables: + * mode: C + * c-set-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */