Hi,
this patch adds minimal support for domU long vhpt format.
It is built on top of my previous patch (hyperprivop.S).
Changes are:
- allow setting of long format vhpt in pta
- check for long format only if vhpt access is really needed (enabled in
region register and pta)
- never find a long vhpt entry, always reflect to domU handler
Tested by boot of dom0 and "special" mini-os with long vhpt configured
Juergen
--
Juergen Gross Principal Developer
IP SW OS6 Telephone: +49 (0) 89 636 47950
Fujitsu Siemens Computers e-mail: juergen.gross@xxxxxxxxxxxxxxxxxxx
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# HG changeset patch
# User gross@xxxxxxxxxxxxxxxxxxxx
# Node ID 6b0c965e95a668bf65d475f519b254107cce21a3
# Parent 5dba504a7fbfee618b8753815d239be4cfc44b7e
minimal long vhpt format support
Signed-off-by: Juergen Gross juergen.gross@xxxxxxxxxxxxxxxxxxx
diff -r 5dba504a7fbf -r 6b0c965e95a6 xen/arch/ia64/xen/hyperprivop.S
--- a/xen/arch/ia64/xen/hyperprivop.S Tue Aug 7 11:31:36 2007 +0200
+++ b/xen/arch/ia64/xen/hyperprivop.S Thu Aug 9 08:48:00 2007 +0200
@@ -844,19 +844,19 @@ fast_tlb_no_tr_match:
1: // check the guest VHPT
adds r19 = XSI_PTA_OFS-XSI_PSR_IC_OFS, r18;;
- ld8 r19=[r19];;
- tbit.nz p7,p0=r19,IA64_PTA_VF_BIT;; // long format VHPT
-(p7) br.cond.spnt.few page_fault;;
+ ld8 r19=[r19]
// if (!rr.ve || !(pta & IA64_PTA_VE)) take slow way for now
// FIXME: later, we deliver an alt_d/i vector after thash and itir
- tbit.z p7,p0=r19,IA64_PTA_VE_BIT
-(p7) br.cond.spnt.few page_fault;;
extr.u r25=r17,61,3
adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
shl r25=r25,3;;
add r21=r21,r25;;
ld8 r22=[r21];;
tbit.z p7,p0=r22,0
+(p7) br.cond.spnt.few page_fault;;
+ tbit.z p7,p0=r19,IA64_PTA_VE_BIT
+(p7) br.cond.spnt.few page_fault;;
+ tbit.nz p7,p0=r19,IA64_PTA_VF_BIT // long format VHPT
(p7) br.cond.spnt.few page_fault;;
// compute and save away itir (r22 & RR_PS_MASK)
diff -r 5dba504a7fbf -r 6b0c965e95a6 xen/arch/ia64/xen/vcpu.c
--- a/xen/arch/ia64/xen/vcpu.c Tue Aug 7 11:31:36 2007 +0200
+++ b/xen/arch/ia64/xen/vcpu.c Thu Aug 9 08:48:00 2007 +0200
@@ -49,7 +49,6 @@ typedef union {
#define IA64_PTA_SZ_BIT 2
#define IA64_PTA_VF_BIT 8
#define IA64_PTA_BASE_BIT 15
-#define IA64_PTA_LFMT (1UL << IA64_PTA_VF_BIT)
#define IA64_PTA_SZ(x) (x##UL << IA64_PTA_SZ_BIT)
#define IA64_PSR_NON_VIRT_BITS \
@@ -755,10 +754,6 @@ IA64FAULT vcpu_set_iva(VCPU * vcpu, u64
IA64FAULT vcpu_set_pta(VCPU * vcpu, u64 val)
{
- if (val & IA64_PTA_LFMT) {
- printk("*** No support for VHPT long format yet!!\n");
- return IA64_ILLOP_FAULT;
- }
if (val & (0x3f << 9)) /* reserved fields */
return IA64_RSVDREG_FAULT;
if (val & 2) /* reserved fields */
@@ -1753,10 +1748,6 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u6
/* check guest VHPT */
pta = PSCB(vcpu, pta);
- if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
- panic_domain(vcpu_regs(vcpu), "can't do long format VHPT\n");
- //return is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR;
- }
*itir = rr & (RR_RID_MASK | RR_PS_MASK);
// note: architecturally, iha is optionally set for alt faults but
@@ -1778,6 +1769,11 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u6
IA64_ALT_INST_TLB_VECTOR;
}
+ if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
+ /* minimal support: vhpt walker is really dumb and won't find
+ anything */
+ return is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR;
+ }
/* avoid recursively walking (short format) VHPT */
if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
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