Re: [Xen-ia64-devel] [PATCH] fix I&D cache incoherency after vcpu migration

[Kouya SHIMURA <kouya@xxxxxxxxxxxxxx>]

Hi Alex,

next->arch.cache_coherent_map is a private data in struct vcpu.
Only PAL_CACHE_FLUSH set it and the other vcpus never touch it.
So it is not racy. 
I think it might be too exaggerated to use atomic cpu_test_and_clear().

Thanks, 
Kouya

Alex Williamson writes:
 > On Tue, 2007-02-13 at 21:15 +0900, Kouya SHIMURA wrote:
 > > +static void flush_cache_for_context_switch(struct vcpu *next)
 > > +{
 > > +       extern cpumask_t cpu_cache_coherent_map;
 > > +       int cpu = smp_processor_id();
 > > +
 > > +       if (is_idle_vcpu(next) ||
 > > +           __test_and_clear_bit(cpu, &next->arch.cache_coherent_map))
 > > { 
 > 
 > Hi Kouya,
 > 
 >    Isn't this racey?  Why use the non-atomic __test_and_clear_bit() here
 > rather than the atomic version?  Thanks,
 > 
 >      Alex
 > 
 > -- 
 > Alex Williamson                             HP Open Source & Linux Org.


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