[Xen-ia64-devel] [PATCH 9/12][RFC]MCA handler support for Xen/ia64

[SUZUKI Kazuhiro <kaz@xxxxxxxxxxxxxx>]

[9/12]  Add MCA offset.[mca-asm-offset.patch]

Signed-off-by: Yutaka Ezaki <yutaka.ezaki@xxxxxxxxxxxxxx>
Signed-off-by: Masaki Kanno <kanno.masaki@xxxxxxxxxxxxxx>
Signed-off-by: SUZUKI Kazuhiro <kaz@xxxxxxxxxxxxxx>

diff -r 685bf9b75eb1 xen/arch/ia64/asm-offsets.c
--- a/xen/arch/ia64/asm-offsets.c       Mon Sep 04 14:48:03 2006 -0600
+++ b/xen/arch/ia64/asm-offsets.c       Wed Sep 06 14:03:52 2006 +0900
@@ -12,6 +12,7 @@
 #include <public/xen.h>
 #include <asm/tlb.h>
 #include <asm/regs.h>
+#include <asm/xenmca.h>
 
 #define task_struct vcpu
 
@@ -217,4 +218,32 @@ void foo(void)
        DEFINE(FAST_HYPERPRIVOP_PERFC_OFS, offsetof (struct perfcounter, 
fast_hyperprivop));
        DEFINE(FAST_REFLECT_PERFC_OFS, offsetof (struct perfcounter, 
fast_reflect));
 #endif
+
+       BLANK();
+       DEFINE(IA64_CPUINFO_PTCE_BASE_OFFSET,
+              offsetof (struct cpuinfo_ia64, ptce_base));
+       DEFINE(IA64_CPUINFO_PTCE_COUNT_OFFSET,
+              offsetof (struct cpuinfo_ia64, ptce_count));
+       DEFINE(IA64_CPUINFO_PTCE_STRIDE_OFFSET,
+              offsetof (struct cpuinfo_ia64, ptce_stride));
+
+       BLANK();
+       DEFINE(IA64_MCA_CPU_PROC_STATE_DUMP_OFFSET,
+              offsetof (struct ia64_mca_cpu, proc_state_dump));
+       DEFINE(IA64_MCA_CPU_STACK_OFFSET,
+              offsetof (struct ia64_mca_cpu, stack));
+       DEFINE(IA64_MCA_CPU_STACKFRAME_OFFSET,
+              offsetof (struct ia64_mca_cpu, stackframe));
+       DEFINE(IA64_MCA_CPU_RBSTORE_OFFSET,
+              offsetof (struct ia64_mca_cpu, rbstore));
+
+       DEFINE(IA64_DOMAIN_SHARED_INFO_OFFSET,
+              offsetof (struct domain, shared_info));
+       DEFINE(IA64_DOMAIN_SHARED_INFO_VA_OFFSET,
+              offsetof (struct domain, arch.shared_info_va));
+
+       BLANK();
+       DEFINE(IA64_MCA_TLB_INFO_SIZE, sizeof (struct ia64_mca_tlb_info));
+       DEFINE(IA64_MCA_PERCPU_OFFSET,
+              offsetof (struct ia64_mca_tlb_info, percpu_paddr));
 }

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