# HG changeset patch
# User tristan.gingold@xxxxxxxx
# Node ID b21eca6faff71dd2b2cfca5c984d62c3380680c4
# Parent  ba84bc649c95330b6a37749af9ac1a7e5107e7f4
dom_rid_bits command line parameter added (set default domain rid bits).
panic_domain declared in domain.h

Signed-off-by: Tristan Gingold <tristan.gingold@xxxxxxxx>

diff -r ba84bc649c95 -r b21eca6faff7 xen/arch/ia64/xen/regionreg.c
--- a/xen/arch/ia64/xen/regionreg.c	Fri Apr 14 08:53:02 2006
+++ b/xen/arch/ia64/xen/regionreg.c	Fri Apr 14 10:10:19 2006
@@ -15,13 +15,20 @@
 #include <asm/regionreg.h>
 #include <asm/vhpt.h>
 #include <asm/vcpu.h>
+
+/* Defined in xemasm.S  */
 extern void ia64_new_rr7(unsigned long rid,void *shared_info, void *shared_arch_info, unsigned long p_vhpt, unsigned long v_pal);
+
 extern void *pal_vaddr;
 
-/* FIXME: where these declarations should be there ? */
-extern void panic_domain(struct pt_regs *, const char *, ...);
-
-#define DOMAIN_RID_BITS_DEFAULT 18
+/* RID virtualization mechanism is really simple:  domains have less rid bits
+   than the host and the host rid space is shared among the domains.
+   The host rid space is split into blocks of 2**IA64_MIN_IMPL_RID_BITS (= 18)
+   rids.  A domain may have one or more consecutive blocks.
+
+   The first block is special.  Xen use its own rid (0-7) from the first block
+   and the remaining entries are used for domain metaphysical rids.
+*/
 
 #define	IA64_MIN_IMPL_RID_BITS	(IA64_MIN_IMPL_RID_MSB+1)
 #define	IA64_MAX_IMPL_RID_BITS	24
@@ -34,6 +41,10 @@
 #define	MAX_RID_BLOCKS	(1 << (IA64_MAX_IMPL_RID_BITS-IA64_MIN_IMPL_RID_BITS))
 #define RIDS_PER_RIDBLOCK MIN_RIDS
 
+/* Default number of rid bits for domains.  */
+static unsigned int domain_rid_bits_default = IA64_MIN_IMPL_RID_BITS;
+integer_param("dom_rid_bits", domain_rid_bits_default); 
+
 #if 0
 // following already defined in include/asm-ia64/gcc_intrin.h
 // it should probably be ifdef'd out from there to ensure all region
@@ -90,10 +101,22 @@
 	if (implemented_rid_bits > IA64_MAX_IMPL_RID_BITS)
 		implemented_rid_bits = IA64_MAX_IMPL_RID_BITS;
 
+	/* Allow the creation of at least one domain.  */
+	if (domain_rid_bits_default > implemented_rid_bits - 1)
+		domain_rid_bits_default = implemented_rid_bits - 1;
+
+	/* Check for too small values.  */
+	if (domain_rid_bits_default < IA64_MIN_IMPL_RID_BITS) {
+		printf ("Default domain rid bits %d is too small, use %d\n",
+			domain_rid_bits_default, IA64_MIN_IMPL_RID_BITS);
+		domain_rid_bits_default = IA64_MIN_IMPL_RID_BITS;
+	}
+
 	log_blocks = (implemented_rid_bits - IA64_MIN_IMPL_RID_BITS);
 
 	printf ("Maximum of simultaneous domains: %d\n",
-		(1 << log_blocks) - 1);
+		(1 << (implemented_rid_bits - domain_rid_bits_default)) - 1);
+	
 
 	mp_rid_shift = IA64_MIN_IMPL_RID_BITS - log_blocks;
 	BUG_ON (mp_rid_shift < 3);
@@ -109,7 +132,7 @@
 	int i, j, n_rid_blocks;
 
 	if (ridbits == 0)
-		ridbits = DOMAIN_RID_BITS_DEFAULT;
+		ridbits = domain_rid_bits_default;
 
 	if (ridbits >= IA64_MAX_IMPL_RID_BITS)
 		ridbits = IA64_MAX_IMPL_RID_BITS - 1;
diff -r ba84bc649c95 -r b21eca6faff7 xen/include/asm-ia64/domain.h
--- a/xen/include/asm-ia64/domain.h	Fri Apr 14 08:53:02 2006
+++ b/xen/include/asm-ia64/domain.h	Fri Apr 14 10:10:19 2006
@@ -17,6 +17,10 @@
    If sync_only is true, only synchronize I&D caches,
    if false, flush and invalidate caches.  */
 extern void domain_cache_flush (struct domain *d, int sync_only);
+
+/* Cleanly crash the current domain with a message.  */
+extern void panic_domain(struct pt_regs *, const char *, ...)
+     __attribute__ ((noreturn, format (printf, 2, 3)));
 
 struct arch_domain {
     struct mm_struct *mm;