# HG changeset patch
# User yamahata@xxxxxxxxxxxxx
# Node ID b3a20899830d6e563733ee2db2f9d334f2406cf4
# Parent  7ed6c203efe9c79446ec21a6ba288c04e2ccee55
made translate_domain_pte() aware _PAGE_ED bits.
_PAGE_PPN_MASK doesn't mask ED bit.
ED bit must be handled explicitly.
This case can occur by vcpu_itc_d().

Signed-off-by: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>

diff -r 7ed6c203efe9 -r b3a20899830d xen/arch/ia64/xen/process.c
--- a/xen/arch/ia64/xen/process.c	Wed Apr 19 10:39:15 2006 -0600
+++ b/xen/arch/ia64/xen/process.c	Fri Apr 21 11:28:20 2006 +0900
@@ -87,9 +87,12 @@ unsigned long translate_domain_pte(unsig
 	struct domain *d = current->domain;
 	unsigned long mask, pteval2, mpaddr;
 
+    pteval &= ((1UL << 53) - 1);// ignore [63:53] bits
+
 	// FIXME address had better be pre-validated on insert
 	mask = ~itir_mask(itir);
-	mpaddr = ((pteval & _PAGE_PPN_MASK) & ~mask) | (address & mask);
+    mpaddr = (((pteval & ~_PAGE_ED) & _PAGE_PPN_MASK) & ~mask) |
+        (address & mask);
 	if (d == dom0) {
 		if (mpaddr < dom0_start || mpaddr >= dom0_start + dom0_size) {
 			/*
@@ -114,6 +117,7 @@ unsigned long translate_domain_pte(unsig
 	}
 	pteval2 = lookup_domain_mpa(d,mpaddr);
 	pteval2 &= _PAGE_PPN_MASK; // ignore non-addr bits
+	pteval2 |= (pteval & _PAGE_ED);
 	pteval2 |= _PAGE_PL_2; // force PL0->2 (PL3 is unaffected)
 	pteval2 = (pteval & ~_PAGE_PPN_MASK) | pteval2;
 	return pteval2;