RE: CONFIG_IA64_SPLIT_CACHE was: [Xen-ia64-devel] Console problem on domU on tip?

["Yang, Fred" <fred.yang@xxxxxxxxx>]

Dan,

You can goto
http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm to
download new SDM.  The psr.ic=1 in calling PAL had been implemented into
PAL since 2002, so is HP's PAL.

The correct way is to run with PSR.ic=1 and let TLB miss handler code to
handle Dside miss.

Please refer to section 11.9.2.1.3 Making PAL Procedure Calls in
Physical or Virtual Mode in SDM Volume#2.  It specifically called out
"with psr.ic=1 to handle any TLB faults that could occur" in the spec

So, Anthony's psr.ic=1 patch is still valid since Xen only maps PAL with
ITR not DTR

-Fred
 


Magenheimer, Dan (HP Labs Fort Collins) wrote:
> Just working for a brief time today...
> 
> I just committed a fix that changes the compile-time CONFIG
> to a run-time test.  Please verify that this runtime test
> works on the future processor.
> 
> Anthony, Fred -- If PAL code were not pinned, we would not
> get a nested DTLB miss.
> 
> Kevin, Anthony -- The SDM description of the PAL_CACHE_FLUSH
> call states that psr.ic must be turned off for this call.
> (Note that my SDM is quite old so this may have changed
> in subsequent revisions.)
> 
> Dan


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