RE: [Xen-devel] [PATCH] scheduler rate controller

[Dario Faggioli <raistlin@xxxxxxxx>]

On Sat, 2011-10-29 at 10:05 +0800, Lv, Hui wrote:
> As you said, if applying the seveal_ms_delay, it will happen whenever system 
> is normal or not (excessive frequency). It may possible have the consequence 
> that 1)under normal condition, it will produce worse Qos than that without 
> applying such delay, 2) under excessive frequency condition, the mitigation 
> effect of 1ms-delay may be too weak. In addition, your idea is to delay 
> scheduling instead of reducing, which means the total number of scheduling 
> would probably not change.
>
I think it would. I mean, all the interrupts that arrive (and that are
causing TASKLET_SCHEDULE->schedule() right now) and see current vcpu not
having run for 1ms would collapse in just one call to schedule() at the
end of the 1ms delay from the time instant when the very first one
(interrupt) happened... Isn't it?

If yes, that would definitely reduce the number of calls to schedule().

> I think one possible solution, is to make the value of 1ms-delay adaptive 
> according to the system status (low load or high load). If so, SRC patch just 
> covered the excessive condition currently :). That's why I mentioned to treat 
> normal and excessive conditions separately and don't influence the normal 
> case as much as possible. Because we never know the consequence without 
> amount of testing work. :)
> 
Well, again, from my perspective, these numbers (1ms, 10ms) really looks
like ages, considering for example audio processing workloads with
software like JACK needs periodicity of 1.3 or 2.6 ms, and thus having
1ms or (for worse) 10ms eaten by the scheduler would definitely step on
their toes. I understand we're not talking very much about audio
processing VMs here but hey, if it has to be general purpose... :-P

> Some of my stupid thinking :)
> 
Same for mine. :-)

Thanks and Regards,
Dario

-- 
<<This happens because I choose it to happen!>> (Raistlin Majere)
----------------------------------------------------------------------
Dario Faggioli, http://retis.sssup.it/people/faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
PhD Candidate, ReTiS Lab, Scuola Superiore Sant'Anna, Pisa  (Italy)

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