Andrew, thanks for your response.
On Tue, Oct 04, 2011 at 05:50:17PM +0100, Andrew Cooper wrote:
>
> Do you mean that it is receiving interrupts for another device, or are
> you trying to pass through multiple interrupts for a device and the
> interrupt is appearing in the wrong event channel?
>
I am not sure I understand your question.
> Could you describe your hardware setup in detail please, especially
> AMD/Intel, IOMMU features in use according to Xen, and the PCI topology
> of the box.
Here's a description. I have a PCI device which supports SRIOV, so
there are several virtual functions besides the primary function. The
device generates interrupts using MSI-X. I bind one of the virtual
functions to the guest. The PCI device driver at the guest requests
msix vectors from kernel and gets two vectors. Then it calls
request_irq for those vectors.
When the device generates msix interrupt using the address/data in
it's msi-x table. However, the guest kernel complains the no handler
is registered for this vector. Specifically, I request_irq for vectors
48 and 49. When the device issues interrupt for vector 49, the guest
complains that it received interrupt for vector 89 which has no
handler routine.
>
> > I am
> > trying to understand how is the guest supposed to recieve the
> > interrupt: Is it handled by dom0 which is using event channels to pass
> > the interrupt to domU, or is handled directly by domU. Please send
> > pointers to the code.
>
> (I am not very familiar with guest IRQs so the following might not be
> accurate)
>
> For a PCI passthrough system, the interrupts should be bound directly to
> domU, with no dom0 interaction. A PIRQ is bound to an event channel
> using the EVTCHNOP_bind_pirq in common/event_channel.c, which should be
> set up by qemu for the relevant domU, when it is interpreting the PCI
> config space reads/writes.
My geust kernel is 2.6.32 based and I can't see any file with the name
event_channel.c.
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