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[Xen-devel] [PATCH][RFC] FPU LWP 0/5: patch description
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| Subject: | [Xen-devel] [PATCH][RFC] FPU LWP 0/5: patch description |
| From: | Wei Huang <wei.huang2@xxxxxxx> |
| Date: | Thu, 14 Apr 2011 15:37:27 -0500 |
| Delivery-date: | Thu, 14 Apr 2011 13:41:54 -0700 |
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The following patches support AMD lightweight profiling.Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to handle lazy and unlazy FPU states differently. Lazy FPU state (such as SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP, is saved and restored on each vcpu context switch. To simplify the code, we also add a mask option to xsave/xrstor function. Thanks, -Wei _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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