exporting patch:
# HG changeset patch
# User Wei Huang <wei.huang2@xxxxxxx>
# Date 1297376709 21600
# Node ID 705de1dacabeb899fae6e8121483b2d88d120e57
# Parent  20d10f3a6d4c6b7357da0cf35a9fe28100cb582d
Add LWP related feature flags.

diff -r 20d10f3a6d4c -r 705de1dacabe xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h	Thu Feb 10 16:17:01 2011 -0600
+++ b/xen/include/asm-x86/cpufeature.h	Thu Feb 10 16:25:09 2011 -0600
@@ -207,6 +207,8 @@
 
 #define cpu_has_xsave           boot_cpu_has(X86_FEATURE_XSAVE)
 
+#define cpu_has_lwp             boot_cpu_has(X86_FEATURE_LWP)
+
 #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 
 #define cpu_has_rdtscp          boot_cpu_has(X86_FEATURE_RDTSCP)
diff -r 20d10f3a6d4c -r 705de1dacabe xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h	Thu Feb 10 16:17:01 2011 -0600
+++ b/xen/include/asm-x86/msr-index.h	Thu Feb 10 16:25:09 2011 -0600
@@ -253,6 +253,10 @@
 #define MSR_AMD_PATCHLEVEL		0x0000008b
 #define MSR_AMD_PATCHLOADER		0xc0010020
 
+/* AMD Lightweight Profiling MSRs */
+#define MSR_AMD64_LWP_CFG                 0xc0000105
+#define MSR_AMD64_LWP_CBADDR              0xc0000106
+
 /* AMD OS Visible Workaround MSRs */
 #define MSR_AMD_OSVW_ID_LENGTH          0xc0010140
 #define MSR_AMD_OSVW_STATUS             0xc0010141