FYI. We are currently testing a patch that sharing EPT and VT-d page tables on
newer systems where both EPT and VT-d has the same page table format. There is
very little change in VT-d specific code. We just need to do IOTLB flushes in
appropriate places to support this.
-----Original Message-----
From: Keir Fraser [mailto:keir.xen@xxxxxxxxx] On Behalf Of Keir Fraser
Sent: Tuesday, December 07, 2010 10:01 AM
To: Wei Wang2; Kay, Allen M
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx; Tim Deegan
Subject: Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support -
implementation
Cc'ing Tim -- he could advise how plausible it is to find other available
bits to move the p2m types to. Also I'm not sure whether the p2m tables ever
get used as host pagetables these days (e.g., when guest has CR0.PG=0). That
could affect how difficult it is to mess with the p2m format.
If it's possible, though, it's probably worth pursuing. Sharing the tables
uses less memory, and could be less complicated code too.
-- Keir
On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@xxxxxxx> wrote:
> Hi Allen,
> Actually, each amd iommu pde entry uses bit 9-11 to encode next page table
> level, but these bits are also used as AVL bits by p2m table to encode
> different page types...So, it might not be quite easy to share NPT table with
> amd iommu unless we change p2m table encoding for this first.
> Thanks,
> Wei
>
> On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote:
>> Hi Wei,
>>
>> My understanding is that both EPT/NPT already supports 2M and 1G page
>> sizes. If this is true and if NPT supports the same page table format as
>> AMD iommu, shouldn't iommu 2M and 1G support just a matter of pointing
>> iommu page table pointer to NPT page table of the same guest OS thus
>> sharing the same page table between NPT and AMD iommu?
>>
>> This should save a lot code changes in iommu code. We just need to flush
>> iommu page table in IOTLB at appropriate places.
>>
>> Allen
>>
>> -----Original Message-----
>> From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
>> [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Wei Wang2 Sent:
>> Friday, December 03, 2010 8:04 AM
>> To: xen-devel@xxxxxxxxxxxxxxxxxxx
>> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support -
>> implementation
>>
>> This is the implementation.
>>
>> Thanks,
>> We
>> Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
>> --
>> Legal Information:
>> Advanced Micro Devices GmbH
>> Sitz: Dornach, Gemeinde Aschheim,
>> Landkreis München Registergericht München, HRB Nr. 43632
>> Geschäftsführer:
>> Alberto Bozzo, Andrew Bowd
>
>
>
>
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