This patch fixes the emulation of latency timer and header type.
The change set of cc1a204423475ff7a918b11d78b9ae637f320e23
deleted the header type register emulation.
On the other hand, the change set of ec5e52d5cb2e6f8851c345b7c3095fe2030fff9c
tries to update header type emulation, however it wrongly
touches latency timer emulation part.
I think this was caused by mis-merging. This patch sorts it out.
Cc: Dexuan Cui <dexuan.cui@xxxxxxxxx>
Cc: Masaki Kanno <kanno.masaki@xxxxxxxxxxxxxx>
Cc: Simon Horman <horms@xxxxxxxxxxxx>
Cc: Ian Jackson <Ian.Jackson@xxxxxxxxxxxxx>
Signed-off-by: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>
---
This is compile-tested only.
Please review/test it
---
hw/pass-through.c | 14 +++++++++++++-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/hw/pass-through.c b/hw/pass-through.c
index fadd358..5a76e8d 100644
--- a/hw/pass-through.c
+++ b/hw/pass-through.c
@@ -329,11 +329,23 @@ static struct pt_reg_info_tbl pt_emu_reg_header0_tbl[] = {
.init_val = 0x00,
.ro_mask = 0x00,
.emu_mask = 0xFF,
- .init = pt_header_type_reg_init,
+ .init = pt_common_reg_init,
.u.b.read = pt_byte_reg_read,
.u.b.write = pt_byte_reg_write,
.u.b.restore = pt_byte_reg_restore,
},
+ /* Header Type reg */
+ {
+ .offset = PCI_HEADER_TYPE,
+ .size = 1,
+ .init_val = 0x00,
+ .ro_mask = 0xFF,
+ .emu_mask = 0x00,
+ .init = pt_header_type_reg_init,
+ .u.b.read = pt_byte_reg_read,
+ .u.b.write = pt_byte_reg_write,
+ .u.b.restore = NULL,
+ },
/* Interrupt Line reg */
{
.offset = PCI_INTERRUPT_LINE,
--
1.6.6.1
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