On Thursday 28 January 2010 14:50:50 Jiang, Yunhong wrote:
> I checked Intel SDM manual, and it defined 0x400H to 0x457H for MCE MSR
> (that is in fact for bank 0~21). MSR 0x480 is for IA32_VMX_MSR. The range
> between 0x457 to 0x480 is undefined. And I didn't find any statement that
> all MSRs till for MAX_NR_BANKS are defined as MCE MSRs.
>
> Is the MAX_NR_BANKS defined clearly in AMD platform?
I don't know why we need/have MAX_NR_BANKS at all.
On AMD, the number of banks is reported by MSR_IA32_MCG_CAP bit MCG_CAP_COUNT.
Each bank has four MCE MSRs: CTRL, STATUS, ADDR and MISC.
We have struct mcinfo_bank for them.
MCE MSRs outside of them are covered by struct mcinfo_extended.
Christoph
>
> In fact, I'm abit curious how should the MAX_NR_BANKS defined. I checked
> the patch and seems it is originally 128, and later changed to 30.
>
> --jyh
>
> >-----Original Message-----
> >From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
> >[mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Christoph
> > Egger Sent: Thursday, January 28, 2010 4:08 PM
> >To: Jiang, Yunhong
> >Cc: Frank.Vanderlinden@xxxxxxx; xen-devel@xxxxxxxxxxxxxxxxxxx; Keir
> > Fraser; Jan Beulich
> >Subject: [Xen-devel] Re: [PATCH 1/6] MCE: Handle the vMCA bank correctly
> >
> >On Thursday 28 January 2010 06:55:50 Jiang, Yunhong wrote:
> >> Handle the vMCA bank correctly
> >>
> >> Currently the virtual MCE MSR assume all MSRs range from 0 to
> >> MAX_NR_BANKS are always MCE MSR, this is not always correct.
> >
> >Please explain, why is this not ? Which MSR is reported that is not an MCE
> >MSR ?
> >
> >Christoph
> >
> >> With this patch, the
> >> mce_rdmsr/mce_wrmsr will only handle vMCE MSR range from 0 to the MCA
> >
> >banks
> >
> >> in the host platform. Please notice that some MSR beyond current MCA
> >> banks in the host platform are really MCA MSRs, that should be handled
> >> by general MSR handler.
> >>
> >> Signed-off-by: Jiang, Yunhong <yunhong.jiang@xxxxxxxxx>
> >>
> >> diff -r 221c9b796e32 xen/arch/x86/cpu/mcheck/mce.c
> >> --- a/xen/arch/x86/cpu/mcheck/mce.c Tue Jan 26 00:33:03 2010 +0800
> >> +++ b/xen/arch/x86/cpu/mcheck/mce.c Tue Jan 26 00:52:04 2010 +0800
> >> @@ -716,8 +716,8 @@ int mce_rdmsr(uint32_t msr, uint64_t *va
> >> bank = (msr - MSR_IA32_MC0_CTL) / 4;
> >> if ( bank >= (d->arch.vmca_msrs.mcg_cap & MCG_CAP_COUNT) )
> >> {
> >> - mce_printk(MCE_QUIET, "MCE: bank %u does not exist\n",
> >> bank); - ret = -1;
> >> + mce_printk(MCE_QUIET, "MCE: MSR %x is not MCA MSR\n", msr);
> >> + ret = 0;
> >> break;
> >> }
> >> switch (msr & (MSR_IA32_MC0_CTL | 3))
> >> @@ -848,8 +848,8 @@ int mce_wrmsr(u32 msr, u64 val)
> >> bank = (msr - MSR_IA32_MC0_CTL) / 4;
> >> if ( bank >= (d->arch.vmca_msrs.mcg_cap & MCG_CAP_COUNT) )
> >> {
> >> - mce_printk(MCE_QUIET, "MCE: bank %u does not exist\n",
> >> bank); - ret = -1;
> >> + mce_printk(MCE_QUIET, "MCE: MSR %x is not MCA MSR\n", msr);
> >> + ret = 0;
> >> break;
> >> }
> >> switch ( msr & (MSR_IA32_MC0_CTL | 3) )
> >
> >
> >
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