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[Xen-devel] [PATCH] Enable TSC_RELIABLE for AMD servers

To: "Xen-Devel (E-mail)" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: [Xen-devel] [PATCH] Enable TSC_RELIABLE for AMD servers
From: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>
Date: Tue, 20 Oct 2009 08:05:25 -0700 (PDT)
Cc: mark.langsdorf@xxxxxxx, Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
Delivery-date: Tue, 20 Oct 2009 08:07:39 -0700
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(Mark, please ack)

Enable TSC_RELIABLE for AMD servers

Except for a published BIOS errata on family 11h processors,
all AMD servers that have the Invariant TSC bit set have
a reliable TSC so Xen should not write to the TSC.

Signed-off-by: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>


diff -r d7d7f978d704 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/arch/x86/cpu/amd.c    Tue Oct 20 08:55:53 2009 -0600
@@ -465,6 +465,8 @@ static void __devinit init_amd(struct cp
                if (c->x86_power & (1<<8)) {
                        set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
                        set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+                       if (c->x86 != 0x11)
+                               set_bit(X86_FEATURE_TSC_RELIABLE, 
c->x86_capability);
                }
        }

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