Jan Beulich <mailto:jbeulich@xxxxxxxxxx> wrote:
> I am observing some odd boot behavior resulting from the changes done
> in this c/s. In particular am I seeing banks being initialized
> inconsistently on my dual quad-core system:
> - after a cold boot, CPU0 has all its MCi_CTL non-zero (apparently BIOS-
> initialized), while CPUs 1, 4, and 5 have MC1_CTL non-zero
> but the others
> zero, and the remaining CPUs have MC1_CTL and MC3_CTL non-zero
> (MC3 presumably is non-zero here indeed because of it being shared
> across two of the four cores)
> - after a warm boot, all of the CPUs have all their MCi_CTL registers except
> for MC3_CTL non-zero, so only bank 3 actually gets initialized (and
> reported - again not for CPUs 0, 2, 3, 6, and 7).
>
> I'm pretty certain that there should neither be a difference
> between cold
> and warm boot here,
> nor should CPU0's BIOS settings (and any
> other CPUs'
> if the BIOS cares to touch them) survive (specifically also resulting in
We thought it is ok because according to IA32 SDM , software can only write all
0 or 1 to the MCi_CTL register, and then it will be ok either BIOS or OS to
setup the value, and there will be no difference for cold/warm boot situation.
(Or maybe buggy BIOS will not working like this way? )
But seems this feature is only for P6 family, we will change that code to
consider other situation.
> MCi_STATUS not being cleared). The old code simply wrote all
The MCi_STATUS will be cleared in machine_check_poll() if it is valid (maybe we
can always clear it).
> ones and all zeros
> respectively to MCi_CTL and MCi_STATUS without checking their original
In system with CMCI, we can't simply clear MCi_STATUS, considering when CPU
offline/online situation and especially the CMCI ownership requirement.
> values.
>
> Jan
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