RE: [Xen-devel] [PATCH] Improve the current FLR logic

["Cui, Dexuan" <dexuan.cui@xxxxxxxxx>]

Thanks for the comments!
Yes, the current simple save/restore has issues, and you have pointed some.
Let me think over all the issues and work out a better solution.

Thanks,
-- Dexuan


-----Original Message-----
From: Yuji Shimada [mailto:shimada-yxb@xxxxxxxxxxxxxxx] 
Sent: 2008年7月17日 17:34
To: Cui, Dexuan; Keir Fraser; xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: Re: [Xen-devel] [PATCH] Improve the current FLR logic

On Sat, 12 Jul 2008 20:37:34 +0800
"Cui, Dexuan" <dexuan.cui@xxxxxxxxx> wrote:

> I'd like to ask for your comments, and test feedbacks. Thank you very
> much!

There is a problem with the device reconfiguring logic. xend saves all
Configuration Register's values before reset. And xend writes the
values to the registers after reset. This means the resister's values
which are configured by guest software are restore. Guest software
setting should be cleared.

I think the following Configuration Resister should be reconfigured to
correct values after reset. And other registers should not be
reconfigured after reset if there is no reason.

- It is necessary to write the base address of the resource allocated
  by the dom0 kernel to the following resister.
    - Base Address Register

- When dom0 starts, the values configured by firmware should be saved,
  and the values should be written to the following resisters after
  reset. The reason is that firmware configures them to archive system
  specific functions. Especially, the registers relating error reporting
  are configured to collect error information. If this configured values
  is changed, some functions might be lost.
  Instead of save/restore, it is good way to write the value from _HPX
  method to registers, I think. _HPX method returns the value to write
  to registers.
    - Cache-line size Register
    - Latency timer Register
    - Enable SERR Bit/Enable PERR Bit in Device Control Register
    - Uncorrectable Error Mask Register
    - Uncorrectable Error Severity Register
    - Correctable Error Mask Register
    - Advanced Error Capabilities and Control Register
    - Device Control Register
    - Link Control Register
    - Secondary Uncorrectable Error Severity Register
    - Secondary Uncorrectable Error Mask Register
    - Device Control 2 Register
    - Link Control 2 Register

- The following resister should be configured to "0".
    - PME Enable Bit/PME Status Bit in PCI Power Management
      Control/Status Register

I would like to discuss this logic more.

Thanks.

--
Yuji Shimada


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