WARNING - OLD ARCHIVES

This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
   
 
 
Xen 
 
Home Products Support Community News
 
   
 

xen-devel

[Xen-devel] [PATCH] Stop clobbering AMD TSC offsets

To: xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-devel] [PATCH] Stop clobbering AMD TSC offsets
From: Ben Guthro <bguthro@xxxxxxxxxxxxxxx>
Date: Thu, 12 Jul 2007 16:50:46 -0400
Delivery-date: Thu, 12 Jul 2007 13:49:39 -0700
Envelope-to: www-data@xxxxxxxxxxxxxxxxxx
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
User-agent: Thunderbird 2.0.0.4 (X11/20070615)
This fixes a bug in which HVM VCPUs running on AMD have their TSC
offset clobbered (to zero) when they switch to real mode.  The
consequences of this are nearly unnoticeable in most cases, but the
AMD folks (Tom Woller & Travis Betak) agree this is a (minor) bug and
have been waiting forever for me to port and post this so they can
strike it off their TODO lists.

Signed-off-by: David Lively <dlively@xxxxxxxxxxxxxxx>
Signed-off-by: Ben Guthro <bguthro@xxxxxxxxxxxxxxx>

diff -r c03c4be32469 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c        Thu Jul 12 14:31:51 2007 -0400
+++ b/xen/arch/x86/hvm/svm/svm.c        Thu Jul 12 14:31:51 2007 -0400
@@ -2329,9 +2329,6 @@ static int svm_reset_to_realmode(struct 
     /* clear the vmcb and user regs */
     memset(regs, 0, sizeof(struct cpu_user_regs));
    
-    /* VMCB Control */
-    vmcb->tsc_offset = 0;
-
     /* VMCB State */
     vmcb->cr0 = X86_CR0_ET | X86_CR0_PG | X86_CR0_WP;
     v->arch.hvm_svm.cpu_shadow_cr0 = X86_CR0_ET;
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel
<Prev in Thread] Current Thread [Next in Thread>
  • [Xen-devel] [PATCH] Stop clobbering AMD TSC offsets, Ben Guthro <=