Re: [Xen-devel] [RFC] x86: cacheability page attributes

["Jan Beulich" <jbeulich@xxxxxxxxxx>]

>>> Keir Fraser <Keir.Fraser@xxxxxxxxxxxx> 04.04.07 09:16 >>>
>On 3/4/07 15:00, "Jan Beulich" <jbeulich@xxxxxxxxxx> wrote:
>
>> Attached draft patch is supposed to help dealing with tracking cacheability
>> attributes on x86, specifically to prevent page aliases using different
>> cacheability attributes.
>
>How important is this to get right? The Intel manual warns a bit vaguely
>about it, but I get the impression that nothing actually breaks in terms of
>cache coherency if a page is mapped with more than one PAT attribute (very
>much unlike the situation if CPUs have differing MTRR attributes!). The
>manual explains that even if a UC attribute is chosen, for example, the
>processor's cache will continue to snoop for accesses/updates of that line.

Since use of _PAGE_PCD alone (which is what PAGE_KERNEL_NOCACHE maps to)
translates to UC-, this is important, as with the MTRRs for such a region
being set to WC the effective memory type is WC, and a WC/WB conflict is
what the Intel manual specifically mentions must be avoided.

Jan

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