>Okay, I see. Well, that makes sense but I think we should have two
>each control word -- the bits we would like to set, and the bits we
>able to set. Also your previous patch added an unnecessary AND
>with 'msr_hi XOR msr_lo'.
No, it's necessary. According to Intel Spec:
If the bit in msr_lo is 1, then the control bit written to VMCS must be
If the bit in msr_hi is 0, then the control bit written to VMCS must be
The msr_lo and msr_hi combinations are:
1) L = 0 and H = 0: the adjusted control bit is 0, no matter what's the
input control value, that's why we need AND msr_hi.
2) L = 0 and H = 1: the adjusted control bit can be 0 or 1, depends on
if we support it.
3) L = 1 and H = 0: INVALID combination!!!
4) L = 1 and H = 1: the adjusted control bit is 1, no matter what's the
input control value, that's why we need OR msr_lo.
Specially for case 2,
if we have the feature support in Xen, we should set the input control
bit, and expect the adjusted value to be 1;
if we don't have the feature support in Xen, we should clear the input
control bit, and expect adjusted value to be 0;
That's meaning the adjusted output is determined by the input control.
So the expression should be "AND (msr_hi XOR msr_lo)".
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