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xen-devel
Re: [Xen-devel] how can native driver response quickly for low FIFO devi
On 25 May 2006, at 14:53, Dong, Eddie wrote:
There's a 128-byte receive buffer. Bytes are greedily taken from the
UART FIFO in interrupt context and written to the software receive
buffer. If overflow were a problem we could obviously quite easily
make that receive buffer substantially larger.
But this need the participate of processor in dom0. If the physical
processor is running for domU, and domU is waiting for its time slice
(descheduled), how can the bytes be taken to software receive buffer?
The bytes are taken from the UART in interrupt context inside Xen. Data
will only build up inside the UART FIFO if interrupts are disabled for
long periods.
-- Keir
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