Re: [Xen-devel] HT Vulnerability CAN-2005-0109

> All that being said, future processors are moving from HT to multicore. The
> problem then migrates to the L2 cache, where coloring is much less
> effective. It is unlikely that there exists any satisfsactory solution
> short of flushing or disabling the cache, neither of which is pragmatically
> viable.

But the bandwidth for L2 cache channel using this technique will also be lower 
than for the L1.  Additionally, I think the dual core CPUs coming from AMD 
and Intel don't actually share any cache (yet), unlike the dual-core POWER 
products from IBM.

Cheers,
Mark

>
> Current high assurance requirements don't require that you solve  the
> channel problem. They require that you characterize them and make a
> reasonable efffort to minimize them.
>
> Shap
>
>
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