# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1275030894 -3600
# Node ID b74af3abf72d2ac86ae271f4169929f22674a7bb
# Parent d86065bbb312cdf180a78ddecc7da18659ef6570
HAP: Add hardware capability check for 2MB super page.
While setting the HAP entry previously, we only check the hardware
capability for 1GB super page. This patch adds hardware capability
check for 2MB superpage
Also, Intel SDM doesn't exclude 1GB feature for 32/pae
host. Therefore remove the BUG_ON() check in common code.
Signed-off-by: Dongxiao Xu <dongxiao.xu@xxxxxxxxx>
---
xen/arch/x86/hvm/svm/svm.c | 5 +++--
xen/arch/x86/hvm/vmx/vmcs.c | 3 ++-
xen/arch/x86/hvm/vmx/vmx.c | 2 +-
xen/arch/x86/mm/p2m.c | 12 ++++--------
xen/include/asm-x86/hvm/hvm.h | 7 +++++--
5 files changed, 15 insertions(+), 14 deletions(-)
diff -r d86065bbb312 -r b74af3abf72d xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c Fri May 28 08:12:15 2010 +0100
+++ b/xen/arch/x86/hvm/svm/svm.c Fri May 28 08:14:54 2010 +0100
@@ -935,8 +935,9 @@ struct hvm_function_table * __init start
cpuid_edx(0x8000000A) : 0);
svm_function_table.hap_supported = cpu_has_svm_npt;
- svm_function_table.hap_1gb_pgtb =
- (CONFIG_PAGING_LEVELS == 4)? !!(cpuid_edx(0x80000001) & 0x04000000):0;
+ svm_function_table.hap_superpage_level =
+ ((CONFIG_PAGING_LEVELS == 4) && (cpuid_edx(0x80000001) & 0x04000000)) ?
+ 2 : 1;
return &svm_function_table;
}
diff -r d86065bbb312 -r b74af3abf72d xen/arch/x86/hvm/vmx/vmcs.c
--- a/xen/arch/x86/hvm/vmx/vmcs.c Fri May 28 08:12:15 2010 +0100
+++ b/xen/arch/x86/hvm/vmx/vmcs.c Fri May 28 08:14:54 2010 +0100
@@ -94,7 +94,8 @@ static void __init vmx_display_features(
if ( vmx_ept_super_page_level_limit )
printk("EPT supports %s super page.\n",
- vmx_ept_super_page_level_limit > 1 ? "1G" : "2M");
+ (vmx_ept_super_page_level_limit == 2) ? "1G" :
+ ((vmx_ept_super_page_level_limit == 1) ? "2M" : "4K"));
}
static u32 adjust_vmx_controls(
diff -r d86065bbb312 -r b74af3abf72d xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c Fri May 28 08:12:15 2010 +0100
+++ b/xen/arch/x86/hvm/vmx/vmx.c Fri May 28 08:14:54 2010 +0100
@@ -1435,7 +1435,7 @@ struct hvm_function_table * __init start
setup_ept_dump();
}
- vmx_function_table.hap_1gb_pgtb = (vmx_ept_super_page_level_limit == 2);
+ vmx_function_table.hap_superpage_level = vmx_ept_super_page_level_limit;
setup_vmcs_dump();
diff -r d86065bbb312 -r b74af3abf72d xen/arch/x86/mm/p2m.c
--- a/xen/arch/x86/mm/p2m.c Fri May 28 08:12:15 2010 +0100
+++ b/xen/arch/x86/mm/p2m.c Fri May 28 08:14:54 2010 +0100
@@ -1757,16 +1757,12 @@ int set_p2m_entry(struct domain *d, unsi
{
if ( is_hvm_domain(d) && paging_mode_hap(d) )
order = ( (((gfn | mfn_x(mfn) | todo) & ((1ul << 18) - 1)) == 0) &&
- hvm_funcs.hap_1gb_pgtb && opt_hap_1gb ) ? 18 :
- (((gfn | mfn_x(mfn) | todo) & ((1ul << 9) - 1)) == 0) ? 9 : 0;
+ (hvm_funcs.hap_superpage_level == 2) &&
+ opt_hap_1gb ) ? 18 :
+ ((((gfn | mfn_x(mfn) | todo) & ((1ul << 9) - 1)) == 0) &&
+ (hvm_funcs.hap_superpage_level >= 1)) ? 9 : 0;
else
order = 0;
-
- /* Note that we only enable hap_1gb_pgtb when CONFIG_PAGING_LEVELS==4.
- * So 1GB should never be enabled under 32bit or PAE modes. But for
- * safety's reason, we double-check the page order again..
- */
- BUG_ON(order == 18 && CONFIG_PAGING_LEVELS < 4);
if ( !d->arch.p2m->set_entry(d, gfn, mfn, order, p2mt) )
rc = 0;
diff -r d86065bbb312 -r b74af3abf72d xen/include/asm-x86/hvm/hvm.h
--- a/xen/include/asm-x86/hvm/hvm.h Fri May 28 08:12:15 2010 +0100
+++ b/xen/include/asm-x86/hvm/hvm.h Fri May 28 08:14:54 2010 +0100
@@ -72,8 +72,11 @@ struct hvm_function_table {
/* Support Hardware-Assisted Paging? */
int hap_supported;
- /* Support 1GB Harware-Assisted Paging? */
- int hap_1gb_pgtb;
+ /*
+ * Indicate HAP super page level.
+ * 0 -- 4KB, 1 -- 2MB, 2 -- 1GB.
+ */
+ int hap_superpage_level;
/*
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