WARNING - OLD ARCHIVES

This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
   
 
 
Xen 
 
Home Products Support Community News
 
   
 

xen-changelog

[Xen-changelog] [xen-unstable] Mask AMD CPUID masks in software before w

To: xen-changelog@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-changelog] [xen-unstable] Mask AMD CPUID masks in software before writing them to the MSRs
From: Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>
Date: Wed, 17 Feb 2010 04:20:14 -0800
Delivery-date: Wed, 17 Feb 2010 04:20:30 -0800
Envelope-to: www-data@xxxxxxxxxxxxxxxxxxx
List-help: <mailto:xen-changelog-request@lists.xensource.com?subject=help>
List-id: BK change log <xen-changelog.lists.xensource.com>
List-post: <mailto:xen-changelog@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/mailman/listinfo/xen-changelog>, <mailto:xen-changelog-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/mailman/listinfo/xen-changelog>, <mailto:xen-changelog-request@lists.xensource.com?subject=unsubscribe>
Reply-to: xen-devel@xxxxxxxxxxxxxxxxxxx
Sender: xen-changelog-bounces@xxxxxxxxxxxxxxxxxxx
# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1266408345 0
# Node ID 220e4996f0e86db89a19e5eba7a1d97c19625a58
# Parent  50ea24db1f88c57611e5c62f1378873c677c0d11
Mask AMD CPUID masks in software before writing them to the MSRs

Mask AMD CPUID masks in software before writing them to the MSRs.
Setting bits in the CPUID mask MSR that are not set in the unmasked
CPUID response can cause those bits to be set in the masked response.
Avoid that by explicitly masking in software.

Signed-off-by: Tim Deegan <Tim.Deegan@xxxxxxxxxx>
---
 xen/arch/x86/cpu/amd.c |    8 ++++++++
 1 files changed, 8 insertions(+)

diff -r 50ea24db1f88 -r 220e4996f0e8 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Wed Feb 17 12:04:50 2010 +0000
+++ b/xen/arch/x86/cpu/amd.c    Wed Feb 17 12:05:45 2010 +0000
@@ -130,6 +130,14 @@ static void __devinit set_cpuidmask(stru
                return;
        }
 
+        /* Setting bits in the CPUID mask MSR that are not set in the
+         * unmasked CPUID response can cause those bits to be set in the
+         * masked response.  Avoid that by explicitly masking in software. */
+        feat_ecx &= cpuid_ecx(0x00000001);
+        feat_edx &= cpuid_edx(0x00000001);
+        extfeat_ecx &= cpuid_ecx(0x80000001);
+        extfeat_edx &= cpuid_edx(0x80000001);
+
        status = set_mask;
        printk("Writing CPUID feature mask ECX:EDX -> %08Xh:%08Xh\n", 
               feat_ecx, feat_edx);

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog

<Prev in Thread] Current Thread [Next in Thread>
  • [Xen-changelog] [xen-unstable] Mask AMD CPUID masks in software before writing them to the MSRs, Xen patchbot-unstable <=