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[Xen-changelog] [xen-unstable] x86 mca: Handle the vMCA bank correctly

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Subject: [Xen-changelog] [xen-unstable] x86 mca: Handle the vMCA bank correctly
From: Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>
Date: Fri, 29 Jan 2010 01:05:12 -0800
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# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1264747644 0
# Node ID f85120520509095daa90ac622f404bedfede94b7
# Parent  b4244eff4384e69120b1695b44102f1276c7859d
x86 mca: Handle the vMCA bank correctly

Currently the virtual MCE MSR assume all MSRs range from 0 to
MAX_NR_BANKS are always MCE MSR, this is not always correct. With this
patch, the mce_rdmsr/mce_wrmsr will only handle vMCE MSR range from 0
to the MCA banks in the host platform.
Please notice that some MSR beyond current MCA banks in the host
platform are really MCA MSRs, that should be handled by general MSR
handler.

Signed-off-by: Jiang, Yunhong <yunhong.jiang@xxxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/mce.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff -r b4244eff4384 -r f85120520509 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c     Fri Jan 29 06:45:45 2010 +0000
+++ b/xen/arch/x86/cpu/mcheck/mce.c     Fri Jan 29 06:47:24 2010 +0000
@@ -716,8 +716,8 @@ int mce_rdmsr(uint32_t msr, uint64_t *va
         bank = (msr - MSR_IA32_MC0_CTL) / 4;
         if ( bank >= (d->arch.vmca_msrs.mcg_cap & MCG_CAP_COUNT) )
         {
-            mce_printk(MCE_QUIET, "MCE: bank %u does not exist\n", bank);
-            ret = -1;
+            mce_printk(MCE_QUIET, "MCE: MSR %x is not MCA MSR\n", msr);
+            ret = 0;
             break;
         }
         switch (msr & (MSR_IA32_MC0_CTL | 3))
@@ -848,8 +848,8 @@ int mce_wrmsr(u32 msr, u64 val)
         bank = (msr - MSR_IA32_MC0_CTL) / 4;
         if ( bank >= (d->arch.vmca_msrs.mcg_cap & MCG_CAP_COUNT) )
         {
-            mce_printk(MCE_QUIET, "MCE: bank %u does not exist\n", bank);
-            ret = -1;
+            mce_printk(MCE_QUIET, "MCE: MSR %x is not MCA MSR\n", msr);
+            ret = 0;
             break;
         }
         switch ( msr & (MSR_IA32_MC0_CTL | 3) )

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