[Xen-changelog] [xen-unstable] AMD IOMMU: Remove unused definitions.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1253258959 -3600
# Node ID 0f05e956957d2e02d4a9de93a54b7777aef95fe2
# Parent  1d503a3e65a0ec513ecebb8481cc44d21642ffe4
AMD IOMMU: Remove unused definitions.

Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
---
 xen/include/asm-x86/amd-iommu.h              |    3 -
 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h |   46 ---------------------------
 2 files changed, 49 deletions(-)

diff -r 1d503a3e65a0 -r 0f05e956957d xen/include/asm-x86/amd-iommu.h
--- a/xen/include/asm-x86/amd-iommu.h   Fri Sep 18 08:28:52 2009 +0100
+++ b/xen/include/asm-x86/amd-iommu.h   Fri Sep 18 08:29:19 2009 +0100
@@ -58,9 +58,6 @@ struct amd_iommu {
     u8 pass_pw;
     u8 ht_tunnel_enable;
 
-    int last_downstream_bus;
-    int downstream_bus_present[PCI_MAX_BUS_COUNT];
-
     void *mmio_base;
     unsigned long mmio_base_phys;
 
diff -r 1d503a3e65a0 -r 0f05e956957d 
xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h      Fri Sep 18 08:28:52 
2009 +0100
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h      Fri Sep 18 08:29:19 
2009 +0100
@@ -21,14 +21,6 @@
 #ifndef _ASM_X86_64_AMD_IOMMU_DEFS_H
 #define _ASM_X86_64_AMD_IOMMU_DEFS_H
 
-/* Reserve some non-mapped pages to handle error conditions.
- * 'bad_dma_address' will point to these reserved pages, and
- * the mapping funtions will return 'bad_dma_address' if there
- * are not enough page table entries available.
- */
-#define IOMMU_RESERVED_BASE_ADDR       0
-#define IOMMU_RESERVED_PAGES           32
-
 /* IOMMU ComWaitInt polling after issuing a COMPLETION_WAIT command */
 #define COMPLETION_WAIT_DEFAULT_POLLING_COUNT  10
 
@@ -37,8 +29,6 @@
 
 /* IOMMU Event Log entries: in power of 2 increments, minimum of 256 */
 #define IOMMU_EVENT_LOG_DEFAULT_ENTRIES     512
-
-#define BITMAP_ENTRIES_PER_BYTE                8
 
 #define PTE_PER_TABLE_SHIFT            9
 #define PTE_PER_TABLE_SIZE             (1 << PTE_PER_TABLE_SHIFT)
@@ -48,41 +38,6 @@
 #define PTE_PER_TABLE_ALLOC(entries)   \
        PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT)
 
-/* 0-based aperture order (represents virtual address space for DMA mappings */
-#define APERTURE_ORDER_FOR_32B_APERTURE                0
-#define APERTURE_ORDER_FOR_64MB_APERTURE       1
-#define APERTURE_ORDER_FOR_128MB_APERTURE      2
-#define APERTURE_ORDER_FOR_256MB_APERTURE      3
-#define APERTURE_ORDER_FOR_512MB_APERTURE      4
-#define APERTURE_ORDER_FOR_1GB_APERTURE                5
-#define APERTURE_ORDER_FOR_MAX_APERTURE                
APERTURE_ORDER_FOR_1GB_APERTURE
-
-/* The minimum 32MB aperture requires 2**13 level-1 page table entries */
-#define SHIFT_FOR_MIN_APERTURE         13
-#define PAGES_FROM_APERTURE_ORDER(order)       \
-       ((1 << (order)) << SHIFT_FOR_MIN_APERTURE)
-#define ORDER_FROM_APERTURE_PAGES(pages)       \
-       get_order(((pages) * PAGE_SIZE) >> SHIFT_FOR_MIN_APERTURE)
-
-/*
- * PCI config-space
- */
-#define VALID_PCI_VENDOR_ID(id)                (((id) != 0) && ((id) != 
0xFFFF))
-#define IS_PCI_MULTI_FUNCTION(hdr)     ((hdr) & 0x80)
-#define IS_PCI_TYPE0_HEADER(hdr)       (((hdr) & 0x7f) == 0)
-#define IS_PCI_TYPE1_HEADER(hdr)       (((hdr) & 0x7f) == 1)
-
-#define PCI_MAX_BUS_COUNT      256
-#define PCI_MAX_DEV_COUNT      32
-#define PCI_MAX_FUNC_COUNT     8
-#define PCI_MIN_DEVFN          0
-#define PCI_MAX_DEVFN          0xFF
-
-/*
- * Capability blocks are 4-byte aligned, and must start at >= offset 0x40,
- * for a max of 48 possible cap_blocks (256 - 0x40 = 192; 192 / 4 = 48)
- * The lower 2 bits of each pointer are reserved, and must be masked off.
- */
 #define PCI_MIN_CAP_OFFSET     0x40
 #define PCI_MAX_CAP_BLOCKS     48
 #define PCI_CAP_PTR_MASK       0xFC
@@ -105,7 +60,6 @@
 #define PCI_CAP_RESET_MASK     0x80000000
 #define PCI_CAP_RESET_SHIFT    31
 
-#define PCI_CAP_ID_SECURE_DEVICE       0x0F
 #define PCI_CAP_TYPE_IOMMU             0x3
 
 #define PCI_CAP_MMIO_BAR_LOW_OFFSET    0x04

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