# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1239970441 -3600
# Node ID b44db970f6b7fe9ff2945e5ed4c2a3bf34487f12
# Parent 150662e5adfc9a8f95329f037432d76a92247aae
cpuidle: Add support for Always Running APIC timer, CPUID_0x6_EAX_Bit2.
This bit means the APIC timer continues to run even when CPU is
in deep C-states.
The advantage is that we can use LAPIC timer on these CPUs
always, and there is no need for "slow to read and program"
external timers (HPET/PIT) and the timer broadcast logic
and related code in C-state entry and exit.
Refer to the latest Intel SDM Vol 2A
(http://www.intel.com/products/processor/manuals/index.htm)
Signed-off-by: Wei Gang <gang.wei@xxxxxxxxx>
---
xen/arch/x86/acpi/cpu_idle.c | 9 +++++++--
xen/arch/x86/cpu/intel.c | 3 +++
xen/arch/x86/time.c | 2 +-
xen/include/asm-x86/cpufeature.h | 1 +
4 files changed, 12 insertions(+), 3 deletions(-)
diff -r 150662e5adfc -r b44db970f6b7 xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c Fri Apr 17 13:07:06 2009 +0100
+++ b/xen/arch/x86/acpi/cpu_idle.c Fri Apr 17 13:14:01 2009 +0100
@@ -51,6 +51,7 @@
/*#define DEBUG_PM_CX*/
+static void lapic_timer_nop(void) { }
static void (*lapic_timer_off)(void);
static void (*lapic_timer_on)(void);
@@ -538,8 +539,12 @@ static int check_cx(struct acpi_processo
if ( local_apic_timer_c2_ok )
break;
case ACPI_STATE_C3:
- /* We must be able to use HPET in place of LAPIC timers. */
- if ( hpet_broadcast_is_available() )
+ if ( boot_cpu_has(X86_FEATURE_ARAT) )
+ {
+ lapic_timer_off = lapic_timer_nop;
+ lapic_timer_on = lapic_timer_nop;
+ }
+ else if ( hpet_broadcast_is_available() )
{
lapic_timer_off = hpet_broadcast_enter;
lapic_timer_on = hpet_broadcast_exit;
diff -r 150662e5adfc -r b44db970f6b7 xen/arch/x86/cpu/intel.c
--- a/xen/arch/x86/cpu/intel.c Fri Apr 17 13:07:06 2009 +0100
+++ b/xen/arch/x86/cpu/intel.c Fri Apr 17 13:14:01 2009 +0100
@@ -222,6 +222,9 @@ static void __devinit init_intel(struct
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
set_bit(X86_FEATURE_NOSTOP_TSC, c->x86_capability);
}
+ if ((c->cpuid_level >= 0x00000006) &&
+ (cpuid_eax(0x00000006) & (1u<<2)))
+ set_bit(X86_FEATURE_ARAT, c->x86_capability);
start_vmx();
}
diff -r 150662e5adfc -r b44db970f6b7 xen/arch/x86/time.c
--- a/xen/arch/x86/time.c Fri Apr 17 13:07:06 2009 +0100
+++ b/xen/arch/x86/time.c Fri Apr 17 13:14:01 2009 +0100
@@ -1274,7 +1274,7 @@ static int disable_pit_irq(void)
* XXX dom0 may rely on RTC interrupt delivery, so only enable
* hpet_broadcast if FSB mode available or if force_hpet_broadcast.
*/
- if ( xen_cpuidle )
+ if ( xen_cpuidle && !boot_cpu_has(X86_FEATURE_ARAT) )
{
hpet_broadcast_init();
if ( !hpet_broadcast_is_available() )
diff -r 150662e5adfc -r b44db970f6b7 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Fri Apr 17 13:07:06 2009 +0100
+++ b/xen/include/asm-x86/cpufeature.h Fri Apr 17 13:14:01 2009 +0100
@@ -75,6 +75,7 @@
#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_NOSTOP_TSC (3*32+ 9) /* TSC does not stop in C states */
+#define X86_FEATURE_ARAT (3*32+ 10) /* Always running APIC timer */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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