# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1239021971 -3600
# Node ID 1a7457bb1fdf3ca09840d5762cb77416eda5bd84
# Parent 5a60eb7fad79294ca1b9e74f8da1ea1d165d3199
x86 mce: Small fix for polling/CMCI race conditions.
When CMCI happens very quickly, polling/CMCI processing path might
cross. For Intel CPUs which support CMCI, if the error bank has CMCI
capability, we'll disable poll on this bank.
Signed-off-by: Liping Ke <liping.ke@xxxxxxxxx>
Signed-off-by: Yunhong Jiang<yunhong.jiang@xxxxxxxxx>
---
xen/arch/x86/cpu/mcheck/mce.c | 15 ++++++++++++++-
xen/arch/x86/cpu/mcheck/mce.h | 4 ++++
xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ++--
xen/arch/x86/cpu/mcheck/non-fatal.c | 8 ++------
4 files changed, 22 insertions(+), 9 deletions(-)
diff -r 5a60eb7fad79 -r 1a7457bb1fdf xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c Thu Apr 02 14:17:19 2009 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.c Mon Apr 06 13:46:11 2009 +0100
@@ -577,6 +577,7 @@ void mcheck_init(struct cpuinfo_x86 *c)
break;
}
+ set_poll_bankmask(c);
if (!inited)
printk(XENLOG_INFO "CPU%i: No machine check initialization\n",
smp_processor_id());
@@ -1230,7 +1231,19 @@ long do_mca(XEN_GUEST_HANDLE(xen_mc_t) u
return ret;
}
-
+void set_poll_bankmask(struct cpuinfo_x86 *c)
+{
+
+ if (cmci_support && !mce_disabled) {
+ memcpy(&(__get_cpu_var(poll_bankmask)),
+ &(__get_cpu_var(no_cmci_banks)), sizeof(cpu_banks_t));
+ }
+ else {
+ memcpy(&(get_cpu_var(poll_bankmask)), &mca_allbanks,
sizeof(cpu_banks_t));
+ if (mce_firstbank(c))
+ clear_bit(0, get_cpu_var(poll_bankmask));
+ }
+}
void mc_panic(char *s)
{
console_start_sync();
diff -r 5a60eb7fad79 -r 1a7457bb1fdf xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h Thu Apr 02 14:17:19 2009 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.h Mon Apr 06 13:46:11 2009 +0100
@@ -88,6 +88,10 @@ struct mca_summary {
};
extern cpu_banks_t mca_allbanks;
+void set_poll_bankmask(struct cpuinfo_x86 *c);
+DECLARE_PER_CPU(cpu_banks_t, poll_bankmask);
+DECLARE_PER_CPU(cpu_banks_t, no_cmci_banks);
+extern int cmci_support;
extern mctelem_cookie_t mcheck_mca_logout(enum mca_source, cpu_banks_t,
struct mca_summary *);
diff -r 5a60eb7fad79 -r 1a7457bb1fdf xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c Thu Apr 02 14:17:19 2009 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c Mon Apr 06 13:46:11 2009 +0100
@@ -12,9 +12,10 @@
#include "x86_mca.h"
DEFINE_PER_CPU(cpu_banks_t, mce_banks_owned);
+DEFINE_PER_CPU(cpu_banks_t, no_cmci_banks);
+int cmci_support = 0;
static int nr_intel_ext_msrs = 0;
-static int cmci_support = 0;
static int firstbank;
#ifdef CONFIG_X86_MCE_THERMAL
@@ -548,7 +549,6 @@ static void intel_machine_check(struct c
}
static DEFINE_SPINLOCK(cmci_discover_lock);
-static DEFINE_PER_CPU(cpu_banks_t, no_cmci_banks);
/*
* Discover bank sharing using the algorithm recommended in the SDM.
diff -r 5a60eb7fad79 -r 1a7457bb1fdf xen/arch/x86/cpu/mcheck/non-fatal.c
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c Thu Apr 02 14:17:19 2009 +0100
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c Mon Apr 06 13:46:11 2009 +0100
@@ -22,7 +22,7 @@
#include "mce.h"
-static cpu_banks_t bankmask;
+DEFINE_PER_CPU(cpu_banks_t, poll_bankmask);
static struct timer mce_timer;
#define MCE_PERIOD MILLISECS(8000)
@@ -39,7 +39,7 @@ static void mce_checkregs (void *info)
struct mca_summary bs;
static uint64_t dumpcount = 0;
- mctc = mcheck_mca_logout(MCA_POLLER, bankmask, &bs);
+ mctc = mcheck_mca_logout(MCA_POLLER, __get_cpu_var(poll_bankmask), &bs);
if (bs.errcnt && mctc != NULL) {
adjust++;
@@ -94,10 +94,6 @@ static int __init init_nonfatal_mce_chec
if (!mce_available(c))
return -ENODEV;
- memcpy(&bankmask, &mca_allbanks, sizeof (cpu_banks_t));
- if (mce_firstbank(c) == 1)
- clear_bit(0, bankmask);
-
/*
* Check for non-fatal errors every MCE_RATE s
*/
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