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[Xen-changelog] [linux-2.6.18-xen] Add the e1000e driver for dom0

To: xen-changelog@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-changelog] [linux-2.6.18-xen] Add the e1000e driver for dom0
From: "Xen patchbot-linux-2.6.18-xen" <patchbot-linux-2.6.18-xen@xxxxxxxxxxxxxxxxxxx>
Date: Tue, 17 Feb 2009 09:05:05 -0800
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# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1234869922 0
# Node ID 2ee6febdd4f96ce25c7b493c6d403b9652c34854
# Parent  be85b1d7a52b624a66f23e7e221a6017b51e001b
Add the e1000e driver for dom0

backport the driver from RHEL5.3 and make it work.

signed-off-by: Zhang Yang <yang.zhang@xxxxxxxxx>
---
 arch/i386/defconfig               |    1 
 arch/ia64/defconfig               |    1 
 arch/x86_64/defconfig             |    1 
 drivers/net/Kconfig               |   23 
 drivers/net/Makefile              |    1 
 drivers/net/e1000e/82571.c        | 1510 +++++++++++
 drivers/net/e1000e/Makefile       |   37 
 drivers/net/e1000e/defines.h      |  784 +++++
 drivers/net/e1000e/e1000.h        |  567 ++++
 drivers/net/e1000e/e1000_compat.h |   69 
 drivers/net/e1000e/es2lan.c       | 1310 +++++++++
 drivers/net/e1000e/ethtool.c      | 1949 ++++++++++++++
 drivers/net/e1000e/hw.h           |  903 ++++++
 drivers/net/e1000e/ich8lan.c      | 2568 ++++++++++++++++++
 drivers/net/e1000e/lib.c          | 2501 ++++++++++++++++++
 drivers/net/e1000e/netdev.c       | 5193 ++++++++++++++++++++++++++++++++++++++
 drivers/net/e1000e/param.c        |  448 +++
 drivers/net/e1000e/phy.c          | 2291 ++++++++++++++++
 18 files changed, 20157 insertions(+)

diff -r be85b1d7a52b -r 2ee6febdd4f9 arch/i386/defconfig
--- a/arch/i386/defconfig       Tue Feb 17 11:17:11 2009 +0000
+++ b/arch/i386/defconfig       Tue Feb 17 11:25:22 2009 +0000
@@ -681,6 +681,7 @@ CONFIG_E100=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 # CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
diff -r be85b1d7a52b -r 2ee6febdd4f9 arch/ia64/defconfig
--- a/arch/ia64/defconfig       Tue Feb 17 11:17:11 2009 +0000
+++ b/arch/ia64/defconfig       Tue Feb 17 11:25:22 2009 +0000
@@ -594,6 +594,7 @@ CONFIG_E100=m
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
+CONFIG_E1000E=y
 # CONFIG_E1000_NAPI is not set
 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
 # CONFIG_NS83820 is not set
diff -r be85b1d7a52b -r 2ee6febdd4f9 arch/x86_64/defconfig
--- a/arch/x86_64/defconfig     Tue Feb 17 11:17:11 2009 +0000
+++ b/arch/x86_64/defconfig     Tue Feb 17 11:25:22 2009 +0000
@@ -701,6 +701,7 @@ CONFIG_8139TOO=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
+CONFIG_E1000E=y
 # CONFIG_E1000_NAPI is not set
 # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
 # CONFIG_NS83820 is not set
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/Kconfig
--- a/drivers/net/Kconfig       Tue Feb 17 11:17:11 2009 +0000
+++ b/drivers/net/Kconfig       Tue Feb 17 11:25:22 2009 +0000
@@ -1959,6 +1959,29 @@ config E1000_DISABLE_PACKET_SPLIT
          hardware.
 
          If in doubt, say N.
+
+config E1000E
+       tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
+       depends on PCI
+       ---help---
+         This driver supports the PCI-Express Intel(R) PRO/1000 gigabit
+         ethernet family of adapters. For PCI or PCI-X e1000 adapters,
+         use the regular e1000 driver For more information on how to
+         identify your adapter, go to the Adapter & Driver ID Guide at:
+
+         <http://support.intel.com/support/network/adapter/pro100/21397.htm>
+
+         For general information and support, go to the Intel support
+         website at:
+
+         <http://support.intel.com>
+
+         More specific information on configuring the driver is in
+         <file:Documentation/networking/e1000e.txt>.
+
+         To compile this driver as a module, choose M here and read
+         <file:Documentation/networking/net-modules.txt>.  The module
+         will be called e1000e.
 
 source "drivers/net/ixp2000/Kconfig"
 
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/Makefile
--- a/drivers/net/Makefile      Tue Feb 17 11:17:11 2009 +0000
+++ b/drivers/net/Makefile      Tue Feb 17 11:25:22 2009 +0000
@@ -7,6 +7,7 @@ endif
 endif
 
 obj-$(CONFIG_E1000) += e1000/
+obj-$(CONFIG_E1000E) += e1000e/
 obj-$(CONFIG_IBM_EMAC) += ibm_emac/
 obj-$(CONFIG_IXGB) += ixgb/
 obj-$(CONFIG_IXGBE) += ixgbe/
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/82571.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/82571.c        Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,1510 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/*
+ * 82571EB Gigabit Ethernet Controller
+ * 82571EB Gigabit Ethernet Controller (Fiber)
+ * 82571EB Dual Port Gigabit Mezzanine Adapter
+ * 82571EB Quad Port Gigabit Mezzanine Adapter
+ * 82571PT Gigabit PT Quad Port Server ExpressModule
+ * 82572EI Gigabit Ethernet Controller (Copper)
+ * 82572EI Gigabit Ethernet Controller (Fiber)
+ * 82572EI Gigabit Ethernet Controller
+ * 82573V Gigabit Ethernet Controller (Copper)
+ * 82573E Gigabit Ethernet Controller (Copper)
+ * 82573L Gigabit Ethernet Controller
+ * 82574L Gigabit Network Connection
+ */
+
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include "e1000.h"
+
+#define ID_LED_RESERVED_F746 0xF746
+#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
+                             (ID_LED_OFF1_ON2  <<  8) | \
+                             (ID_LED_DEF1_DEF2 <<  4) | \
+                             (ID_LED_DEF1_DEF2))
+
+#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+
+#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask 
*/
+
+static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
+static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
+static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
+static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+                                     u16 words, u16 *data);
+static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
+static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
+static s32 e1000_setup_link_82571(struct e1000_hw *hw);
+static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
+static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
+static s32 e1000_led_on_82574(struct e1000_hw *hw);
+
+/**
+ *  e1000_init_phy_params_82571 - Init PHY func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+
+       if (hw->phy.media_type != e1000_media_type_copper) {
+               phy->type = e1000_phy_none;
+               return 0;
+       }
+
+       phy->addr                        = 1;
+       phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+       phy->reset_delay_us              = 100;
+
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               phy->type                = e1000_phy_igp_2;
+               break;
+       case e1000_82573:
+               phy->type                = e1000_phy_m88;
+               break;
+       case e1000_82574:
+               phy->type                = e1000_phy_bm;
+               break;
+       default:
+               return -E1000_ERR_PHY;
+               break;
+       }
+
+       /* This can only be done after all function pointers are setup. */
+       ret_val = e1000_get_phy_id_82571(hw);
+
+       /* Verify phy id */
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               if (phy->id != IGP01E1000_I_PHY_ID)
+                       return -E1000_ERR_PHY;
+               break;
+       case e1000_82573:
+               if (phy->id != M88E1111_I_PHY_ID)
+                       return -E1000_ERR_PHY;
+               break;
+       case e1000_82574:
+               if (phy->id != BME1000_E_PHY_ID_R2)
+                       return -E1000_ERR_PHY;
+               break;
+       default:
+               return -E1000_ERR_PHY;
+               break;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 eecd = er32(EECD);
+       u16 size;
+
+       nvm->opcode_bits = 8;
+       nvm->delay_usec = 1;
+       switch (nvm->override) {
+       case e1000_nvm_override_spi_large:
+               nvm->page_size = 32;
+               nvm->address_bits = 16;
+               break;
+       case e1000_nvm_override_spi_small:
+               nvm->page_size = 8;
+               nvm->address_bits = 8;
+               break;
+       default:
+               nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+               nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
+               break;
+       }
+
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+               if (((eecd >> 15) & 0x3) == 0x3) {
+                       nvm->type = e1000_nvm_flash_hw;
+                       nvm->word_size = 2048;
+                       /*
+                        * Autonomous Flash update bit must be cleared due
+                        * to Flash update issue.
+                        */
+                       eecd &= ~E1000_EECD_AUPDEN;
+                       ew32(EECD, eecd);
+                       break;
+               }
+               /* Fall Through */
+       default:
+               nvm->type = e1000_nvm_eeprom_spi;
+               size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
+                                 E1000_EECD_SIZE_EX_SHIFT);
+               /*
+                * Added to a constant, "size" becomes the left-shift value
+                * for setting word_size.
+                */
+               size += NVM_WORD_SIZE_BASE_SHIFT;
+
+               /* EEPROM access above 16k is unsupported */
+               if (size > 14)
+                       size = 14;
+               nvm->word_size  = 1 << size;
+               break;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_init_mac_params_82571 - Init MAC func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       struct e1000_mac_info *mac = &hw->mac;
+       struct e1000_mac_operations *func = &mac->ops;
+
+       /* Set media type */
+       switch (adapter->pdev->device) {
+       case E1000_DEV_ID_82571EB_FIBER:
+       case E1000_DEV_ID_82572EI_FIBER:
+       case E1000_DEV_ID_82571EB_QUAD_FIBER:
+               hw->phy.media_type = e1000_media_type_fiber;
+               break;
+       case E1000_DEV_ID_82571EB_SERDES:
+       case E1000_DEV_ID_82572EI_SERDES:
+       case E1000_DEV_ID_82571EB_SERDES_DUAL:
+       case E1000_DEV_ID_82571EB_SERDES_QUAD:
+               hw->phy.media_type = e1000_media_type_internal_serdes;
+               break;
+       default:
+               hw->phy.media_type = e1000_media_type_copper;
+               break;
+       }
+
+       /* Set mta register count */
+       mac->mta_reg_count = 128;
+       /* Set rar entry count */
+       mac->rar_entry_count = E1000_RAR_ENTRIES;
+       /* Set if manageability features are enabled. */
+       mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
+
+       /* check for link */
+       switch (hw->phy.media_type) {
+       case e1000_media_type_copper:
+               func->setup_physical_interface = e1000_setup_copper_link_82571;
+               func->check_for_link = e1000e_check_for_copper_link;
+               func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
+               break;
+       case e1000_media_type_fiber:
+               func->setup_physical_interface =
+                       e1000_setup_fiber_serdes_link_82571;
+               func->check_for_link = e1000e_check_for_fiber_link;
+               func->get_link_up_info =
+                       e1000e_get_speed_and_duplex_fiber_serdes;
+               break;
+       case e1000_media_type_internal_serdes:
+               func->setup_physical_interface =
+                       e1000_setup_fiber_serdes_link_82571;
+               func->check_for_link = e1000e_check_for_serdes_link;
+               func->get_link_up_info =
+                       e1000e_get_speed_and_duplex_fiber_serdes;
+               break;
+       default:
+               return -E1000_ERR_CONFIG;
+               break;
+       }
+
+       switch (hw->mac.type) {
+       case e1000_82574:
+               func->check_mng_mode = e1000_check_mng_mode_82574;
+               func->led_on = e1000_led_on_82574;
+               break;
+       default:
+               func->check_mng_mode = e1000e_check_mng_mode_generic;
+               func->led_on = e1000e_led_on_generic;
+               break;
+       }
+
+       return 0;
+}
+
+static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       static int global_quad_port_a; /* global port a indication */
+       struct pci_dev *pdev = adapter->pdev;
+       u16 eeprom_data = 0;
+       int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
+       s32 rc;
+
+       rc = e1000_init_mac_params_82571(adapter);
+       if (rc)
+               return rc;
+
+       rc = e1000_init_nvm_params_82571(hw);
+       if (rc)
+               return rc;
+
+       rc = e1000_init_phy_params_82571(hw);
+       if (rc)
+               return rc;
+
+       /* tag quad port adapters first, it's used below */
+       switch (pdev->device) {
+       case E1000_DEV_ID_82571EB_QUAD_COPPER:
+       case E1000_DEV_ID_82571EB_QUAD_FIBER:
+       case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
+       case E1000_DEV_ID_82571PT_QUAD_COPPER:
+               adapter->flags |= FLAG_IS_QUAD_PORT;
+               /* mark the first port */
+               if (global_quad_port_a == 0)
+                       adapter->flags |= FLAG_IS_QUAD_PORT_A;
+               /* Reset for multiple quad port adapters */
+               global_quad_port_a++;
+               if (global_quad_port_a == 4)
+                       global_quad_port_a = 0;
+               break;
+       default:
+               break;
+       }
+
+       switch (adapter->hw.mac.type) {
+       case e1000_82571:
+               /* these dual ports don't have WoL on port B at all */
+               if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
+                    (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
+                    (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
+                   (is_port_b))
+                       adapter->flags &= ~FLAG_HAS_WOL;
+               /* quad ports only support WoL on port A */
+               if (adapter->flags & FLAG_IS_QUAD_PORT &&
+                   (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
+                       adapter->flags &= ~FLAG_HAS_WOL;
+               /* Does not support WoL on any port */
+               if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
+                       adapter->flags &= ~FLAG_HAS_WOL;
+               break;
+
+       case e1000_82573:
+               if (pdev->device == E1000_DEV_ID_82573L) {
+                       e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
+                                      &eeprom_data);
+                       if (eeprom_data & NVM_WORD1A_ASPM_MASK)
+                               adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
+               }
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the PHY registers and stores the PHY ID and possibly the PHY
+ *  revision in the hardware structure.
+ **/
+static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 phy_id = 0;
+
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               /*
+                * The 82571 firmware may still be configuring the PHY.
+                * In this case, we cannot access the PHY until the
+                * configuration is done.  So we explicitly set the
+                * PHY ID.
+                */
+               phy->id = IGP01E1000_I_PHY_ID;
+               break;
+       case e1000_82573:
+               return e1000e_get_phy_id(hw);
+               break;
+       case e1000_82574:
+               ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
+               if (ret_val)
+                       return ret_val;
+
+               phy->id = (u32)(phy_id << 16);
+               udelay(20);
+               ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
+               if (ret_val)
+                       return ret_val;
+
+               phy->id |= (u32)(phy_id);
+               phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
+               break;
+       default:
+               return -E1000_ERR_PHY;
+               break;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the HW semaphore to access the PHY or NVM
+ **/
+static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
+{
+       u32 swsm;
+       s32 timeout = hw->nvm.word_size + 1;
+       s32 i = 0;
+
+       /* Get the FW semaphore. */
+       for (i = 0; i < timeout; i++) {
+               swsm = er32(SWSM);
+               ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
+
+               /* Semaphore acquired if bit latched */
+               if (er32(SWSM) & E1000_SWSM_SWESMBI)
+                       break;
+
+               udelay(50);
+       }
+
+       if (i == timeout) {
+               /* Release semaphores */
+               e1000e_put_hw_semaphore(hw);
+               hw_dbg(hw, "Driver can't access the NVM\n");
+               return -E1000_ERR_NVM;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used to access the PHY or NVM
+ **/
+static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
+{
+       u32 swsm;
+
+       swsm = er32(SWSM);
+
+       swsm &= ~E1000_SWSM_SWESMBI;
+
+       ew32(SWSM, swsm);
+}
+
+/**
+ *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
+ *  @hw: pointer to the HW structure
+ *
+ *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
+ *  Then for non-82573 hardware, set the EEPROM access request bit and wait
+ *  for EEPROM access grant bit.  If the access grant bit is not set, release
+ *  hardware semaphore.
+ **/
+static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
+{
+       s32 ret_val;
+
+       ret_val = e1000_get_hw_semaphore_82571(hw);
+       if (ret_val)
+               return ret_val;
+
+       if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
+               ret_val = e1000e_acquire_nvm(hw);
+
+       if (ret_val)
+               e1000_put_hw_semaphore_82571(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
+ *  @hw: pointer to the HW structure
+ *
+ *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
+ **/
+static void e1000_release_nvm_82571(struct e1000_hw *hw)
+{
+       e1000e_release_nvm(hw);
+       e1000_put_hw_semaphore_82571(hw);
+}
+
+/**
+ *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
+ *  @hw: pointer to the HW structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @words: number of words to write
+ *  @data: 16 bit word(s) to be written to the EEPROM
+ *
+ *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
+ *
+ *  If e1000e_update_nvm_checksum is not called after this function, the
+ *  EEPROM will most likely contain an invalid checksum.
+ **/
+static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
+                                u16 *data)
+{
+       s32 ret_val;
+
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+               ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
+               break;
+       case e1000_82571:
+       case e1000_82572:
+               ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
+               break;
+       default:
+               ret_val = -E1000_ERR_NVM;
+               break;
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
+ *  up to the checksum.  Then calculates the EEPROM checksum and writes the
+ *  value to the EEPROM.
+ **/
+static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
+{
+       u32 eecd;
+       s32 ret_val;
+       u16 i;
+
+       ret_val = e1000e_update_nvm_checksum_generic(hw);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * If our nvm is an EEPROM, then we're done
+        * otherwise, commit the checksum to the flash NVM.
+        */
+       if (hw->nvm.type != e1000_nvm_flash_hw)
+               return ret_val;
+
+       /* Check for pending operations. */
+       for (i = 0; i < E1000_FLASH_UPDATES; i++) {
+               msleep(1);
+               if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
+                       break;
+       }
+
+       if (i == E1000_FLASH_UPDATES)
+               return -E1000_ERR_NVM;
+
+       /* Reset the firmware if using STM opcode. */
+       if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
+               /*
+                * The enabling of and the actual reset must be done
+                * in two write cycles.
+                */
+               ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
+               e1e_flush();
+               ew32(HICR, E1000_HICR_FW_RESET);
+       }
+
+       /* Commit the write to flash */
+       eecd = er32(EECD) | E1000_EECD_FLUPD;
+       ew32(EECD, eecd);
+
+       for (i = 0; i < E1000_FLASH_UPDATES; i++) {
+               msleep(1);
+               if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
+                       break;
+       }
+
+       if (i == E1000_FLASH_UPDATES)
+               return -E1000_ERR_NVM;
+
+       return 0;
+}
+
+/**
+ *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
+ *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
+ **/
+static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
+{
+       if (hw->nvm.type == e1000_nvm_flash_hw)
+               e1000_fix_nvm_checksum_82571(hw);
+
+       return e1000e_validate_nvm_checksum_generic(hw);
+}
+
+/**
+ *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
+ *  @hw: pointer to the HW structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @words: number of words to write
+ *  @data: 16 bit word(s) to be written to the EEPROM
+ *
+ *  After checking for invalid values, poll the EEPROM to ensure the previous
+ *  command has completed before trying to write the next word.  After write
+ *  poll for completion.
+ *
+ *  If e1000e_update_nvm_checksum is not called after this function, the
+ *  EEPROM will most likely contain an invalid checksum.
+ **/
+static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+                                     u16 words, u16 *data)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 i;
+       u32 eewr = 0;
+       s32 ret_val = 0;
+
+       /*
+        * A check for invalid values:  offset too large, too many words,
+        * and not enough words.
+        */
+       if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
+           (words == 0)) {
+               hw_dbg(hw, "nvm parameter(s) out of bounds\n");
+               return -E1000_ERR_NVM;
+       }
+
+       for (i = 0; i < words; i++) {
+               eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
+                      ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
+                      E1000_NVM_RW_REG_START;
+
+               ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
+               if (ret_val)
+                       break;
+
+               ew32(EEWR, eewr);
+
+               ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
+               if (ret_val)
+                       break;
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000_get_cfg_done_82571 - Poll for configuration done
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the management control register for the config done bit to be set.
+ **/
+static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
+{
+       s32 timeout = PHY_CFG_TIMEOUT;
+
+       while (timeout) {
+               if (er32(EEMNGCTL) &
+                   E1000_NVM_CFG_DONE_PORT_0)
+                       break;
+               msleep(1);
+               timeout--;
+       }
+       if (!timeout) {
+               hw_dbg(hw, "MNG configuration cycle has not completed.\n");
+               return -E1000_ERR_RESET;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
+ *  @hw: pointer to the HW structure
+ *  @active: TRUE to enable LPLU, FALSE to disable
+ *
+ *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
+ *  this function also disables smart speed and vice versa.  LPLU will not be
+ *  activated unless the device autonegotiation advertisement meets standards
+ *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
+ *  pointer entry point only called by PHY setup routines.
+ **/
+static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 data;
+
+       ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
+       if (ret_val)
+               return ret_val;
+
+       if (active) {
+               data |= IGP02E1000_PM_D0_LPLU;
+               ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
+               if (ret_val)
+                       return ret_val;
+
+               /* When LPLU is enabled, we should disable SmartSpeed */
+               ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
+               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
+               if (ret_val)
+                       return ret_val;
+       } else {
+               data &= ~IGP02E1000_PM_D0_LPLU;
+               ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
+               /*
+                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                * during Dx states where the power conservation is most
+                * important.  During driver activity we should enable
+                * SmartSpeed, so performance is maintained.
+                */
+               if (phy->smart_speed == e1000_smart_speed_on) {
+                       ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          data);
+                       if (ret_val)
+                               return ret_val;
+               } else if (phy->smart_speed == e1000_smart_speed_off) {
+                       ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          data);
+                       if (ret_val)
+                               return ret_val;
+               }
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_reset_hw_82571 - Reset hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  This resets the hardware into a known state.  This is a
+ *  function pointer entry point called by the api module.
+ **/
+static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       u32 extcnf_ctrl;
+       u32 ctrl_ext;
+       u32 icr;
+       s32 ret_val;
+       u16 i = 0;
+
+       /*
+        * Prevent the PCI-E bus from sticking if there is no TLP connection
+        * on the last TLP read/write transaction when MAC is reset.
+        */
+       ret_val = e1000e_disable_pcie_master(hw);
+       if (ret_val)
+               hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+
+       hw_dbg(hw, "Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       ew32(RCTL, 0);
+       ew32(TCTL, E1000_TCTL_PSP);
+       e1e_flush();
+
+       msleep(10);
+
+       /*
+        * Must acquire the MDIO ownership before MAC reset.
+        * Ownership defaults to firmware after a reset.
+        */
+       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+               extcnf_ctrl = er32(EXTCNF_CTRL);
+               extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+               do {
+                       ew32(EXTCNF_CTRL, extcnf_ctrl);
+                       extcnf_ctrl = er32(EXTCNF_CTRL);
+
+                       if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
+                               break;
+
+                       extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+                       msleep(2);
+                       i++;
+               } while (i < MDIO_OWNERSHIP_TIMEOUT);
+       }
+
+       ctrl = er32(CTRL);
+
+       hw_dbg(hw, "Issuing a global reset to MAC\n");
+       ew32(CTRL, ctrl | E1000_CTRL_RST);
+
+       if (hw->nvm.type == e1000_nvm_flash_hw) {
+               udelay(10);
+               ctrl_ext = er32(CTRL_EXT);
+               ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+               ew32(CTRL_EXT, ctrl_ext);
+               e1e_flush();
+       }
+
+       ret_val = e1000e_get_auto_rd_done(hw);
+       if (ret_val)
+               /* We don't want to continue accessing MAC registers. */
+               return ret_val;
+
+       /*
+        * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
+        * Need to wait for Phy configuration completion before accessing
+        * NVM and Phy.
+        */
+       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
+               msleep(25);
+
+       /* Clear any pending interrupt events. */
+       ew32(IMC, 0xffffffff);
+       icr = er32(ICR);
+
+       if (hw->mac.type == e1000_82571 &&
+               hw->dev_spec.e82571.alt_mac_addr_is_present)
+                       e1000e_set_laa_state_82571(hw, 1);
+
+       return 0;
+}
+
+/**
+ *  e1000_init_hw_82571 - Initialize hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  This inits the hardware readying it for operation.
+ **/
+static s32 e1000_init_hw_82571(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 reg_data;
+       s32 ret_val;
+       u16 i;
+       u16 rar_count = mac->rar_entry_count;
+
+       e1000_initialize_hw_bits_82571(hw);
+
+       /* Initialize identification LED */
+       ret_val = e1000e_id_led_init(hw);
+       if (ret_val) {
+               hw_dbg(hw, "Error initializing identification LED\n");
+               return ret_val;
+       }
+
+       /* Disabling VLAN filtering */
+       hw_dbg(hw, "Initializing the IEEE VLAN\n");
+       e1000e_clear_vfta(hw);
+
+       /* Setup the receive address. */
+       /*
+        * If, however, a locally administered address was assigned to the
+        * 82571, we must reserve a RAR for it to work around an issue where
+        * resetting one port will reload the MAC on the other port.
+        */
+       if (e1000e_get_laa_state_82571(hw))
+               rar_count--;
+       e1000e_init_rx_addrs(hw, rar_count);
+
+       /* Zero out the Multicast HASH table */
+       hw_dbg(hw, "Zeroing the MTA\n");
+       for (i = 0; i < mac->mta_reg_count; i++)
+               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
+
+       /* Setup link and flow control */
+       ret_val = e1000_setup_link_82571(hw);
+
+       /* Set the transmit descriptor write-back policy */
+       reg_data = er32(TXDCTL(0));
+       reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                  E1000_TXDCTL_FULL_TX_DESC_WB |
+                  E1000_TXDCTL_COUNT_DESC;
+       ew32(TXDCTL(0), reg_data);
+
+       /* ...for both queues. */
+       if (mac->type != e1000_82573 && mac->type != e1000_82574) {
+               reg_data = er32(TXDCTL(1));
+               reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                          E1000_TXDCTL_FULL_TX_DESC_WB |
+                          E1000_TXDCTL_COUNT_DESC;
+               ew32(TXDCTL(1), reg_data);
+       } else {
+               e1000e_enable_tx_pkt_filtering(hw);
+               reg_data = er32(GCR);
+               reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+               ew32(GCR, reg_data);
+       }
+
+       /*
+        * Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000_clear_hw_cntrs_82571(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
+ *  @hw: pointer to the HW structure
+ *
+ *  Initializes required hardware-dependent bits needed for normal operation.
+ **/
+static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
+{
+       u32 reg;
+
+       /* Transmit Descriptor Control 0 */
+       reg = er32(TXDCTL(0));
+       reg |= (1 << 22);
+       ew32(TXDCTL(0), reg);
+
+       /* Transmit Descriptor Control 1 */
+       reg = er32(TXDCTL(1));
+       reg |= (1 << 22);
+       ew32(TXDCTL(1), reg);
+
+       /* Transmit Arbitration Control 0 */
+       reg = er32(TARC(0));
+       reg &= ~(0xF << 27); /* 30:27 */
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
+               break;
+       default:
+               break;
+       }
+       ew32(TARC(0), reg);
+
+       /* Transmit Arbitration Control 1 */
+       reg = er32(TARC(1));
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               reg &= ~((1 << 29) | (1 << 30));
+               reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
+               if (er32(TCTL) & E1000_TCTL_MULR)
+                       reg &= ~(1 << 28);
+               else
+                       reg |= (1 << 28);
+               ew32(TARC(1), reg);
+               break;
+       default:
+               break;
+       }
+
+       /* Device Control */
+       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+               reg = er32(CTRL);
+               reg &= ~(1 << 29);
+               ew32(CTRL, reg);
+       }
+
+       /* Extended Device Control */
+       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+               reg = er32(CTRL_EXT);
+               reg &= ~(1 << 23);
+               reg |= (1 << 22);
+               ew32(CTRL_EXT, reg);
+       }
+
+       if (hw->mac.type == e1000_82571) {
+               reg = er32(PBA_ECC);
+               reg |= E1000_PBA_ECC_CORR_EN;
+               ew32(PBA_ECC, reg);
+       }
+
+       /* PCI-Ex Control Register */
+       if (hw->mac.type == e1000_82574) {
+               reg = er32(GCR);
+               reg |= (1 << 22);
+               ew32(GCR, reg);
+       }
+
+       return;
+}
+
+/**
+ *  e1000e_clear_vfta - Clear VLAN filter table
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the register array which contains the VLAN filter table by
+ *  setting all the values to 0.
+ **/
+void e1000e_clear_vfta(struct e1000_hw *hw)
+{
+       u32 offset;
+       u32 vfta_value = 0;
+       u32 vfta_offset = 0;
+       u32 vfta_bit_in_reg = 0;
+
+       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+               if (hw->mng_cookie.vlan_id != 0) {
+                       /*
+                        * The VFTA is a 4096b bit-field, each identifying
+                        * a single VLAN ID.  The following operations
+                        * determine which 32b entry (i.e. offset) into the
+                        * array we want to set the VLAN ID (i.e. bit) of
+                        * the manageability unit.
+                        */
+                       vfta_offset = (hw->mng_cookie.vlan_id >>
+                                      E1000_VFTA_ENTRY_SHIFT) &
+                                     E1000_VFTA_ENTRY_MASK;
+                       vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
+                                              E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
+               }
+       }
+       for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
+               /*
+                * If the offset we want to clear is the same offset of the
+                * manageability VLAN ID, then clear all bits except that of
+                * the manageability unit.
+                */
+               vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
+               E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
+               e1e_flush();
+       }
+}
+
+/**
+ *  e1000_check_mng_mode_82574 - Check manageability is enabled
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the NVM Initialization Control Word 2 and returns true
+ *  (>0) if any manageability is enabled, else false (0).
+ **/
+static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
+{
+       u16 data;
+
+       e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
+       return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
+}
+
+/**
+ *  e1000_led_on_82574 - Turn LED on
+ *  @hw: pointer to the HW structure
+ *
+ *  Turn LED on.
+ **/
+static s32 e1000_led_on_82574(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       u32 i;
+
+       ctrl = hw->mac.ledctl_mode2;
+       if (!(E1000_STATUS_LU & er32(STATUS))) {
+               /*
+                * If no link, then turn LED on by setting the invert bit
+                * for each LED that's "on" (0x0E) in ledctl_mode2.
+                */
+               for (i = 0; i < 4; i++)
+                       if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
+                           E1000_LEDCTL_MODE_LED_ON)
+                               ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
+       }
+       ew32(LEDCTL, ctrl);
+
+       return 0;
+}
+
+/**
+ *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
+ *  @hw: pointer to the HW structure
+ *  @mc_addr_list: array of multicast addresses to program
+ *  @mc_addr_count: number of multicast addresses to program
+ *  @rar_used_count: the first RAR register free to program
+ *  @rar_count: total number of supported Receive Address Registers
+ *
+ *  Updates the Receive Address Registers and Multicast Table Array.
+ *  The caller must have a packed mc_addr_list of multicast addresses.
+ *  The parameter rar_count will usually be hw->mac.rar_entry_count
+ *  unless there are workarounds that change this.
+ **/
+static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
+                                           u8 *mc_addr_list,
+                                           u32 mc_addr_count,
+                                           u32 rar_used_count,
+                                           u32 rar_count)
+{
+       if (e1000e_get_laa_state_82571(hw))
+               rar_count--;
+
+       e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
+                                          rar_used_count, rar_count);
+}
+
+/**
+ *  e1000_setup_link_82571 - Setup flow control and link settings
+ *  @hw: pointer to the HW structure
+ *
+ *  Determines which flow control settings to use, then configures flow
+ *  control.  Calls the appropriate media-specific link configuration
+ *  function.  Assuming the adapter has a valid link partner, a valid link
+ *  should be established.  Assumes the hardware has previously been reset
+ *  and the transmitter and receiver are not enabled.
+ **/
+static s32 e1000_setup_link_82571(struct e1000_hw *hw)
+{
+       /*
+        * 82573 does not have a word in the NVM to determine
+        * the default flow control setting, so we explicitly
+        * set it to full.
+        */
+       if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
+           hw->fc.type == e1000_fc_default)
+               hw->fc.type = e1000_fc_full;
+
+       return e1000e_setup_link(hw);
+}
+
+/**
+ *  e1000_setup_copper_link_82571 - Configure copper link settings
+ *  @hw: pointer to the HW structure
+ *
+ *  Configures the link for auto-neg or forced speed and duplex.  Then we check
+ *  for link, once link is established calls to configure collision distance
+ *  and flow control are called.
+ **/
+static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       u32 led_ctrl;
+       s32 ret_val;
+
+       ctrl = er32(CTRL);
+       ctrl |= E1000_CTRL_SLU;
+       ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ew32(CTRL, ctrl);
+
+       switch (hw->phy.type) {
+       case e1000_phy_m88:
+       case e1000_phy_bm:
+               ret_val = e1000e_copper_link_setup_m88(hw);
+               break;
+       case e1000_phy_igp_2:
+               ret_val = e1000e_copper_link_setup_igp(hw);
+               /* Setup activity LED */
+               led_ctrl = er32(LEDCTL);
+               led_ctrl &= IGP_ACTIVITY_LED_MASK;
+               led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+               ew32(LEDCTL, led_ctrl);
+               break;
+       default:
+               return -E1000_ERR_PHY;
+               break;
+       }
+
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000e_setup_copper_link(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
+ *  @hw: pointer to the HW structure
+ *
+ *  Configures collision distance and flow control for fiber and serdes links.
+ *  Upon successful setup, poll for link.
+ **/
+static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
+{
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               /*
+                * If SerDes loopback mode is entered, there is no form
+                * of reset to take the adapter out of that mode.  So we
+                * have to explicitly take the adapter out of loopback
+                * mode.  This prevents drivers from twiddling their thumbs
+                * if another tool failed to take it out of loopback mode.
+                */
+               ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
+               break;
+       default:
+               break;
+       }
+
+       return e1000e_setup_fiber_serdes_link(hw);
+}
+
+/**
+ *  e1000_valid_led_default_82571 - Verify a valid default LED config
+ *  @hw: pointer to the HW structure
+ *  @data: pointer to the NVM (EEPROM)
+ *
+ *  Read the EEPROM for the current default LED configuration.  If the
+ *  LED configuration is not valid, set to a valid LED configuration.
+ **/
+static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
+{
+       s32 ret_val;
+
+       ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
+       if (ret_val) {
+               hw_dbg(hw, "NVM Read Error\n");
+               return ret_val;
+       }
+
+       if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
+           *data == ID_LED_RESERVED_F746)
+               *data = ID_LED_DEFAULT_82573;
+       else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
+               *data = ID_LED_DEFAULT;
+
+       return 0;
+}
+
+/**
+ *  e1000e_get_laa_state_82571 - Get locally administered address state
+ *  @hw: pointer to the HW structure
+ *
+ *  Retrieve and return the current locally administered address state.
+ **/
+bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
+{
+       if (hw->mac.type != e1000_82571)
+               return 0;
+
+       return hw->dev_spec.e82571.laa_is_present;
+}
+
+/**
+ *  e1000e_set_laa_state_82571 - Set locally administered address state
+ *  @hw: pointer to the HW structure
+ *  @state: enable/disable locally administered address
+ *
+ *  Enable/Disable the current locally administers address state.
+ **/
+void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
+{
+       if (hw->mac.type != e1000_82571)
+               return;
+
+       hw->dev_spec.e82571.laa_is_present = state;
+
+       /* If workaround is activated... */
+       if (state)
+               /*
+                * Hold a copy of the LAA in RAR[14] This is done so that
+                * between the time RAR[0] gets clobbered and the time it
+                * gets fixed, the actual LAA is in one of the RARs and no
+                * incoming packets directed to this port are dropped.
+                * Eventually the LAA will be in RAR[0] and RAR[14].
+                */
+               e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
+}
+
+/**
+ *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Verifies that the EEPROM has completed the update.  After updating the
+ *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
+ *  the checksum fix is not implemented, we need to set the bit and update
+ *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
+ *  we need to return bad checksum.
+ **/
+static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       s32 ret_val;
+       u16 data;
+
+       if (nvm->type != e1000_nvm_flash_hw)
+               return 0;
+
+       /*
+        * Check bit 4 of word 10h.  If it is 0, firmware is done updating
+        * 10h-12h.  Checksum may need to be fixed.
+        */
+       ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
+       if (ret_val)
+               return ret_val;
+
+       if (!(data & 0x10)) {
+               /*
+                * Read 0x23 and check bit 15.  This bit is a 1
+                * when the checksum has already been fixed.  If
+                * the checksum is still wrong and this bit is a
+                * 1, we need to return bad checksum.  Otherwise,
+                * we need to set this bit to a 1 and update the
+                * checksum.
+                */
+               ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
+               if (ret_val)
+                       return ret_val;
+
+               if (!(data & 0x8000)) {
+                       data |= 0x8000;
+                       ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
+                       if (ret_val)
+                               return ret_val;
+                       ret_val = e1000e_update_nvm_checksum(hw);
+               }
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the hardware counters by reading the counter registers.
+ **/
+static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
+{
+       u32 temp;
+
+       e1000e_clear_hw_cntrs_base(hw);
+
+       temp = er32(PRC64);
+       temp = er32(PRC127);
+       temp = er32(PRC255);
+       temp = er32(PRC511);
+       temp = er32(PRC1023);
+       temp = er32(PRC1522);
+       temp = er32(PTC64);
+       temp = er32(PTC127);
+       temp = er32(PTC255);
+       temp = er32(PTC511);
+       temp = er32(PTC1023);
+       temp = er32(PTC1522);
+
+       temp = er32(ALGNERRC);
+       temp = er32(RXERRC);
+       temp = er32(TNCRS);
+       temp = er32(CEXTERR);
+       temp = er32(TSCTC);
+       temp = er32(TSCTFC);
+
+       temp = er32(MGTPRC);
+       temp = er32(MGTPDC);
+       temp = er32(MGTPTC);
+
+       temp = er32(IAC);
+       temp = er32(ICRXOC);
+
+       temp = er32(ICRXPTC);
+       temp = er32(ICRXATC);
+       temp = er32(ICTXPTC);
+       temp = er32(ICTXATC);
+       temp = er32(ICTXQEC);
+       temp = er32(ICTXQMTC);
+       temp = er32(ICRXDMTC);
+}
+
+static struct e1000_mac_operations e82571_mac_ops = {
+       /* .check_mng_mode: mac type dependent */
+       /* .check_for_link: media type dependent */
+       .cleanup_led            = e1000e_cleanup_led_generic,
+       .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
+       .get_bus_info           = e1000e_get_bus_info_pcie,
+       /* .get_link_up_info: media type dependent */
+       /* .led_on: mac type dependent */
+       .led_off                = e1000e_led_off_generic,
+       .update_mc_addr_list    = e1000_update_mc_addr_list_82571,
+       .reset_hw               = e1000_reset_hw_82571,
+       .init_hw                = e1000_init_hw_82571,
+       .setup_link             = e1000_setup_link_82571,
+       /* .setup_physical_interface: media type dependent */
+};
+
+static struct e1000_phy_operations e82_phy_ops_igp = {
+       .acquire_phy            = e1000_get_hw_semaphore_82571,
+       .check_reset_block      = e1000e_check_reset_block_generic,
+       .commit_phy             = NULL,
+       .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
+       .get_cfg_done           = e1000_get_cfg_done_82571,
+       .get_cable_length       = e1000e_get_cable_length_igp_2,
+       .get_phy_info           = e1000e_get_phy_info_igp,
+       .read_phy_reg           = e1000e_read_phy_reg_igp,
+       .release_phy            = e1000_put_hw_semaphore_82571,
+       .reset_phy              = e1000e_phy_hw_reset_generic,
+       .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
+       .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
+       .write_phy_reg          = e1000e_write_phy_reg_igp,
+};
+
+static struct e1000_phy_operations e82_phy_ops_m88 = {
+       .acquire_phy            = e1000_get_hw_semaphore_82571,
+       .check_reset_block      = e1000e_check_reset_block_generic,
+       .commit_phy             = e1000e_phy_sw_reset,
+       .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
+       .get_cfg_done           = e1000e_get_cfg_done,
+       .get_cable_length       = e1000e_get_cable_length_m88,
+       .get_phy_info           = e1000e_get_phy_info_m88,
+       .read_phy_reg           = e1000e_read_phy_reg_m88,
+       .release_phy            = e1000_put_hw_semaphore_82571,
+       .reset_phy              = e1000e_phy_hw_reset_generic,
+       .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
+       .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
+       .write_phy_reg          = e1000e_write_phy_reg_m88,
+};
+
+static struct e1000_phy_operations e82_phy_ops_bm = {
+       .acquire_phy            = e1000_get_hw_semaphore_82571,
+       .check_reset_block      = e1000e_check_reset_block_generic,
+       .commit_phy             = e1000e_phy_sw_reset,
+       .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
+       .get_cfg_done           = e1000e_get_cfg_done,
+       .get_cable_length       = e1000e_get_cable_length_m88,
+       .get_phy_info           = e1000e_get_phy_info_m88,
+       .read_phy_reg           = e1000e_read_phy_reg_bm2,
+       .release_phy            = e1000_put_hw_semaphore_82571,
+       .reset_phy              = e1000e_phy_hw_reset_generic,
+       .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
+       .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
+       .write_phy_reg          = e1000e_write_phy_reg_bm2,
+};
+
+static struct e1000_nvm_operations e82571_nvm_ops = {
+       .acquire_nvm            = e1000_acquire_nvm_82571,
+       .read_nvm               = e1000e_read_nvm_eerd,
+       .release_nvm            = e1000_release_nvm_82571,
+       .update_nvm             = e1000_update_nvm_checksum_82571,
+       .valid_led_default      = e1000_valid_led_default_82571,
+       .validate_nvm           = e1000_validate_nvm_checksum_82571,
+       .write_nvm              = e1000_write_nvm_82571,
+};
+
+struct e1000_info e1000_82571_info = {
+       .mac                    = e1000_82571,
+       .flags                  = FLAG_HAS_HW_VLAN_FILTER
+                                 | FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_HAS_WOL
+                                 | FLAG_APME_IN_CTRL3
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_HAS_SMART_POWER_DOWN
+                                 | FLAG_RESET_OVERWRITES_LAA /* errata */
+                                 | FLAG_TARC_SPEED_MODE_BIT /* errata */
+                                 | FLAG_APME_CHECK_PORT_B,
+       .pba                    = 38,
+       .get_variants           = e1000_get_variants_82571,
+       .mac_ops                = &e82571_mac_ops,
+       .phy_ops                = &e82_phy_ops_igp,
+       .nvm_ops                = &e82571_nvm_ops,
+};
+
+struct e1000_info e1000_82572_info = {
+       .mac                    = e1000_82572,
+       .flags                  = FLAG_HAS_HW_VLAN_FILTER
+                                 | FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_HAS_WOL
+                                 | FLAG_APME_IN_CTRL3
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
+       .pba                    = 38,
+       .get_variants           = e1000_get_variants_82571,
+       .mac_ops                = &e82571_mac_ops,
+       .phy_ops                = &e82_phy_ops_igp,
+       .nvm_ops                = &e82571_nvm_ops,
+};
+
+struct e1000_info e1000_82573_info = {
+       .mac                    = e1000_82573,
+       .flags                  = FLAG_HAS_HW_VLAN_FILTER
+                                 | FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_HAS_WOL
+                                 | FLAG_APME_IN_CTRL3
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_SMART_POWER_DOWN
+                                 | FLAG_HAS_AMT
+                                 | FLAG_HAS_ERT
+                                 | FLAG_HAS_SWSM_ON_LOAD,
+       .pba                    = 20,
+       .get_variants           = e1000_get_variants_82571,
+       .mac_ops                = &e82571_mac_ops,
+       .phy_ops                = &e82_phy_ops_m88,
+       .nvm_ops                = &e82571_nvm_ops,
+};
+
+struct e1000_info e1000_82574_info = {
+       .mac                    = e1000_82574,
+       .flags                  = FLAG_HAS_HW_VLAN_FILTER
+                                 | FLAG_HAS_MSIX
+                                 | FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_HAS_WOL
+                                 | FLAG_APME_IN_CTRL3
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_SMART_POWER_DOWN
+                                 | FLAG_HAS_AMT
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD,
+       .pba                    = 20,
+       .get_variants           = e1000_get_variants_82571,
+       .mac_ops                = &e82571_mac_ops,
+       .phy_ops                = &e82_phy_ops_bm,
+       .nvm_ops                = &e82571_nvm_ops,
+};
+
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/Makefile
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/Makefile       Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,37 @@
+################################################################################
+#
+# Intel PRO/1000 Linux driver
+# Copyright(c) 1999 - 2008 Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program; if not, write to the Free Software Foundation, Inc.,
+# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# The full GNU General Public License is included in this distribution in
+# the file called "COPYING".
+#
+# Contact Information:
+# Linux NICS <linux.nics@xxxxxxxxx>
+# e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+#
+################################################################################
+
+#
+# Makefile for the Intel(R) PRO/1000 ethernet driver
+#
+
+obj-$(CONFIG_E1000E) += e1000e.o
+
+e1000e-objs := 82571.o ich8lan.o es2lan.o \
+              lib.o phy.o param.o ethtool.o netdev.o
+
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/defines.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/defines.h      Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,784 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _E1000_DEFINES_H_
+#define _E1000_DEFINES_H_
+
+#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+
+/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
+#define REQ_TX_DESCRIPTOR_MULTIPLE  8
+#define REQ_RX_DESCRIPTOR_MULTIPLE  8
+
+/* Definitions for power management and wakeup registers */
+/* Wake Up Control */
+#define E1000_WUC_APME       0x00000001 /* APM Enable */
+#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
+
+/* Wake Up Filter Control */
+#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
+
+/* Extended Device Control */
+#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
+#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
+#define E1000_CTRL_EXT_EIAME          0x01000000
+#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
+#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge 
Auto-mask */
+#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers 
after IMS clear */
+#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
+
+/* Receive Descriptor bit definitions */
+#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
+#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
+#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
+#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
+#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
+#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
+#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
+#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
+#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
+
+#define E1000_RXDEXT_STATERR_CE    0x01000000
+#define E1000_RXDEXT_STATERR_SE    0x02000000
+#define E1000_RXDEXT_STATERR_SEQ   0x04000000
+#define E1000_RXDEXT_STATERR_CXE   0x10000000
+#define E1000_RXDEXT_STATERR_RXE   0x80000000
+
+/* mask to determine if packets should be dropped due to frame errors */
+#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
+    E1000_RXD_ERR_CE  |                \
+    E1000_RXD_ERR_SE  |                \
+    E1000_RXD_ERR_SEQ |                \
+    E1000_RXD_ERR_CXE |                \
+    E1000_RXD_ERR_RXE)
+
+/* Same mask, but for extended and packet split descriptors */
+#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
+    E1000_RXDEXT_STATERR_CE  |            \
+    E1000_RXDEXT_STATERR_SE  |            \
+    E1000_RXDEXT_STATERR_SEQ |            \
+    E1000_RXDEXT_STATERR_CXE |            \
+    E1000_RXDEXT_STATERR_RXE)
+
+#define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
+
+/* Management Control */
+#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
+#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
+#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
+#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
+/* Enable MAC address filtering */
+#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
+/* Enable MNG packets to host memory */
+#define E1000_MANC_EN_MNG2HOST   0x00200000
+
+/* Receive Control */
+#define E1000_RCTL_EN             0x00000002    /* enable */
+#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
+#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable 
*/
+#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab 
*/
+#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
+#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
+#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
+#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
+#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
+#define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min threshold size 
*/
+#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
+#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
+/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
+#define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */
+#define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */
+#define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */
+/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
+#define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */
+#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
+#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
+#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
+#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
+#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
+
+/*
+ * Use byte values for the following shift parameters
+ * Usage:
+ *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
+ *                  E1000_PSRCTL_BSIZE0_MASK) |
+ *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
+ *                  E1000_PSRCTL_BSIZE1_MASK) |
+ *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
+ *                  E1000_PSRCTL_BSIZE2_MASK) |
+ *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
+ *                  E1000_PSRCTL_BSIZE3_MASK))
+ * where value0 = [128..16256],  default=256
+ *       value1 = [1024..64512], default=4096
+ *       value2 = [0..64512],    default=4096
+ *       value3 = [0..64512],    default=0
+ */
+
+#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
+#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
+#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
+#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
+
+#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
+#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
+#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
+#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
+
+/* SWFW_SYNC Definitions */
+#define E1000_SWFW_EEP_SM   0x1
+#define E1000_SWFW_PHY0_SM  0x2
+#define E1000_SWFW_PHY1_SM  0x4
+#define E1000_SWFW_CSR_SM   0x8
+
+/* Device Control */
+#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests 
*/
+#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
+#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
+#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
+#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
+#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
+#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
+#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
+#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
+#define E1000_CTRL_RST      0x04000000  /* Global reset */
+#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
+#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
+
+/*
+ * Bit definitions for the Management Data IO (MDIO) and Management Data
+ * Clock (MDC) pins in the Device Control Register.
+ */
+
+/* Device Status */
+#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
+#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
+#define E1000_STATUS_FUNC_SHIFT 2
+#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
+#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
+#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
+#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM 
*/
+#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master 
requests. */
+
+/* Constants used to interpret the masked PCI-X bus speed. */
+
+#define HALF_DUPLEX 1
+#define FULL_DUPLEX 2
+
+
+#define ADVERTISE_10_HALF                 0x0001
+#define ADVERTISE_10_FULL                 0x0002
+#define ADVERTISE_100_HALF                0x0004
+#define ADVERTISE_100_FULL                0x0008
+#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
+#define ADVERTISE_1000_FULL               0x0020
+
+/* 1000/H is not supported, nor spec-compliant. */
+#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
+                               ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
+                                                    ADVERTISE_1000_FULL)
+#define E1000_ALL_NOT_GIG      ( ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
+                               ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
+#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
+#define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
+#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
+
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
+
+/* LED Control */
+#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
+#define E1000_LEDCTL_LED0_MODE_SHIFT      0
+#define E1000_LEDCTL_LED0_IVRT            0x00000040
+#define E1000_LEDCTL_LED0_BLINK           0x00000080
+
+#define E1000_LEDCTL_MODE_LED_ON        0xE
+#define E1000_LEDCTL_MODE_LED_OFF       0xF
+
+/* Transmit Descriptor bit definitions */
+#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
+#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+
+/* Transmit Control */
+#define E1000_TCTL_EN     0x00000002    /* enable Tx */
+#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
+#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
+#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
+#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
+#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
+
+/* Transmit Arbitration Count */
+
+/* SerDes Control */
+#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+
+/* Receive Checksum Control */
+#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
+
+/* Header split receive */
+#define E1000_RFCTL_ACK_DIS             0x00001000
+#define E1000_RFCTL_EXTEN               0x00008000
+#define E1000_RFCTL_IPV6_EX_DIS         0x00010000
+#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
+
+/* Collision related configuration parameters */
+#define E1000_COLLISION_THRESHOLD       15
+#define E1000_CT_SHIFT                  4
+#define E1000_COLLISION_DISTANCE        63
+#define E1000_COLD_SHIFT                12
+
+/* Default values for the transmit IPG register */
+#define DEFAULT_82543_TIPG_IPGT_COPPER 8
+
+#define E1000_TIPG_IPGT_MASK  0x000003FF
+
+#define DEFAULT_82543_TIPG_IPGR1 8
+#define E1000_TIPG_IPGR1_SHIFT  10
+
+#define DEFAULT_82543_TIPG_IPGR2 6
+#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
+#define E1000_TIPG_IPGR2_SHIFT  20
+
+#define MAX_JUMBO_FRAME_SIZE    0x3F00
+
+/* Extended Configuration Control and Size */
+#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
+#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
+#define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
+
+#define E1000_PHY_CTRL_D0A_LPLU           0x00000002
+#define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
+#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
+#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
+
+#define E1000_KABGTXD_BGSQLBIAS           0x00050000
+
+/* PBA constants */
+#define E1000_PBA_8K  0x0008    /* 8KB */
+#define E1000_PBA_16K 0x0010    /* 16KB */
+
+#define E1000_PBS_16K E1000_PBA_16K
+
+#define IFS_MAX       80
+#define IFS_MIN       40
+#define IFS_RATIO     4
+#define IFS_STEP      10
+#define MIN_NUM_XMITS 1000
+
+/* SW Semaphore Register */
+#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
+#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
+
+/* Interrupt Cause Read */
+#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
+#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
+#define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */
+#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
+#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
+#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver 
should claim the interrupt */
+#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */
+#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
+#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
+#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
+#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
+
+/* PBA ECC Register */
+#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */
+#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */
+
+/*
+ * This defines the bits that are set in the Interrupt Mask
+ * Set/Read Register.  Each bit is documented below:
+ *   o RXT0   = Receiver Timer Interrupt (ring 0)
+ *   o TXDW   = Transmit Descriptor Written Back
+ *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
+ *   o RXSEQ  = Receive Sequence Error
+ *   o LSC    = Link Status Change
+ */
+#define IMS_ENABLE_MASK ( \
+    E1000_IMS_RXT0   |    \
+    E1000_IMS_TXDW   |    \
+    E1000_IMS_RXDMT0 |    \
+    E1000_IMS_RXSEQ  |    \
+    E1000_IMS_LSC)
+
+/* Interrupt Mask Set */
+#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back 
*/
+#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
+#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
+#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
+#define E1000_IMS_RXQ0      E1000_ICR_RXQ0      /* Rx Queue 0 Interrupt */
+#define E1000_IMS_RXQ1      E1000_ICR_RXQ1      /* Rx Queue 1 Interrupt */
+#define E1000_IMS_TXQ0      E1000_ICR_TXQ0      /* Tx Queue 0 Interrupt */
+#define E1000_IMS_TXQ1      E1000_ICR_TXQ1      /* Tx Queue 1 Interrupt */
+#define E1000_IMS_OTHER     E1000_ICR_OTHER     /* Other Interrupts */
+
+/* Interrupt Cause Set */
+#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
+#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
+#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
+
+/* Transmit Descriptor Control */
+#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
+/* Enable the counting of desc. still to be processed. */
+#define E1000_TXDCTL_COUNT_DESC 0x00400000
+
+/* Flow Control Constants */
+#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
+#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
+#define FLOW_CONTROL_TYPE         0x8808
+
+/* 802.1q VLAN Packet Size */
+#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
+
+/* Receive Address */
+/*
+ * Number of high/low register pairs in the RAR. The RAR (Receive Address
+ * Registers) holds the directed and multicast addresses that we monitor.
+ * Technically, we have 16 spots.  However, we reserve one of these spots
+ * (RAR[15]) for our directed address used by controllers with
+ * manageability enabled, allowing us room for 15 multicast addresses.
+ */
+#define E1000_RAR_ENTRIES     15
+#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
+
+/* Error Codes */
+#define E1000_ERR_NVM      1
+#define E1000_ERR_PHY      2
+#define E1000_ERR_CONFIG   3
+#define E1000_ERR_PARAM    4
+#define E1000_ERR_MAC_INIT 5
+#define E1000_ERR_PHY_TYPE 6
+#define E1000_ERR_RESET   9
+#define E1000_ERR_MASTER_REQUESTS_PENDING 10
+#define E1000_ERR_HOST_INTERFACE_COMMAND 11
+#define E1000_BLK_PHY_RESET   12
+#define E1000_ERR_SWFW_SYNC 13
+#define E1000_NOT_IMPLEMENTED 14
+
+/* Loop limit on how long we wait for auto-negotiation to complete */
+#define FIBER_LINK_UP_LIMIT               50
+#define COPPER_LINK_UP_LIMIT              10
+#define PHY_AUTO_NEG_LIMIT                45
+#define PHY_FORCE_LIMIT                   20
+/* Number of 100 microseconds we wait for PCI Express master disable */
+#define MASTER_DISABLE_TIMEOUT      800
+/* Number of milliseconds we wait for PHY configuration done after MAC reset */
+#define PHY_CFG_TIMEOUT             100
+/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
+#define MDIO_OWNERSHIP_TIMEOUT      10
+/* Number of milliseconds for NVM auto read done after MAC reset. */
+#define AUTO_READ_DONE_TIMEOUT      10
+
+/* Flow Control */
+#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+
+/* Transmit Configuration Word */
+#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
+#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
+#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+
+/* Receive Configuration Word */
+#define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
+#define E1000_RXCW_C          0x20000000        /* Receive config */
+#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
+
+/* PCI Express Control */
+#define E1000_GCR_RXD_NO_SNOOP          0x00000001
+#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
+#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
+#define E1000_GCR_TXD_NO_SNOOP          0x00000008
+#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
+#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
+
+#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
+                          E1000_GCR_RXDSCW_NO_SNOOP      | \
+                          E1000_GCR_RXDSCR_NO_SNOOP      | \
+                          E1000_GCR_TXD_NO_SNOOP         | \
+                          E1000_GCR_TXDSCW_NO_SNOOP      | \
+                          E1000_GCR_TXDSCR_NO_SNOOP)
+
+/* PHY Control Register */
+#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
+#define MII_CR_POWER_DOWN       0x0800  /* Power down */
+#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
+#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_1000       0x0040
+#define MII_CR_SPEED_100        0x2000
+#define MII_CR_SPEED_10         0x0000
+
+/* PHY Status Register */
+#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
+
+/* Autoneg Advertisement Register */
+#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
+#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
+#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
+
+/* Link Partner Ability Register (Base Page) */
+#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
+
+/* Autoneg Expansion Register */
+#define NWAY_ER_LP_NWAY_CAPS     0x0001 /* LP has Auto Neg Capability */
+
+/* 1000BASE-T Control Register */
+#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
+                                       /* 0=DTE device */
+#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
+                                       /* 0=Configure PHY as Slave */
+#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value 
*/
+                                       /* 0=Automatic Master/Slave config */
+
+/* 1000BASE-T Status Register */
+#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
+
+
+/* PHY 1000 MII Register/Bit Definitions */
+/* PHY Registers defined by IEEE */
+#define PHY_CONTROL      0x00 /* Control Register */
+#define PHY_STATUS       0x01 /* Status Register */
+#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
+#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
+#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
+#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
+
+/* NVM Control */
+#define E1000_EECD_SK        0x00000001 /* NVM Clock */
+#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
+#define E1000_EECD_DI        0x00000004 /* NVM Data In */
+#define E1000_EECD_DO        0x00000008 /* NVM Data Out */
+#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
+#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
+#define E1000_EECD_PRES      0x00000100 /* NVM Present */
+#define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
+/* NVM Addressing bits based on type (0-small, 1-large) */
+#define E1000_EECD_ADDR_BITS 0x00000400
+#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
+#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
+#define E1000_EECD_SIZE_EX_SHIFT     11
+#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
+#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
+#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
+
+#define E1000_NVM_RW_REG_DATA   16   /* Offset to data in NVM read/write 
registers */
+#define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
+#define E1000_NVM_RW_REG_START  1    /* Start operation */
+#define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
+#define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
+#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
+#define E1000_FLASH_UPDATES  2000
+
+/* NVM Word Offsets */
+#define NVM_ID_LED_SETTINGS        0x0004
+#define NVM_INIT_CONTROL2_REG      0x000F
+#define NVM_INIT_CONTROL3_PORT_B   0x0014
+#define NVM_INIT_3GIO_3            0x001A
+#define NVM_INIT_CONTROL3_PORT_A   0x0024
+#define NVM_CFG                    0x0012
+#define NVM_ALT_MAC_ADDR_PTR       0x0037
+#define NVM_CHECKSUM_REG           0x003F
+
+#define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
+#define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
+
+/* Mask bits for fields in Word 0x0f of the NVM */
+#define NVM_WORD0F_PAUSE_MASK       0x3000
+#define NVM_WORD0F_PAUSE            0x1000
+#define NVM_WORD0F_ASM_DIR          0x2000
+
+/* Mask bits for fields in Word 0x1a of the NVM */
+#define NVM_WORD1A_ASPM_MASK  0x000C
+
+/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
+#define NVM_SUM                    0xBABA
+
+/* PBA (printed board assembly) number words */
+#define NVM_PBA_OFFSET_0           8
+#define NVM_PBA_OFFSET_1           9
+
+#define NVM_WORD_SIZE_BASE_SHIFT   6
+
+/* NVM Commands - SPI */
+#define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
+#define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
+#define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
+#define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
+#define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
+#define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
+
+/* SPI NVM Status Register */
+#define NVM_STATUS_RDY_SPI         0x01
+
+/* Word definitions for ID LED Settings */
+#define ID_LED_RESERVED_0000 0x0000
+#define ID_LED_RESERVED_FFFF 0xFFFF
+#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
+                             (ID_LED_OFF1_OFF2 <<  8) | \
+                             (ID_LED_DEF1_DEF2 <<  4) | \
+                             (ID_LED_DEF1_DEF2))
+#define ID_LED_DEF1_DEF2     0x1
+#define ID_LED_DEF1_ON2      0x2
+#define ID_LED_DEF1_OFF2     0x3
+#define ID_LED_ON1_DEF2      0x4
+#define ID_LED_ON1_ON2       0x5
+#define ID_LED_ON1_OFF2      0x6
+#define ID_LED_OFF1_DEF2     0x7
+#define ID_LED_OFF1_ON2      0x8
+#define ID_LED_OFF1_OFF2     0x9
+
+#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
+#define IGP_ACTIVITY_LED_ENABLE 0x0300
+#define IGP_LED3_MODE           0x07000000
+
+/* PCI/PCI-X/PCI-EX Config space */
+#define PCI_HEADER_TYPE_REGISTER     0x0E
+#define PCIE_LINK_STATUS             0x12
+
+#define PCI_HEADER_TYPE_MULTIFUNC    0x80
+#define PCIE_LINK_WIDTH_MASK         0x3F0
+#define PCIE_LINK_WIDTH_SHIFT        4
+
+#define PHY_REVISION_MASK      0xFFFFFFF0
+#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_MULTI_PAGE_REG 0xF
+
+/* Bit definitions for valid PHY IDs. */
+/*
+ * I = Integrated
+ * E = External
+ */
+#define M88E1000_E_PHY_ID    0x01410C50
+#define M88E1000_I_PHY_ID    0x01410C30
+#define M88E1011_I_PHY_ID    0x01410C20
+#define IGP01E1000_I_PHY_ID  0x02A80380
+#define M88E1111_I_PHY_ID    0x01410CC0
+#define GG82563_E_PHY_ID     0x01410CA0
+#define IGP03E1000_E_PHY_ID  0x02A80390
+#define IFE_E_PHY_ID         0x02A80330
+#define IFE_PLUS_E_PHY_ID    0x02A80320
+#define IFE_C_E_PHY_ID       0x02A80310
+#define BME1000_E_PHY_ID     0x01410CB0
+#define BME1000_E_PHY_ID_R2  0x01410CB1
+
+/* M88E1000 Specific Registers */
+#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
+#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
+#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
+
+#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
+#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
+
+/* M88E1000 PHY Specific Control Register */
+#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled 
*/
+#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 
*/
+                                              /* Manual MDI configuration */
+#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
+/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define M88E1000_PSCR_AUTO_X_1000T     0x0040
+/* Auto crossover enabled all speeds */
+#define M88E1000_PSCR_AUTO_X_MODE      0x0060
+/*
+ * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
+ * 0=Normal 10BASE-T Rx Threshold
+ */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
+
+/* M88E1000 PHY Specific Status Register */
+#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
+#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
+#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
+/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
+#define M88E1000_PSSR_CABLE_LENGTH       0x0380
+#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
+#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
+
+#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
+
+/*
+ * Number of times we will attempt to autonegotiate before downshifting if we
+ * are the master
+ */
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
+/*
+ * Number of times we will attempt to autonegotiate before downshifting if we
+ * are the slave
+ */
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
+#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
+
+/* M88EC018 Rev 2 specific DownShift settings */
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
+
+/* BME1000 PHY Specific Control Register */
+#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
+
+
+#define PHY_PAGE_SHIFT 5
+#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
+                           ((reg) & MAX_PHY_REG_ADDRESS))
+
+/*
+ * Bits...
+ * 15-5: page
+ * 4-0: register offset
+ */
+#define GG82563_PAGE_SHIFT        5
+#define GG82563_REG(page, reg)    \
+       (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
+#define GG82563_MIN_ALT_REG       30
+
+/* GG82563 Specific Registers */
+#define GG82563_PHY_SPEC_CTRL           \
+       GG82563_REG(0, 16) /* PHY Specific Control */
+#define GG82563_PHY_PAGE_SELECT         \
+       GG82563_REG(0, 22) /* Page Select */
+#define GG82563_PHY_SPEC_CTRL_2         \
+       GG82563_REG(0, 26) /* PHY Specific Control 2 */
+#define GG82563_PHY_PAGE_SELECT_ALT     \
+       GG82563_REG(0, 29) /* Alternate Page Select */
+
+#define GG82563_PHY_MAC_SPEC_CTRL       \
+       GG82563_REG(2, 21) /* MAC Specific Control Register */
+
+#define GG82563_PHY_DSP_DISTANCE    \
+       GG82563_REG(5, 26) /* DSP Distance */
+
+/* Page 193 - Port Control Registers */
+#define GG82563_PHY_KMRN_MODE_CTRL   \
+       GG82563_REG(193, 16) /* Kumeran Mode Control */
+#define GG82563_PHY_PWR_MGMT_CTRL       \
+       GG82563_REG(193, 20) /* Power Management Control */
+
+/* Page 194 - KMRN Registers */
+#define GG82563_PHY_INBAND_CTRL         \
+       GG82563_REG(194, 18) /* Inband Control */
+
+/* MDI Control */
+#define E1000_MDIC_REG_SHIFT 16
+#define E1000_MDIC_PHY_SHIFT 21
+#define E1000_MDIC_OP_WRITE  0x04000000
+#define E1000_MDIC_OP_READ   0x08000000
+#define E1000_MDIC_READY     0x10000000
+#define E1000_MDIC_ERROR     0x40000000
+
+/* SerDes Control */
+#define E1000_GEN_POLL_TIMEOUT          640
+
+#endif /* _E1000_DEFINES_H_ */
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/e1000.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/e1000.h        Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,567 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/* Linux PRO/1000 Ethernet Driver main header file */
+
+#ifndef _E1000_H_
+#define _E1000_H_
+
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <linux/io.h>
+#include <linux/netdevice.h>
+
+#include "e1000_compat.h"
+#include "hw.h"
+
+struct e1000_info;
+
+#define e_printk(level, adapter, format, arg...) \
+       printk(level "%s: " format, \
+              adapter->netdev->name, ## arg)
+
+#ifdef DEBUG
+#define e_dbg(format, arg...) \
+       e_printk(KERN_DEBUG , adapter, format, ## arg)
+#else
+#define e_dbg(format, arg...) do { (void)(adapter); } while (0)
+#endif
+
+#define e_err(format, arg...) \
+       e_printk(KERN_ERR, adapter, format, ## arg)
+#define e_info(format, arg...) \
+       e_printk(KERN_INFO, adapter, format, ## arg)
+#define e_warn(format, arg...) \
+       e_printk(KERN_WARNING, adapter, format, ## arg)
+#define e_notice(format, arg...) \
+       e_printk(KERN_NOTICE, adapter, format, ## arg)
+
+
+/* Interrupt modes, as used by the IntMode paramter */
+#define E1000E_INT_MODE_LEGACY         0
+#define E1000E_INT_MODE_MSI            1
+#define E1000E_INT_MODE_MSIX           2
+
+/* Tx/Rx descriptor defines */
+#define E1000_DEFAULT_TXD              256
+#define E1000_MAX_TXD                  4096
+#define E1000_MIN_TXD                  64
+
+#define E1000_DEFAULT_RXD              256
+#define E1000_MAX_RXD                  4096
+#define E1000_MIN_RXD                  64
+
+#define E1000_MIN_ITR_USECS            10 /* 100000 irq/sec */
+#define E1000_MAX_ITR_USECS            10000 /* 100    irq/sec */
+
+/* Early Receive defines */
+#define E1000_ERT_2048                 0x100
+
+#define E1000_FC_PAUSE_TIME            0x0680 /* 858 usec */
+
+/* How many Tx Descriptors do we need to call netif_wake_queue ? */
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
+#define E1000_RX_BUFFER_WRITE          16 /* Must be power of 2 */
+
+#define AUTO_ALL_MODES                 0
+#define E1000_EEPROM_APME              0x0400
+
+#define E1000_MNG_VLAN_NONE            (-1)
+
+/* Number of packet split data buffers (not including the header buffer) */
+#define PS_PAGE_BUFFERS                        (MAX_PS_BUFFERS - 1)
+
+enum e1000_boards {
+       board_82571,
+       board_82572,
+       board_82573,
+       board_82574,
+       board_80003es2lan,
+       board_ich8lan,
+       board_ich9lan,
+       board_ich10lan,
+};
+
+struct e1000_queue_stats {
+       u64 packets;
+       u64 bytes;
+};
+
+struct e1000_ps_page {
+       struct page *page;
+       u64 dma; /* must be u64 - written to hw */
+};
+
+/*
+ * wrappers around a pointer to a socket buffer,
+ * so a DMA handle can be stored along with the buffer
+ */
+struct e1000_buffer {
+       dma_addr_t dma;
+       struct sk_buff *skb;
+       union {
+               /* Tx */
+               struct {
+                       unsigned long time_stamp;
+                       u16 length;
+                       u16 next_to_watch;
+               };
+               /* Rx */
+               /* arrays of page information for packet split */
+               struct e1000_ps_page *ps_pages;
+       };
+       struct page *page;
+};
+
+struct e1000_ring {
+       void *desc;                     /* pointer to ring memory  */
+       dma_addr_t dma;                 /* phys address of ring    */
+       unsigned int size;              /* length of ring in bytes */
+       unsigned int count;             /* number of desc. in ring */
+
+       u16 next_to_use;
+       u16 next_to_clean;
+
+       u16 head;
+       u16 tail;
+
+       /* array of buffer information structs */
+       struct e1000_buffer *buffer_info;
+
+       char name[IFNAMSIZ + 5];
+       u32 ims_val;
+       u32 itr_val;
+       u16 itr_register;
+       int set_itr;
+
+       struct sk_buff *rx_skb_top;
+
+       struct e1000_queue_stats stats;
+};
+
+/* PHY register snapshot values */
+struct e1000_phy_regs {
+       u16 bmcr;               /* basic mode control register    */
+       u16 bmsr;               /* basic mode status register     */
+       u16 advertise;          /* auto-negotiation advertisement */
+       u16 lpa;                /* link partner ability register  */
+       u16 expansion;          /* auto-negotiation expansion reg */
+       u16 ctrl1000;           /* 1000BASE-T control register    */
+       u16 stat1000;           /* 1000BASE-T status register     */
+       u16 estatus;            /* extended status register       */
+};
+
+/* board specific private data structure */
+struct e1000_adapter {
+       struct timer_list watchdog_timer;
+       struct timer_list phy_info_timer;
+       struct timer_list blink_timer;
+
+       struct work_struct reset_task;
+       struct work_struct watchdog_task;
+
+       const struct e1000_info *ei;
+
+       struct vlan_group *vlgrp;
+       u32 bd_number;
+       u32 rx_buffer_len;
+       u16 mng_vlan_id;
+       u16 link_speed;
+       u16 link_duplex;
+
+       spinlock_t tx_queue_lock; /* prevent concurrent tail updates */
+
+       /* track device up/down/testing state */
+       unsigned long state;
+
+       /* Interrupt Throttle Rate */
+       u32 itr;
+       u32 itr_setting;
+       u16 tx_itr;
+       u16 rx_itr;
+
+       /*
+        * Tx
+        */
+       struct e1000_ring *tx_ring /* One per active queue */
+                                               ____cacheline_aligned_in_smp;
+
+       unsigned long tx_queue_len;
+       unsigned int restart_queue;
+       u32 txd_cmd;
+
+       bool detect_tx_hung;
+       u8 tx_timeout_factor;
+
+       u32 tx_int_delay;
+       u32 tx_abs_int_delay;
+
+       unsigned int total_tx_bytes;
+       unsigned int total_tx_packets;
+       unsigned int total_rx_bytes;
+       unsigned int total_rx_packets;
+
+       /* Tx stats */
+       u64 tpt_old;
+       u64 colc_old;
+       u32 gotc;
+       u64 gotc_old;
+       u32 tx_timeout_count;
+       u32 tx_fifo_head;
+       u32 tx_head_addr;
+       u32 tx_fifo_size;
+       u32 tx_dma_failed;
+
+       /*
+        * Rx
+        */
+       bool (*clean_rx) (struct e1000_adapter *adapter,
+                         int *work_done, int work_to_do)
+                                               ____cacheline_aligned_in_smp;
+       void (*alloc_rx_buf) (struct e1000_adapter *adapter,
+                             int cleaned_count);
+       struct e1000_ring *rx_ring;
+
+       u32 rx_int_delay;
+       u32 rx_abs_int_delay;
+
+       /* Rx stats */
+       u64 hw_csum_err;
+       u64 hw_csum_good;
+       u64 rx_hdr_split;
+       u32 gorc;
+       u64 gorc_old;
+       u32 alloc_rx_buff_failed;
+       u32 rx_dma_failed;
+
+       unsigned int rx_ps_pages;
+       u16 rx_ps_bsize0;
+       u32 max_frame_size;
+       u32 min_frame_size;
+
+       /* OS defined structs */
+       struct net_device *netdev;
+       struct pci_dev *pdev;
+       struct net_device_stats net_stats;
+       spinlock_t stats_lock;      /* prevent concurrent stats updates */
+
+       /* structs defined in e1000_hw.h */
+       struct e1000_hw hw;
+
+       struct e1000_hw_stats stats;
+       struct e1000_phy_info phy_info;
+       struct e1000_phy_stats phy_stats;
+
+       /* Snapshot of PHY registers */
+       struct e1000_phy_regs phy_regs;
+
+       struct e1000_ring test_tx_ring;
+       struct e1000_ring test_rx_ring;
+       u32 test_icr;
+
+       u32 msg_enable;
+       struct msix_entry *msix_entries;
+       int int_mode;
+       u32 eiac_mask;
+
+       u32 eeprom_wol;
+       u32 wol;
+       u32 pba;
+
+       bool fc_autoneg;
+
+       unsigned long led_status;
+
+       unsigned int flags;
+};
+
+struct e1000_info {
+       enum e1000_mac_type     mac;
+       unsigned int            flags;
+       u32                     pba;
+       s32                     (*get_variants)(struct e1000_adapter *);
+       struct e1000_mac_operations *mac_ops;
+       struct e1000_phy_operations *phy_ops;
+       struct e1000_nvm_operations *nvm_ops;
+};
+
+/* hardware capability, feature, and workaround flags */
+#define FLAG_HAS_AMT                      (1 << 0)
+#define FLAG_HAS_FLASH                    (1 << 1)
+#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
+#define FLAG_HAS_WOL                      (1 << 3)
+#define FLAG_HAS_ERT                      (1 << 4)
+#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
+#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
+#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
+#define FLAG_READ_ONLY_NVM                (1 << 8)
+#define FLAG_IS_ICH                       (1 << 9)
+#define FLAG_HAS_MSIX                     (1 << 10)
+#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
+#define FLAG_IS_QUAD_PORT_A               (1 << 12)
+#define FLAG_IS_QUAD_PORT                 (1 << 13)
+#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN   (1 << 14)
+#define FLAG_APME_IN_WUC                  (1 << 15)
+#define FLAG_APME_IN_CTRL3                (1 << 16)
+#define FLAG_APME_CHECK_PORT_B            (1 << 17)
+#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
+#define FLAG_NO_WAKE_UCAST                (1 << 19)
+#define FLAG_MNG_PT_ENABLED               (1 << 20)
+#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
+#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
+#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
+#define FLAG_RX_NEEDS_RESTART             (1 << 24)
+#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
+#define FLAG_SMART_POWER_DOWN             (1 << 26)
+#define FLAG_MSI_ENABLED                  (1 << 27)
+#define FLAG_RX_CSUM_ENABLED              (1 << 28)
+#define FLAG_TSO_FORCE                    (1 << 29)
+#define FLAG_MSI_TEST_FAILED              (1 << 30)
+#define FLAG_RX_RESTART_NOW               (1 << 31)
+
+#define E1000_RX_DESC_PS(R, i)     \
+       (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
+#define E1000_GET_DESC(R, i, type)     (&(((struct type *)((R).desc))[i]))
+#define E1000_RX_DESC(R, i)            E1000_GET_DESC(R, i, e1000_rx_desc)
+#define E1000_TX_DESC(R, i)            E1000_GET_DESC(R, i, e1000_tx_desc)
+#define E1000_CONTEXT_DESC(R, i)       E1000_GET_DESC(R, i, e1000_context_desc)
+
+enum e1000_state_t {
+       __E1000_TESTING,
+       __E1000_RESETTING,
+       __E1000_DOWN
+};
+
+enum latency_range {
+       lowest_latency = 0,
+       low_latency = 1,
+       bulk_latency = 2,
+       latency_invalid = 255
+};
+
+extern char e1000e_driver_name[];
+extern const char e1000e_driver_version[];
+
+extern void e1000e_check_options(struct e1000_adapter *adapter);
+extern void e1000e_set_ethtool_ops(struct net_device *netdev);
+
+extern int e1000e_up(struct e1000_adapter *adapter);
+extern void e1000e_down(struct e1000_adapter *adapter);
+extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
+extern void e1000e_reset(struct e1000_adapter *adapter);
+extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
+extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
+extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
+extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
+extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
+extern void e1000e_update_stats(struct e1000_adapter *adapter);
+extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
+extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
+
+extern unsigned int copybreak;
+
+extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
+
+extern struct e1000_info e1000_82571_info;
+extern struct e1000_info e1000_82572_info;
+extern struct e1000_info e1000_82573_info;
+extern struct e1000_info e1000_82574_info;
+extern struct e1000_info e1000_ich8_info;
+extern struct e1000_info e1000_ich9_info;
+extern struct e1000_info e1000_ich10_info;
+extern struct e1000_info e1000_es2_info;
+
+extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
+
+extern s32  e1000e_commit_phy(struct e1000_hw *hw);
+
+extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
+
+extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
+extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
+
+extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
+extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
+                                                bool state);
+extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
+extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
+extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
+
+extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
+extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
+extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
+extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
+extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
+extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
+extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
+extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 
u16 *duplex);
+extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 
*speed, u16 *duplex);
+extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
+extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
+extern s32 e1000e_id_led_init(struct e1000_hw *hw);
+extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
+extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
+extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
+extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
+extern s32 e1000e_setup_link(struct e1000_hw *hw);
+extern void e1000e_clear_vfta(struct e1000_hw *hw);
+extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
+extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
+                                              u8 *mc_addr_list,
+                                              u32 mc_addr_count,
+                                              u32 rar_used_count,
+                                              u32 rar_count);
+extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
+extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
+extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
+extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
+extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
+extern void e1000e_config_collision_dist(struct e1000_hw *hw);
+extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
+extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
+extern s32 e1000e_blink_led(struct e1000_hw *hw);
+extern void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
+extern void e1000e_reset_adaptive(struct e1000_hw *hw);
+extern void e1000e_update_adaptive(struct e1000_hw *hw);
+
+extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
+extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
+extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
+extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
+extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
+extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
+extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
+extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
+extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
+extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
+extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
+extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
+extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
+extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
+extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
+extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
+extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
+extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
+extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 
*phy_ctrl);
+extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
+extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
+extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
+                              u32 usec_interval, bool *success);
+extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
+extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 
*data);
+extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 
data);
+extern s32 e1000e_check_downshift(struct e1000_hw *hw);
+
+static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
+{
+       return hw->phy.ops.reset_phy(hw);
+}
+
+static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
+{
+       return hw->phy.ops.check_reset_block(hw);
+}
+
+static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
+{
+       return hw->phy.ops.read_phy_reg(hw, offset, data);
+}
+
+static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
+{
+       return hw->phy.ops.write_phy_reg(hw, offset, data);
+}
+
+static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
+{
+       return hw->phy.ops.get_cable_length(hw);
+}
+
+extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
+extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, 
u16 *data);
+extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
+extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
+extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, 
u16 *data);
+extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
+extern void e1000e_release_nvm(struct e1000_hw *hw);
+extern void e1000e_reload_nvm(struct e1000_hw *hw);
+extern s32 e1000e_read_mac_addr(struct e1000_hw *hw);
+
+static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
+{
+       return hw->nvm.ops.validate_nvm(hw);
+}
+
+static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
+{
+       return hw->nvm.ops.update_nvm(hw);
+}
+
+static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 
u16 *data)
+{
+       return hw->nvm.ops.read_nvm(hw, offset, words, data);
+}
+
+static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 
u16 *data)
+{
+       return hw->nvm.ops.write_nvm(hw, offset, words, data);
+}
+
+static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
+{
+       return hw->phy.ops.get_phy_info(hw);
+}
+
+static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
+{
+       return hw->mac.ops.check_mng_mode(hw);
+}
+
+extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
+extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
+extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 
length);
+
+static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
+{
+       return readl(hw->hw_addr + reg);
+}
+
+static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
+{
+       writel(val, hw->hw_addr + reg);
+}
+
+#endif /* _E1000_H_ */
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/e1000_compat.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/e1000_compat.h Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,69 @@
+#ifndef __E1000E_COMPAT_H__
+#define __E1000E_COMPAT_H__
+
+#include <linux/if_vlan.h>
+#include <linux/pci.h>
+
+typedef unsigned int bool;
+
+#define ETH_FCS_LEN               4
+
+static inline struct net_device *vlan_group_get_device(struct vlan_group *vg,
+                                                      int vlan_id)
+{
+       return vg->vlan_devices[vlan_id];
+}
+
+static inline void vlan_group_set_device(struct vlan_group *vg, int vlan_id,
+                                        struct net_device *dev)
+{
+       vg->vlan_devices[vlan_id] = NULL;
+}
+/* generic boolean compatibility */
+#define true 1
+#define false 0
+
+/*
+ * backport csum_unfold and datatypes from 2.6.25
+ */
+typedef __u16 __bitwise __sum16;
+typedef __u32 __bitwise __wsum;
+
+static inline __wsum csum_unfold(__sum16 n)
+{
+    return (__force __wsum)n;
+};
+
+#ifndef CHECKSUM_PARTIAL
+#define CHECKSUM_PARTIAL CHECKSUM_HW
+#define CHECKSUM_COMPLETE CHECKSUM_HW
+#endif
+
+#define skb_tail_pointer(skb) skb->tail
+#define skb_copy_to_linear_data_offset(skb, offset, from, len) \
+    memcpy(skb->data + offset, from, len)
+
+
+static inline int pci_channel_offline(struct pci_dev *pdev)
+{
+    return (pdev->error_state != pci_channel_io_normal);
+}
+#ifndef round_jiffies
+#define round_jiffies(x) x
+#endif
+
+#define tcp_hdr(skb) (skb->h.th)
+#define tcp_hdrlen(skb) (skb->h.th->doff << 2)
+#define skb_transport_offset(skb) (skb->h.raw - skb->data)
+#define skb_transport_header(skb) (skb->h.raw)
+#define ipv6_hdr(skb) (skb->nh.ipv6h)
+#define ip_hdr(skb) (skb->nh.iph)
+#define skb_network_offset(skb) (skb->nh.raw - skb->data)
+
+#ifndef PCI_VDEVICE
+#define PCI_VDEVICE(ven, dev)        \
+    PCI_VENDOR_ID_##ven, (dev),  \
+    PCI_ANY_ID, PCI_ANY_ID, 0, 0
+#endif
+
+#endif 
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/es2lan.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/es2lan.c       Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,1310 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/*
+ * 80003ES2LAN Gigabit Ethernet Controller (Copper)
+ * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
+ */
+
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include "e1000.h"
+
+#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL      0x00
+#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL       0x02
+#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL        0x10
+#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE         0x1F
+
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS   0x0008
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS   0x0800
+#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING  0x0010
+
+#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
+#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT  0x0000
+#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE                 0x2000
+
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
+#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN       0x00010000
+
+#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN      0x8
+#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN    0x9
+
+/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disab. */
+#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
+#define GG82563_PSCR_CROSSOVER_MODE_MDI                 0x0000 /* 00=Manual 
MDI */
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
+
+/* PHY Specific Control Register 2 (Page 0, Register 26) */
+#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
+                                               /* 1=Reverse Auto-Negotiation */
+
+/* MAC Specific Control Register (Page 2, Register 21) */
+/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
+#define GG82563_MSCR_TX_CLK_MASK                0x0007
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
+#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
+#define GG82563_MSCR_TX_CLK_1000MBPS_25                 0x0007
+
+#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
+
+/* DSP Distance Register (Page 5, Register 26) */
+#define GG82563_DSPD_CABLE_LENGTH               0x0007 /* 0 = <50M
+                                                          1 = 50-80M
+                                                          2 = 80-110M
+                                                          3 = 110-140M
+                                                          4 = >140M */
+
+/* Kumeran Mode Control Register (Page 193, Register 16) */
+#define GG82563_KMCR_PASS_FALSE_CARRIER                 0x0800
+
+/* Max number of times Kumeran read/write should be validated */
+#define GG82563_MAX_KMRN_RETRY  0x5
+
+/* Power Management Control Register (Page 193, Register 20) */
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
+                                          /* 1=Enable SERDES Electrical Idle */
+
+/* In-Band Control Register (Page 194, Register 18) */
+#define GG82563_ICR_DIS_PADDING                         0x0010 /* Disable 
Padding */
+
+/*
+ * A table for the GG82563 cable length where the range is defined
+ * with a lower bound at "index" and the upper bound at
+ * "index + 5".
+ */
+static const u16 e1000_gg82563_cable_length_table[] =
+        { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
+
+static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
+static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
+static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
+static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
+static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
+static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
+static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
+
+/**
+ *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+
+       if (hw->phy.media_type != e1000_media_type_copper) {
+               phy->type       = e1000_phy_none;
+               return 0;
+       }
+
+       phy->addr               = 1;
+       phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+       phy->reset_delay_us      = 100;
+       phy->type               = e1000_phy_gg82563;
+
+       /* This can only be done after all function pointers are setup. */
+       ret_val = e1000e_get_phy_id(hw);
+
+       /* Verify phy id */
+       if (phy->id != GG82563_E_PHY_ID)
+               return -E1000_ERR_PHY;
+
+       return ret_val;
+}
+
+/**
+ *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       u32 eecd = er32(EECD);
+       u16 size;
+
+       nvm->opcode_bits        = 8;
+       nvm->delay_usec  = 1;
+       switch (nvm->override) {
+       case e1000_nvm_override_spi_large:
+               nvm->page_size    = 32;
+               nvm->address_bits = 16;
+               break;
+       case e1000_nvm_override_spi_small:
+               nvm->page_size    = 8;
+               nvm->address_bits = 8;
+               break;
+       default:
+               nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+               nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
+               break;
+       }
+
+       nvm->type = e1000_nvm_eeprom_spi;
+
+       size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
+                         E1000_EECD_SIZE_EX_SHIFT);
+
+       /*
+        * Added to a constant, "size" becomes the left-shift value
+        * for setting word_size.
+        */
+       size += NVM_WORD_SIZE_BASE_SHIFT;
+
+       /* EEPROM access above 16k is unsupported */
+       if (size > 14)
+               size = 14;
+       nvm->word_size  = 1 << size;
+
+       return 0;
+}
+
+/**
+ *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
+ *  @hw: pointer to the HW structure
+ *
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       struct e1000_mac_info *mac = &hw->mac;
+       struct e1000_mac_operations *func = &mac->ops;
+
+       /* Set media type */
+       switch (adapter->pdev->device) {
+       case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
+               hw->phy.media_type = e1000_media_type_internal_serdes;
+               break;
+       default:
+               hw->phy.media_type = e1000_media_type_copper;
+               break;
+       }
+
+       /* Set mta register count */
+       mac->mta_reg_count = 128;
+       /* Set rar entry count */
+       mac->rar_entry_count = E1000_RAR_ENTRIES;
+       /* Set if manageability features are enabled. */
+       mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
+
+       /* check for link */
+       switch (hw->phy.media_type) {
+       case e1000_media_type_copper:
+               func->setup_physical_interface = 
e1000_setup_copper_link_80003es2lan;
+               func->check_for_link = e1000e_check_for_copper_link;
+               break;
+       case e1000_media_type_fiber:
+               func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
+               func->check_for_link = e1000e_check_for_fiber_link;
+               break;
+       case e1000_media_type_internal_serdes:
+               func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
+               func->check_for_link = e1000e_check_for_serdes_link;
+               break;
+       default:
+               return -E1000_ERR_CONFIG;
+               break;
+       }
+
+       return 0;
+}
+
+static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       s32 rc;
+
+       rc = e1000_init_mac_params_80003es2lan(adapter);
+       if (rc)
+               return rc;
+
+       rc = e1000_init_nvm_params_80003es2lan(hw);
+       if (rc)
+               return rc;
+
+       rc = e1000_init_phy_params_80003es2lan(hw);
+       if (rc)
+               return rc;
+
+       return 0;
+}
+
+/**
+ *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  A wrapper to acquire access rights to the correct PHY.  This is a
+ *  function pointer entry point called by the api module.
+ **/
+static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
+{
+       u16 mask;
+
+       mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
+       mask |= E1000_SWFW_CSR_SM;
+
+       return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
+}
+
+/**
+ *  e1000_release_phy_80003es2lan - Release rights to access PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  A wrapper to release access rights to the correct PHY.  This is a
+ *  function pointer entry point called by the api module.
+ **/
+static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
+{
+       u16 mask;
+
+       mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
+       mask |= E1000_SWFW_CSR_SM;
+
+       e1000_release_swfw_sync_80003es2lan(hw, mask);
+}
+
+/**
+ *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the semaphore to access the EEPROM.  This is a function
+ *  pointer entry point called by the api module.
+ **/
+static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+
+       ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000e_acquire_nvm(hw);
+
+       if (ret_val)
+               e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
+ *  @hw: pointer to the HW structure
+ *
+ *  Release the semaphore used to access the EEPROM.  This is a
+ *  function pointer entry point called by the api module.
+ **/
+static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
+{
+       e1000e_release_nvm(hw);
+       e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
+}
+
+/**
+ *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
+ *  @hw: pointer to the HW structure
+ *  @mask: specifies which semaphore to acquire
+ *
+ *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
+ *  will also specify which port we're acquiring the lock for.
+ **/
+static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
+{
+       u32 swfw_sync;
+       u32 swmask = mask;
+       u32 fwmask = mask << 16;
+       s32 i = 0;
+       s32 timeout = 200;
+
+       while (i < timeout) {
+               if (e1000e_get_hw_semaphore(hw))
+                       return -E1000_ERR_SWFW_SYNC;
+
+               swfw_sync = er32(SW_FW_SYNC);
+               if (!(swfw_sync & (fwmask | swmask)))
+                       break;
+
+               /*
+                * Firmware currently using resource (fwmask)
+                * or other software thread using resource (swmask)
+                */
+               e1000e_put_hw_semaphore(hw);
+               mdelay(5);
+               i++;
+       }
+
+       if (i == timeout) {
+               hw_dbg(hw,
+                      "Driver can't access resource, SW_FW_SYNC timeout.\n");
+               return -E1000_ERR_SWFW_SYNC;
+       }
+
+       swfw_sync |= swmask;
+       ew32(SW_FW_SYNC, swfw_sync);
+
+       e1000e_put_hw_semaphore(hw);
+
+       return 0;
+}
+
+/**
+ *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
+ *  @hw: pointer to the HW structure
+ *  @mask: specifies which semaphore to acquire
+ *
+ *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
+ *  will also specify which port we're releasing the lock for.
+ **/
+static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
+{
+       u32 swfw_sync;
+
+       while (e1000e_get_hw_semaphore(hw) != 0);
+       /* Empty */
+
+       swfw_sync = er32(SW_FW_SYNC);
+       swfw_sync &= ~mask;
+       ew32(SW_FW_SYNC, swfw_sync);
+
+       e1000e_put_hw_semaphore(hw);
+}
+
+/**
+ *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of the register to read
+ *  @data: pointer to the data returned from the operation
+ *
+ *  Read the GG82563 PHY register.  This is a function pointer entry
+ *  point called by the api module.
+ **/
+static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
+                                                 u32 offset, u16 *data)
+{
+       s32 ret_val;
+       u32 page_select;
+       u16 temp;
+
+       ret_val = e1000_acquire_phy_80003es2lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       /* Select Configuration Page */
+       if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
+               page_select = GG82563_PHY_PAGE_SELECT;
+       } else {
+               /*
+                * Use Alternative Page Select register to access
+                * registers 30 and 31
+                */
+               page_select = GG82563_PHY_PAGE_SELECT_ALT;
+       }
+
+       temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
+       ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
+       if (ret_val) {
+               e1000_release_phy_80003es2lan(hw);
+               return ret_val;
+       }
+
+       /*
+        * The "ready" bit in the MDIC register may be incorrectly set
+        * before the device has completed the "Page Select" MDI
+        * transaction.  So we wait 200us after each MDI command...
+        */
+       udelay(200);
+
+       /* ...and verify the command was successful. */
+       ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
+
+       if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
+               ret_val = -E1000_ERR_PHY;
+               e1000_release_phy_80003es2lan(hw);
+               return ret_val;
+       }
+
+       udelay(200);
+
+       ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+                                          data);
+
+       udelay(200);
+       e1000_release_phy_80003es2lan(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of the register to read
+ *  @data: value to write to the register
+ *
+ *  Write to the GG82563 PHY register.  This is a function pointer entry
+ *  point called by the api module.
+ **/
+static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
+                                                  u32 offset, u16 data)
+{
+       s32 ret_val;
+       u32 page_select;
+       u16 temp;
+
+       ret_val = e1000_acquire_phy_80003es2lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       /* Select Configuration Page */
+       if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
+               page_select = GG82563_PHY_PAGE_SELECT;
+       } else {
+               /*
+                * Use Alternative Page Select register to access
+                * registers 30 and 31
+                */
+               page_select = GG82563_PHY_PAGE_SELECT_ALT;
+       }
+
+       temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
+       ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
+       if (ret_val) {
+               e1000_release_phy_80003es2lan(hw);
+               return ret_val;
+       }
+
+
+       /*
+        * The "ready" bit in the MDIC register may be incorrectly set
+        * before the device has completed the "Page Select" MDI
+        * transaction.  So we wait 200us after each MDI command...
+        */
+       udelay(200);
+
+       /* ...and verify the command was successful. */
+       ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
+
+       if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
+               e1000_release_phy_80003es2lan(hw);
+               return -E1000_ERR_PHY;
+       }
+
+       udelay(200);
+
+       ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+                                           data);
+
+       udelay(200);
+       e1000_release_phy_80003es2lan(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: offset of the register to read
+ *  @words: number of words to write
+ *  @data: buffer of data to write to the NVM
+ *
+ *  Write "words" of data to the ESB2 NVM.  This is a function
+ *  pointer entry point called by the api module.
+ **/
+static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
+                                      u16 words, u16 *data)
+{
+       return e1000e_write_nvm_spi(hw, offset, words, data);
+}
+
+/**
+ *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
+ *  @hw: pointer to the HW structure
+ *
+ *  Wait a specific amount of time for manageability processes to complete.
+ *  This is a function pointer entry point called by the phy module.
+ **/
+static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
+{
+       s32 timeout = PHY_CFG_TIMEOUT;
+       u32 mask = E1000_NVM_CFG_DONE_PORT_0;
+
+       if (hw->bus.func == 1)
+               mask = E1000_NVM_CFG_DONE_PORT_1;
+
+       while (timeout) {
+               if (er32(EEMNGCTL) & mask)
+                       break;
+               msleep(1);
+               timeout--;
+       }
+       if (!timeout) {
+               hw_dbg(hw, "MNG configuration cycle has not completed.\n");
+               return -E1000_ERR_RESET;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
+ *  @hw: pointer to the HW structure
+ *
+ *  Force the speed and duplex settings onto the PHY.  This is a
+ *  function pointer entry point called by the phy module.
+ **/
+static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 phy_data;
+       bool link;
+
+       /*
+        * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
+        * forced whenever speed and duplex are forced.
+        */
+       ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
+       ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
+       if (ret_val)
+               return ret_val;
+
+       hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
+
+       ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
+
+       /* Reset the phy to commit changes. */
+       phy_data |= MII_CR_RESET;
+
+       ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
+       if (ret_val)
+               return ret_val;
+
+       udelay(1);
+
+       if (hw->phy.autoneg_wait_to_complete) {
+               hw_dbg(hw, "Waiting for forced speed/duplex link "
+                        "on GG82563 phy.\n");
+
+               ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+                                                    100000, &link);
+               if (ret_val)
+                       return ret_val;
+
+               if (!link) {
+                       /*
+                        * We didn't get link.
+                        * Reset the DSP and cross our fingers.
+                        */
+                       ret_val = e1000e_phy_reset_dsp(hw);
+                       if (ret_val)
+                               return ret_val;
+               }
+
+               /* Try once more */
+               ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+                                                    100000, &link);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * Resetting the phy means we need to verify the TX_CLK corresponds
+        * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
+        */
+       phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
+       if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
+               phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
+       else
+               phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
+
+       /*
+        * In addition, we must re-enable CRS on Tx for both half and full
+        * duplex.
+        */
+       phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+       ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_get_cable_length_80003es2lan - Set approximate cable length
+ *  @hw: pointer to the HW structure
+ *
+ *  Find the approximate cable length as measured by the GG82563 PHY.
+ *  This is a function pointer entry point called by the phy module.
+ **/
+static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 phy_data;
+       u16 index;
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       index = phy_data & GG82563_DSPD_CABLE_LENGTH;
+       phy->min_cable_length = e1000_gg82563_cable_length_table[index];
+       phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
+
+       phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
+
+       return 0;
+}
+
+/**
+ *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
+ *  @hw: pointer to the HW structure
+ *  @speed: pointer to speed buffer
+ *  @duplex: pointer to duplex buffer
+ *
+ *  Retrieve the current speed and duplex configuration.
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
+                                             u16 *duplex)
+{
+       s32 ret_val;
+
+       if (hw->phy.media_type == e1000_media_type_copper) {
+               ret_val = e1000e_get_speed_and_duplex_copper(hw,
+                                                                   speed,
+                                                                   duplex);
+               if (ret_val)
+                       return ret_val;
+               if (*speed == SPEED_1000)
+                       ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
+               else
+                       ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
+                                                             *duplex);
+       } else {
+               ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
+                                                                 speed,
+                                                                 duplex);
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
+ *  @hw: pointer to the HW structure
+ *
+ *  Perform a global reset to the ESB2 controller.
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       u32 icr;
+       s32 ret_val;
+
+       /*
+        * Prevent the PCI-E bus from sticking if there is no TLP connection
+        * on the last TLP read/write transaction when MAC is reset.
+        */
+       ret_val = e1000e_disable_pcie_master(hw);
+       if (ret_val)
+               hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+
+       hw_dbg(hw, "Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       ew32(RCTL, 0);
+       ew32(TCTL, E1000_TCTL_PSP);
+       e1e_flush();
+
+       msleep(10);
+
+       ctrl = er32(CTRL);
+
+       hw_dbg(hw, "Issuing a global reset to MAC\n");
+       ew32(CTRL, ctrl | E1000_CTRL_RST);
+
+       ret_val = e1000e_get_auto_rd_done(hw);
+       if (ret_val)
+               /* We don't want to continue accessing MAC registers. */
+               return ret_val;
+
+       /* Clear any pending interrupt events. */
+       ew32(IMC, 0xffffffff);
+       icr = er32(ICR);
+
+       return 0;
+}
+
+/**
+ *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
+ *  This is a function pointer entry point called by the api module.
+ **/
+static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 reg_data;
+       s32 ret_val;
+       u16 i;
+
+       e1000_initialize_hw_bits_80003es2lan(hw);
+
+       /* Initialize identification LED */
+       ret_val = e1000e_id_led_init(hw);
+       if (ret_val) {
+               hw_dbg(hw, "Error initializing identification LED\n");
+               return ret_val;
+       }
+
+       /* Disabling VLAN filtering */
+       hw_dbg(hw, "Initializing the IEEE VLAN\n");
+       e1000e_clear_vfta(hw);
+
+       /* Setup the receive address. */
+       e1000e_init_rx_addrs(hw, mac->rar_entry_count);
+
+       /* Zero out the Multicast HASH table */
+       hw_dbg(hw, "Zeroing the MTA\n");
+       for (i = 0; i < mac->mta_reg_count; i++)
+               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
+
+       /* Setup link and flow control */
+       ret_val = e1000e_setup_link(hw);
+
+       /* Set the transmit descriptor write-back policy */
+       reg_data = er32(TXDCTL(0));
+       reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                  E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+       ew32(TXDCTL(0), reg_data);
+
+       /* ...for both queues. */
+       reg_data = er32(TXDCTL(1));
+       reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
+                  E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+       ew32(TXDCTL(1), reg_data);
+
+       /* Enable retransmit on late collisions */
+       reg_data = er32(TCTL);
+       reg_data |= E1000_TCTL_RTLC;
+       ew32(TCTL, reg_data);
+
+       /* Configure Gigabit Carry Extend Padding */
+       reg_data = er32(TCTL_EXT);
+       reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
+       reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
+       ew32(TCTL_EXT, reg_data);
+
+       /* Configure Transmit Inter-Packet Gap */
+       reg_data = er32(TIPG);
+       reg_data &= ~E1000_TIPG_IPGT_MASK;
+       reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
+       ew32(TIPG, reg_data);
+
+       reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
+       reg_data &= ~0x00100000;
+       E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
+
+       /*
+        * Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000_clear_hw_cntrs_80003es2lan(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
+ *  @hw: pointer to the HW structure
+ *
+ *  Initializes required hardware-dependent bits needed for normal operation.
+ **/
+static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
+{
+       u32 reg;
+
+       /* Transmit Descriptor Control 0 */
+       reg = er32(TXDCTL(0));
+       reg |= (1 << 22);
+       ew32(TXDCTL(0), reg);
+
+       /* Transmit Descriptor Control 1 */
+       reg = er32(TXDCTL(1));
+       reg |= (1 << 22);
+       ew32(TXDCTL(1), reg);
+
+       /* Transmit Arbitration Control 0 */
+       reg = er32(TARC(0));
+       reg &= ~(0xF << 27); /* 30:27 */
+       if (hw->phy.media_type != e1000_media_type_copper)
+               reg &= ~(1 << 20);
+       ew32(TARC(0), reg);
+
+       /* Transmit Arbitration Control 1 */
+       reg = er32(TARC(1));
+       if (er32(TCTL) & E1000_TCTL_MULR)
+               reg &= ~(1 << 28);
+       else
+               reg |= (1 << 28);
+       ew32(TARC(1), reg);
+}
+
+/**
+ *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
+ *  @hw: pointer to the HW structure
+ *
+ *  Setup some GG82563 PHY registers for obtaining link
+ **/
+static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u32 ctrl_ext;
+       u32 i = 0;
+       u16 data, data2;
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
+       if (ret_val)
+               return ret_val;
+
+       data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+       /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
+       data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
+
+       ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * Options:
+        *   MDI/MDI-X = 0 (default)
+        *   0 - Auto for all speeds
+        *   1 - MDI mode
+        *   2 - MDI-X mode
+        *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+        */
+       ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
+       if (ret_val)
+               return ret_val;
+
+       data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
+
+       switch (phy->mdix) {
+       case 1:
+               data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
+               break;
+       case 2:
+               data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
+               break;
+       case 0:
+       default:
+               data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
+               break;
+       }
+
+       /*
+        * Options:
+        *   disable_polarity_correction = 0 (default)
+        *       Automatic Correction for Reversed Cable Polarity
+        *   0 - Disabled
+        *   1 - Enabled
+        */
+       data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+       if (phy->disable_polarity_correction)
+               data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+
+       ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
+       if (ret_val)
+               return ret_val;
+
+       /* SW Reset the PHY so all changes take effect */
+       ret_val = e1000e_commit_phy(hw);
+       if (ret_val) {
+               hw_dbg(hw, "Error Resetting the PHY\n");
+               return ret_val;
+       }
+
+       /* Bypass Rx and Tx FIFO's */
+       ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
+                                       E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
+                                       E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000e_read_kmrn_reg(hw,
+                                      E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
+                                      &data);
+       if (ret_val)
+               return ret_val;
+       data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
+       ret_val = e1000e_write_kmrn_reg(hw,
+                                       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
+                                       data);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
+       if (ret_val)
+               return ret_val;
+
+       data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
+       ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
+       if (ret_val)
+               return ret_val;
+
+       ctrl_ext = er32(CTRL_EXT);
+       ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
+       ew32(CTRL_EXT, ctrl_ext);
+
+       ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * Do not init these registers when the HW is in IAMT mode, since the
+        * firmware will have already initialized them.  We only initialize
+        * them if the HW is not in IAMT mode.
+        */
+       if (!e1000e_check_mng_mode(hw)) {
+               /* Enable Electrical Idle on the PHY */
+               data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
+               ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
+               if (ret_val)
+                       return ret_val;
+
+               do {
+                       ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                          &data2);
+                       if (ret_val)
+                               return ret_val;
+                       i++;
+               } while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY));
+
+               data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+               ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       /*
+        * Workaround: Disable padding in Kumeran interface in the MAC
+        * and in the PHY to avoid CRC errors.
+        */
+       ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
+       if (ret_val)
+               return ret_val;
+
+       data |= GG82563_ICR_DIS_PADDING;
+       ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
+       if (ret_val)
+               return ret_val;
+
+       return 0;
+}
+
+/**
+ *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
+ *  @hw: pointer to the HW structure
+ *
+ *  Essentially a wrapper for setting up all things "copper" related.
+ *  This is a function pointer entry point called by the mac module.
+ **/
+static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       s32 ret_val;
+       u16 reg_data;
+
+       ctrl = er32(CTRL);
+       ctrl |= E1000_CTRL_SLU;
+       ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ew32(CTRL, ctrl);
+
+       /*
+        * Set the mac to wait the maximum time between each
+        * iteration and increase the max iterations when
+        * polling the phy; this fixes erroneous timeouts at 10Mbps.
+        */
+       ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
+       if (ret_val)
+               return ret_val;
+       ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
+       if (ret_val)
+               return ret_val;
+       reg_data |= 0x3F;
+       ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
+       if (ret_val)
+               return ret_val;
+       ret_val = e1000e_read_kmrn_reg(hw,
+                                     E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
+                                     &reg_data);
+       if (ret_val)
+               return ret_val;
+       reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
+       ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
+                                       reg_data);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000e_setup_copper_link(hw);
+
+       return 0;
+}
+
+/**
+ *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
+ *  @hw: pointer to the HW structure
+ *  @duplex: current duplex setting
+ *
+ *  Configure the KMRN interface by applying last minute quirks for
+ *  10/100 operation.
+ **/
+static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
+{
+       s32 ret_val;
+       u32 tipg;
+       u32 i = 0;
+       u16 reg_data, reg_data2;
+
+       reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
+       ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+                                       reg_data);
+       if (ret_val)
+               return ret_val;
+
+       /* Configure Transmit Inter-Packet Gap */
+       tipg = er32(TIPG);
+       tipg &= ~E1000_TIPG_IPGT_MASK;
+       tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
+       ew32(TIPG, tipg);
+
+       do {
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+               if (ret_val)
+                       return ret_val;
+
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
+               if (ret_val)
+                       return ret_val;
+               i++;
+       } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
+
+       if (duplex == HALF_DUPLEX)
+               reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
+       else
+               reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+
+       ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+       return 0;
+}
+
+/**
+ *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
+ *  @hw: pointer to the HW structure
+ *
+ *  Configure the KMRN interface by applying last minute quirks for
+ *  gigabit operation.
+ **/
+static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 reg_data, reg_data2;
+       u32 tipg;
+       u32 i = 0;
+
+       reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
+       ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+                                       reg_data);
+       if (ret_val)
+               return ret_val;
+
+       /* Configure Transmit Inter-Packet Gap */
+       tipg = er32(TIPG);
+       tipg &= ~E1000_TIPG_IPGT_MASK;
+       tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
+       ew32(TIPG, tipg);
+
+       do {
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+               if (ret_val)
+                       return ret_val;
+
+               ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
+               if (ret_val)
+                       return ret_val;
+               i++;
+       } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
+
+       reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+       ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the hardware counters by reading the counter registers.
+ **/
+static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
+{
+       u32 temp;
+
+       e1000e_clear_hw_cntrs_base(hw);
+
+       temp = er32(PRC64);
+       temp = er32(PRC127);
+       temp = er32(PRC255);
+       temp = er32(PRC511);
+       temp = er32(PRC1023);
+       temp = er32(PRC1522);
+       temp = er32(PTC64);
+       temp = er32(PTC127);
+       temp = er32(PTC255);
+       temp = er32(PTC511);
+       temp = er32(PTC1023);
+       temp = er32(PTC1522);
+
+       temp = er32(ALGNERRC);
+       temp = er32(RXERRC);
+       temp = er32(TNCRS);
+       temp = er32(CEXTERR);
+       temp = er32(TSCTC);
+       temp = er32(TSCTFC);
+
+       temp = er32(MGTPRC);
+       temp = er32(MGTPDC);
+       temp = er32(MGTPTC);
+
+       temp = er32(IAC);
+       temp = er32(ICRXOC);
+
+       temp = er32(ICRXPTC);
+       temp = er32(ICRXATC);
+       temp = er32(ICTXPTC);
+       temp = er32(ICTXATC);
+       temp = er32(ICTXQEC);
+       temp = er32(ICTXQMTC);
+       temp = er32(ICRXDMTC);
+}
+
+static struct e1000_mac_operations es2_mac_ops = {
+       .check_mng_mode         = e1000e_check_mng_mode_generic,
+       /* check_for_link dependent on media type */
+       .cleanup_led            = e1000e_cleanup_led_generic,
+       .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
+       .get_bus_info           = e1000e_get_bus_info_pcie,
+       .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
+       .led_on                 = e1000e_led_on_generic,
+       .led_off                = e1000e_led_off_generic,
+       .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
+       .reset_hw               = e1000_reset_hw_80003es2lan,
+       .init_hw                = e1000_init_hw_80003es2lan,
+       .setup_link             = e1000e_setup_link,
+       /* setup_physical_interface dependent on media type */
+};
+
+static struct e1000_phy_operations es2_phy_ops = {
+       .acquire_phy            = e1000_acquire_phy_80003es2lan,
+       .check_reset_block      = e1000e_check_reset_block_generic,
+       .commit_phy             = e1000e_phy_sw_reset,
+       .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
+       .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
+       .get_cable_length       = e1000_get_cable_length_80003es2lan,
+       .get_phy_info           = e1000e_get_phy_info_m88,
+       .read_phy_reg           = e1000_read_phy_reg_gg82563_80003es2lan,
+       .release_phy            = e1000_release_phy_80003es2lan,
+       .reset_phy              = e1000e_phy_hw_reset_generic,
+       .set_d0_lplu_state      = NULL,
+       .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
+       .write_phy_reg          = e1000_write_phy_reg_gg82563_80003es2lan,
+};
+
+static struct e1000_nvm_operations es2_nvm_ops = {
+       .acquire_nvm            = e1000_acquire_nvm_80003es2lan,
+       .read_nvm               = e1000e_read_nvm_eerd,
+       .release_nvm            = e1000_release_nvm_80003es2lan,
+       .update_nvm             = e1000e_update_nvm_checksum_generic,
+       .valid_led_default      = e1000e_valid_led_default,
+       .validate_nvm           = e1000e_validate_nvm_checksum_generic,
+       .write_nvm              = e1000_write_nvm_80003es2lan,
+};
+
+struct e1000_info e1000_es2_info = {
+       .mac                    = e1000_80003es2lan,
+       .flags                  = FLAG_HAS_HW_VLAN_FILTER
+                                 | FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_HAS_WOL
+                                 | FLAG_APME_IN_CTRL3
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_RX_NEEDS_RESTART /* errata */
+                                 | FLAG_TARC_SET_BIT_ZERO /* errata */
+                                 | FLAG_APME_CHECK_PORT_B
+                                 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
+                                 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
+       .pba                    = 38,
+       .get_variants           = e1000_get_variants_80003es2lan,
+       .mac_ops                = &es2_mac_ops,
+       .phy_ops                = &es2_phy_ops,
+       .nvm_ops                = &es2_nvm_ops,
+};
+
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/ethtool.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/ethtool.c      Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,1949 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/* ethtool support for e1000 */
+
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+
+#include "e1000.h"
+
+struct e1000_stats {
+       char stat_string[ETH_GSTRING_LEN];
+       int sizeof_stat;
+       int stat_offset;
+};
+
+#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
+                     offsetof(struct e1000_adapter, m)
+static const struct e1000_stats e1000_gstrings_stats[] = {
+       { "rx_packets", E1000_STAT(stats.gprc) },
+       { "tx_packets", E1000_STAT(stats.gptc) },
+       { "rx_bytes", E1000_STAT(stats.gorc) },
+       { "tx_bytes", E1000_STAT(stats.gotc) },
+       { "rx_broadcast", E1000_STAT(stats.bprc) },
+       { "tx_broadcast", E1000_STAT(stats.bptc) },
+       { "rx_multicast", E1000_STAT(stats.mprc) },
+       { "tx_multicast", E1000_STAT(stats.mptc) },
+       { "rx_errors", E1000_STAT(net_stats.rx_errors) },
+       { "tx_errors", E1000_STAT(net_stats.tx_errors) },
+       { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
+       { "multicast", E1000_STAT(stats.mprc) },
+       { "collisions", E1000_STAT(stats.colc) },
+       { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
+       { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
+       { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
+       { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
+       { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
+       { "rx_missed_errors", E1000_STAT(stats.mpc) },
+       { "tx_aborted_errors", E1000_STAT(stats.ecol) },
+       { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
+       { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
+       { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
+       { "tx_window_errors", E1000_STAT(stats.latecol) },
+       { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
+       { "tx_deferred_ok", E1000_STAT(stats.dc) },
+       { "tx_single_coll_ok", E1000_STAT(stats.scc) },
+       { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
+       { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
+       { "tx_restart_queue", E1000_STAT(restart_queue) },
+       { "rx_long_length_errors", E1000_STAT(stats.roc) },
+       { "rx_short_length_errors", E1000_STAT(stats.ruc) },
+       { "rx_align_errors", E1000_STAT(stats.algnerrc) },
+       { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
+       { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
+       { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
+       { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
+       { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
+       { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
+       { "rx_long_byte_count", E1000_STAT(stats.gorc) },
+       { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
+       { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
+       { "rx_header_split", E1000_STAT(rx_hdr_split) },
+       { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
+       { "tx_smbus", E1000_STAT(stats.mgptc) },
+       { "rx_smbus", E1000_STAT(stats.mgprc) },
+       { "dropped_smbus", E1000_STAT(stats.mgpdc) },
+       { "rx_dma_failed", E1000_STAT(rx_dma_failed) },
+       { "tx_dma_failed", E1000_STAT(tx_dma_failed) },
+};
+
+#define E1000_GLOBAL_STATS_LEN ARRAY_SIZE(e1000_gstrings_stats)
+#define E1000_STATS_LEN (E1000_GLOBAL_STATS_LEN)
+static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
+       "Register test  (offline)", "Eeprom test    (offline)",
+       "Interrupt test (offline)", "Loopback test  (offline)",
+       "Link test   (on/offline)"
+};
+#define E1000_TEST_LEN ARRAY_SIZE(e1000_gstrings_test)
+
+static int e1000_get_settings(struct net_device *netdev,
+                             struct ethtool_cmd *ecmd)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+       u32 status;
+
+       if (hw->phy.media_type == e1000_media_type_copper) {
+
+               ecmd->supported = (SUPPORTED_10baseT_Half |
+                                  SUPPORTED_10baseT_Full |
+                                  SUPPORTED_100baseT_Half |
+                                  SUPPORTED_100baseT_Full |
+                                  SUPPORTED_1000baseT_Full |
+                                  SUPPORTED_Autoneg |
+                                  SUPPORTED_TP);
+               if (hw->phy.type == e1000_phy_ife)
+                       ecmd->supported &= ~SUPPORTED_1000baseT_Full;
+               ecmd->advertising = ADVERTISED_TP;
+
+               if (hw->mac.autoneg == 1) {
+                       ecmd->advertising |= ADVERTISED_Autoneg;
+                       /* the e1000 autoneg seems to match ethtool nicely */
+                       ecmd->advertising |= hw->phy.autoneg_advertised;
+               }
+
+               ecmd->port = PORT_TP;
+               ecmd->phy_address = hw->phy.addr;
+               ecmd->transceiver = XCVR_INTERNAL;
+
+       } else {
+               ecmd->supported   = (SUPPORTED_1000baseT_Full |
+                                    SUPPORTED_FIBRE |
+                                    SUPPORTED_Autoneg);
+
+               ecmd->advertising = (ADVERTISED_1000baseT_Full |
+                                    ADVERTISED_FIBRE |
+                                    ADVERTISED_Autoneg);
+
+               ecmd->port = PORT_FIBRE;
+               ecmd->transceiver = XCVR_EXTERNAL;
+       }
+
+       status = er32(STATUS);
+       if (status & E1000_STATUS_LU) {
+               if (status & E1000_STATUS_SPEED_1000)
+                       ecmd->speed = 1000;
+               else if (status & E1000_STATUS_SPEED_100)
+                       ecmd->speed = 100;
+               else
+                       ecmd->speed = 10;
+
+               if (status & E1000_STATUS_FD)
+                       ecmd->duplex = DUPLEX_FULL;
+               else
+                       ecmd->duplex = DUPLEX_HALF;
+       } else {
+               ecmd->speed = -1;
+               ecmd->duplex = -1;
+       }
+
+       ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
+                        hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
+       return 0;
+}
+
+static u32 e1000_get_link(struct net_device *netdev)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+       u32 status;
+       
+       status = er32(STATUS);
+       return (status & E1000_STATUS_LU) ? 1 : 0;
+}
+
+static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
+{
+       struct e1000_mac_info *mac = &adapter->hw.mac;
+
+       mac->autoneg = 0;
+
+       /* Fiber NICs only allow 1000 gbps Full duplex */
+       if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
+               spddplx != (SPEED_1000 + DUPLEX_FULL)) {
+               e_err("Unsupported Speed/Duplex configuration\n");
+               return -EINVAL;
+       }
+
+       switch (spddplx) {
+       case SPEED_10 + DUPLEX_HALF:
+               mac->forced_speed_duplex = ADVERTISE_10_HALF;
+               break;
+       case SPEED_10 + DUPLEX_FULL:
+               mac->forced_speed_duplex = ADVERTISE_10_FULL;
+               break;
+       case SPEED_100 + DUPLEX_HALF:
+               mac->forced_speed_duplex = ADVERTISE_100_HALF;
+               break;
+       case SPEED_100 + DUPLEX_FULL:
+               mac->forced_speed_duplex = ADVERTISE_100_FULL;
+               break;
+       case SPEED_1000 + DUPLEX_FULL:
+               mac->autoneg = 1;
+               adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
+               break;
+       case SPEED_1000 + DUPLEX_HALF: /* not supported */
+       default:
+               e_err("Unsupported Speed/Duplex configuration\n");
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static int e1000_set_settings(struct net_device *netdev,
+                             struct ethtool_cmd *ecmd)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+
+       /*
+        * When SoL/IDER sessions are active, autoneg/speed/duplex
+        * cannot be changed
+        */
+       if (e1000_check_reset_block(hw)) {
+               e_err("Cannot change link characteristics when SoL/IDER is "
+                     "active.\n");
+               return -EINVAL;
+       }
+
+       while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
+               msleep(1);
+
+       if (ecmd->autoneg == AUTONEG_ENABLE) {
+               hw->mac.autoneg = 1;
+               if (hw->phy.media_type == e1000_media_type_fiber)
+                       hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
+                                                    ADVERTISED_FIBRE |
+                                                    ADVERTISED_Autoneg;
+               else
+                       hw->phy.autoneg_advertised = ecmd->advertising |
+                                                    ADVERTISED_TP |
+                                                    ADVERTISED_Autoneg;
+               ecmd->advertising = hw->phy.autoneg_advertised;
+               if (adapter->fc_autoneg)
+                       hw->fc.original_type = e1000_fc_default;
+       } else {
+               if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
+                       clear_bit(__E1000_RESETTING, &adapter->state);
+                       return -EINVAL;
+               }
+       }
+
+       /* reset the link */
+
+       if (netif_running(adapter->netdev)) {
+               e1000e_down(adapter);
+               e1000e_up(adapter);
+       } else {
+               e1000e_reset(adapter);
+       }
+
+       clear_bit(__E1000_RESETTING, &adapter->state);
+       return 0;
+}
+
+static void e1000_get_pauseparam(struct net_device *netdev,
+                                struct ethtool_pauseparam *pause)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+
+       pause->autoneg =
+               (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
+
+       if (hw->fc.type == e1000_fc_rx_pause) {
+               pause->rx_pause = 1;
+       } else if (hw->fc.type == e1000_fc_tx_pause) {
+               pause->tx_pause = 1;
+       } else if (hw->fc.type == e1000_fc_full) {
+               pause->rx_pause = 1;
+               pause->tx_pause = 1;
+       }
+}
+
+static int e1000_set_pauseparam(struct net_device *netdev,
+                               struct ethtool_pauseparam *pause)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+       int retval = 0;
+
+       adapter->fc_autoneg = pause->autoneg;
+
+       while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
+               msleep(1);
+
+       if (pause->rx_pause && pause->tx_pause)
+               hw->fc.type = e1000_fc_full;
+       else if (pause->rx_pause && !pause->tx_pause)
+               hw->fc.type = e1000_fc_rx_pause;
+       else if (!pause->rx_pause && pause->tx_pause)
+               hw->fc.type = e1000_fc_tx_pause;
+       else if (!pause->rx_pause && !pause->tx_pause)
+               hw->fc.type = e1000_fc_none;
+
+       hw->fc.original_type = hw->fc.type;
+
+       if (adapter->fc_autoneg == AUTONEG_ENABLE) {
+               hw->fc.type = e1000_fc_default;
+               if (netif_running(adapter->netdev)) {
+                       e1000e_down(adapter);
+                       e1000e_up(adapter);
+               } else {
+                       e1000e_reset(adapter);
+               }
+       } else {
+               retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
+                         hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw));
+       }
+
+       clear_bit(__E1000_RESETTING, &adapter->state);
+       return retval;
+}
+
+static u32 e1000_get_rx_csum(struct net_device *netdev)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       return (adapter->flags & FLAG_RX_CSUM_ENABLED);
+}
+
+static int e1000_set_rx_csum(struct net_device *netdev, u32 data)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+
+       if (data)
+               adapter->flags |= FLAG_RX_CSUM_ENABLED;
+       else
+               adapter->flags &= ~FLAG_RX_CSUM_ENABLED;
+
+       if (netif_running(netdev))
+               e1000e_reinit_locked(adapter);
+       else
+               e1000e_reset(adapter);
+       return 0;
+}
+
+static u32 e1000_get_tx_csum(struct net_device *netdev)
+{
+       return ((netdev->features & NETIF_F_HW_CSUM) != 0);
+}
+
+static int e1000_set_tx_csum(struct net_device *netdev, u32 data)
+{
+       if (data)
+               netdev->features |= NETIF_F_HW_CSUM;
+       else
+               netdev->features &= ~NETIF_F_HW_CSUM;
+
+       return 0;
+}
+
+static int e1000_set_tso(struct net_device *netdev, u32 data)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+
+       if (data) {
+               netdev->features |= NETIF_F_TSO;
+               netdev->features |= NETIF_F_TSO6;
+       } else {
+               netdev->features &= ~NETIF_F_TSO;
+               netdev->features &= ~NETIF_F_TSO6;
+       }
+
+       e_info("TSO is %s\n", data ? "Enabled" : "Disabled");
+       adapter->flags |= FLAG_TSO_FORCE;
+       return 0;
+}
+
+static u32 e1000_get_msglevel(struct net_device *netdev)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       return adapter->msg_enable;
+}
+
+static void e1000_set_msglevel(struct net_device *netdev, u32 data)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       adapter->msg_enable = data;
+}
+
+static int e1000_get_regs_len(struct net_device *netdev)
+{
+#define E1000_REGS_LEN 32 /* overestimate */
+       return E1000_REGS_LEN * sizeof(u32);
+}
+
+static void e1000_get_regs(struct net_device *netdev,
+                          struct ethtool_regs *regs, void *p)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+       u32 *regs_buff = p;
+       u16 phy_data;
+       u8 revision_id;
+
+       memset(p, 0, E1000_REGS_LEN * sizeof(u32));
+
+       pci_read_config_byte(adapter->pdev, PCI_REVISION_ID, &revision_id);
+
+       regs->version = (1 << 24) | (revision_id << 16) | adapter->pdev->device;
+
+       regs_buff[0]  = er32(CTRL);
+       regs_buff[1]  = er32(STATUS);
+
+       regs_buff[2]  = er32(RCTL);
+       regs_buff[3]  = er32(RDLEN);
+       regs_buff[4]  = er32(RDH);
+       regs_buff[5]  = er32(RDT);
+       regs_buff[6]  = er32(RDTR);
+
+       regs_buff[7]  = er32(TCTL);
+       regs_buff[8]  = er32(TDLEN);
+       regs_buff[9]  = er32(TDH);
+       regs_buff[10] = er32(TDT);
+       regs_buff[11] = er32(TIDV);
+
+       regs_buff[12] = adapter->hw.phy.type;  /* PHY type (IGP=1, M88=0) */
+       if (hw->phy.type == e1000_phy_m88) {
+               e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+               regs_buff[13] = (u32)phy_data; /* cable length */
+               regs_buff[14] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
+               regs_buff[15] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
+               regs_buff[16] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
+               e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+               regs_buff[17] = (u32)phy_data; /* extended 10bt distance */
+               regs_buff[18] = regs_buff[13]; /* cable polarity */
+               regs_buff[19] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
+               regs_buff[20] = regs_buff[17]; /* polarity correction */
+               /* phy receive errors */
+               regs_buff[22] = adapter->phy_stats.receive_errors;
+               regs_buff[23] = regs_buff[13]; /* mdix mode */
+       }
+       regs_buff[21] = adapter->phy_stats.idle_errors;  /* phy idle errors */
+       e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
+       regs_buff[24] = (u32)phy_data;  /* phy local receiver status */
+       regs_buff[25] = regs_buff[24];  /* phy remote receiver status */
+}
+
+static int e1000_get_eeprom_len(struct net_device *netdev)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       return adapter->hw.nvm.word_size * 2;
+}
+
+static int e1000_get_eeprom(struct net_device *netdev,
+                           struct ethtool_eeprom *eeprom, u8 *bytes)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+       u16 *eeprom_buff;
+       int first_word;
+       int last_word;
+       int ret_val = 0;
+       u16 i;
+
+       if (eeprom->len == 0)
+               return -EINVAL;
+
+       eeprom->magic = adapter->pdev->vendor | (adapter->pdev->device << 16);
+
+       first_word = eeprom->offset >> 1;
+       last_word = (eeprom->offset + eeprom->len - 1) >> 1;
+
+       eeprom_buff = kmalloc(sizeof(u16) *
+                       (last_word - first_word + 1), GFP_KERNEL);
+       if (!eeprom_buff)
+               return -ENOMEM;
+
+       if (hw->nvm.type == e1000_nvm_eeprom_spi) {
+               ret_val = e1000_read_nvm(hw, first_word,
+                                        last_word - first_word + 1,
+                                        eeprom_buff);
+       } else {
+               for (i = 0; i < last_word - first_word + 1; i++) {
+                       ret_val = e1000_read_nvm(hw, first_word + i, 1,
+                                                     &eeprom_buff[i]);
+                       if (ret_val) {
+                               /* a read error occurred, throw away the
+                                * result */
+                               memset(eeprom_buff, 0xff, sizeof(eeprom_buff));
+                               break;
+                       }
+               }
+       }
+
+       /* Device's eeprom is always little-endian, word addressable */
+       for (i = 0; i < last_word - first_word + 1; i++)
+               le16_to_cpus(&eeprom_buff[i]);
+
+       memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
+       kfree(eeprom_buff);
+
+       return ret_val;
+}
+
+static int e1000_set_eeprom(struct net_device *netdev,
+                           struct ethtool_eeprom *eeprom, u8 *bytes)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+       u16 *eeprom_buff;
+       void *ptr;
+       int max_len;
+       int first_word;
+       int last_word;
+       int ret_val = 0;
+       u16 i;
+
+       if (eeprom->len == 0)
+               return -EOPNOTSUPP;
+
+       if (eeprom->magic != (adapter->pdev->vendor | (adapter->pdev->device << 
16)))
+               return -EFAULT;
+
+       if (adapter->flags & FLAG_READ_ONLY_NVM)
+               return -EINVAL;
+
+       max_len = hw->nvm.word_size * 2;
+
+       first_word = eeprom->offset >> 1;
+       last_word = (eeprom->offset + eeprom->len - 1) >> 1;
+       eeprom_buff = kmalloc(max_len, GFP_KERNEL);
+       if (!eeprom_buff)
+               return -ENOMEM;
+
+       ptr = (void *)eeprom_buff;
+
+       if (eeprom->offset & 1) {
+               /* need read/modify/write of first changed EEPROM word */
+               /* only the second byte of the word is being modified */
+               ret_val = e1000_read_nvm(hw, first_word, 1, &eeprom_buff[0]);
+               ptr++;
+       }
+       if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0))
+               /* need read/modify/write of last changed EEPROM word */
+               /* only the first byte of the word is being modified */
+               ret_val = e1000_read_nvm(hw, last_word, 1,
+                                 &eeprom_buff[last_word - first_word]);
+
+       /* Device's eeprom is always little-endian, word addressable */
+       for (i = 0; i < last_word - first_word + 1; i++)
+               le16_to_cpus(&eeprom_buff[i]);
+
+       memcpy(ptr, bytes, eeprom->len);
+
+       for (i = 0; i < last_word - first_word + 1; i++)
+               eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
+
+       ret_val = e1000_write_nvm(hw, first_word,
+                                 last_word - first_word + 1, eeprom_buff);
+
+       /*
+        * Update the checksum over the first part of the EEPROM if needed
+        * and flush shadow RAM for 82573 controllers
+        */
+       if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG) ||
+                              (hw->mac.type == e1000_82574) ||
+                              (hw->mac.type == e1000_82573)))
+               e1000e_update_nvm_checksum(hw);
+
+       kfree(eeprom_buff);
+       return ret_val;
+}
+
+static void e1000_get_drvinfo(struct net_device *netdev,
+                             struct ethtool_drvinfo *drvinfo)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       char firmware_version[32];
+       u16 eeprom_data;
+
+       strncpy(drvinfo->driver,  e1000e_driver_name, 32);
+       strncpy(drvinfo->version, e1000e_driver_version, 32);
+
+       /*
+        * EEPROM image version # is reported as firmware version # for
+        * PCI-E controllers
+        */
+       e1000_read_nvm(&adapter->hw, 5, 1, &eeprom_data);
+       sprintf(firmware_version, "%d.%d-%d",
+               (eeprom_data & 0xF000) >> 12,
+               (eeprom_data & 0x0FF0) >> 4,
+               eeprom_data & 0x000F);
+
+       strncpy(drvinfo->fw_version, firmware_version, 32);
+       strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+       drvinfo->regdump_len = e1000_get_regs_len(netdev);
+       drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
+}
+
+static void e1000_get_ringparam(struct net_device *netdev,
+                               struct ethtool_ringparam *ring)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_ring *tx_ring = adapter->tx_ring;
+       struct e1000_ring *rx_ring = adapter->rx_ring;
+
+       ring->rx_max_pending = E1000_MAX_RXD;
+       ring->tx_max_pending = E1000_MAX_TXD;
+       ring->rx_mini_max_pending = 0;
+       ring->rx_jumbo_max_pending = 0;
+       ring->rx_pending = rx_ring->count;
+       ring->tx_pending = tx_ring->count;
+       ring->rx_mini_pending = 0;
+       ring->rx_jumbo_pending = 0;
+}
+
+static int e1000_set_ringparam(struct net_device *netdev,
+                              struct ethtool_ringparam *ring)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_ring *tx_ring, *tx_old;
+       struct e1000_ring *rx_ring, *rx_old;
+       int err;
+
+       if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
+               return -EINVAL;
+
+       while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
+               msleep(1);
+
+       if (netif_running(adapter->netdev))
+               e1000e_down(adapter);
+
+       tx_old = adapter->tx_ring;
+       rx_old = adapter->rx_ring;
+
+       err = -ENOMEM;
+       tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
+       if (!tx_ring)
+               goto err_alloc_tx;
+       /*
+        * use a memcpy to save any previously configured
+        * items like napi structs from having to be
+        * reinitialized
+        */
+       memcpy(tx_ring, tx_old, sizeof(struct e1000_ring));
+
+       rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
+       if (!rx_ring)
+               goto err_alloc_rx;
+       memcpy(rx_ring, rx_old, sizeof(struct e1000_ring));
+
+       adapter->tx_ring = tx_ring;
+       adapter->rx_ring = rx_ring;
+
+       rx_ring->count = max(ring->rx_pending, (u32)E1000_MIN_RXD);
+       rx_ring->count = min(rx_ring->count, (u32)(E1000_MAX_RXD));
+       rx_ring->count = ALIGN(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
+
+       tx_ring->count = max(ring->tx_pending, (u32)E1000_MIN_TXD);
+       tx_ring->count = min(tx_ring->count, (u32)(E1000_MAX_TXD));
+       tx_ring->count = ALIGN(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
+
+       if (netif_running(adapter->netdev)) {
+               /* Try to get new resources before deleting old */
+               err = e1000e_setup_rx_resources(adapter);
+               if (err)
+                       goto err_setup_rx;
+               err = e1000e_setup_tx_resources(adapter);
+               if (err)
+                       goto err_setup_tx;
+
+               /*
+                * restore the old in order to free it,
+                * then add in the new
+                */
+               adapter->rx_ring = rx_old;
+               adapter->tx_ring = tx_old;
+               e1000e_free_rx_resources(adapter);
+               e1000e_free_tx_resources(adapter);
+               kfree(tx_old);
+               kfree(rx_old);
+               adapter->rx_ring = rx_ring;
+               adapter->tx_ring = tx_ring;
+               err = e1000e_up(adapter);
+               if (err)
+                       goto err_setup;
+       }
+
+       clear_bit(__E1000_RESETTING, &adapter->state);
+       return 0;
+err_setup_tx:
+       e1000e_free_rx_resources(adapter);
+err_setup_rx:
+       adapter->rx_ring = rx_old;
+       adapter->tx_ring = tx_old;
+       kfree(rx_ring);
+err_alloc_rx:
+       kfree(tx_ring);
+err_alloc_tx:
+       e1000e_up(adapter);
+err_setup:
+       clear_bit(__E1000_RESETTING, &adapter->state);
+       return err;
+}
+
+static int reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
+                            int reg, int offset, u32 mask, u32 write)
+{
+       u32 pat, val;
+       static const u32 test[] =
+               {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
+       for (pat = 0; pat < ARRAY_SIZE(test); pat++) {
+               E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset,
+                                     (test[pat] & write));
+               val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset);
+               if (val != (test[pat] & write & mask)) {
+                       e_err("pattern test reg %04X failed: got 0x%08X "
+                             "expected 0x%08X\n", reg + offset, val,
+                             (test[pat] & write & mask));
+                       *data = reg;
+                       return 1;
+               }
+       }
+       return 0;
+}
+
+static int reg_set_and_check(struct e1000_adapter *adapter, u64 *data,
+                             int reg, u32 mask, u32 write)
+{
+       u32 val;
+       __ew32(&adapter->hw, reg, write & mask);
+       val = __er32(&adapter->hw, reg);
+       if ((write & mask) != (val & mask)) {
+               e_err("set/check reg %04X test failed: got 0x%08X "
+                     "expected 0x%08X\n", reg, (val & mask), (write & mask));
+               *data = reg;
+               return 1;
+       }
+       return 0;
+}
+#define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write)                       
\
+       do {                                                                   \
+               if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \
+                       return 1;                                              \
+       } while (0)
+#define REG_PATTERN_TEST(reg, mask, write)                                     
\
+       REG_PATTERN_TEST_ARRAY(reg, 0, mask, write)
+
+#define REG_SET_AND_CHECK(reg, mask, write)                                    
\
+       do {                                                                   \
+               if (reg_set_and_check(adapter, data, reg, mask, write))        \
+                       return 1;                                              \
+       } while (0)
+
+static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       struct e1000_mac_info *mac = &adapter->hw.mac;
+       u32 value;
+       u32 before;
+       u32 after;
+       u32 i;
+       u32 toggle;
+
+       /*
+        * The status register is Read Only, so a write should fail.
+        * Some bits that get toggled are ignored.
+        */
+       switch (mac->type) {
+       /* there are several bits on newer hardware that are r/w */
+       case e1000_82571:
+       case e1000_82572:
+       case e1000_80003es2lan:
+               toggle = 0x7FFFF3FF;
+               break;
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_ich8lan:
+       case e1000_ich9lan:
+       case e1000_ich10lan:
+               toggle = 0x7FFFF033;
+               break;
+       default:
+               toggle = 0xFFFFF833;
+               break;
+       }
+
+       before = er32(STATUS);
+       value = (er32(STATUS) & toggle);
+       ew32(STATUS, toggle);
+       after = er32(STATUS) & toggle;
+       if (value != after) {
+               e_err("failed STATUS register test got: 0x%08X expected: "
+                     "0x%08X\n", after, value);
+               *data = 1;
+               return 1;
+       }
+       /* restore previous status */
+       ew32(STATUS, before);
+
+       if (!(adapter->flags & FLAG_IS_ICH)) {
+               REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
+               REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
+               REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
+               REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
+       }
+
+       REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
+       REG_PATTERN_TEST(E1000_RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
+       REG_PATTERN_TEST(E1000_RDLEN, 0x000FFF80, 0x000FFFFF);
+       REG_PATTERN_TEST(E1000_RDH, 0x0000FFFF, 0x0000FFFF);
+       REG_PATTERN_TEST(E1000_RDT, 0x0000FFFF, 0x0000FFFF);
+       REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
+       REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
+       REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
+       REG_PATTERN_TEST(E1000_TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
+       REG_PATTERN_TEST(E1000_TDLEN, 0x000FFF80, 0x000FFFFF);
+
+       REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
+
+       before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);
+       REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
+       REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
+
+       REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
+       REG_PATTERN_TEST(E1000_RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
+       if (!(adapter->flags & FLAG_IS_ICH))
+               REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
+       REG_PATTERN_TEST(E1000_TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
+       REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
+       for (i = 0; i < mac->rar_entry_count; i++)
+               REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
+                                      ((mac->type == e1000_ich10lan) ?
+                                          0x8007FFFF : 0x8003FFFF),
+                                      0xFFFFFFFF);
+
+       for (i = 0; i < mac->mta_reg_count; i++)
+               REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
+
+       *data = 0;
+       return 0;
+}
+
+static int e1000_eeprom_test(struct e1000_adapter *adapter, u64 *data)
+{
+       u16 temp;
+       u16 checksum = 0;
+       u16 i;
+
+       *data = 0;
+       /* Read and add up the contents of the EEPROM */
+       for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
+               if ((e1000_read_nvm(&adapter->hw, i, 1, &temp)) < 0) {
+                       *data = 1;
+                       break;
+               }
+               checksum += temp;
+       }
+
+       /* If Checksum is not Correct return error else test passed */
+       if ((checksum != (u16) NVM_SUM) && !(*data))
+               *data = 2;
+
+       return *data;
+}
+
+static irqreturn_t e1000_test_intr(int irq, void *data, struct pt_regs *regs)
+{
+       struct net_device *netdev = (struct net_device *) data;
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+
+       adapter->test_icr |= er32(ICR);
+
+       return IRQ_HANDLED;
+}
+
+static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
+{
+       struct net_device *netdev = adapter->netdev;
+       struct e1000_hw *hw = &adapter->hw;
+       u32 mask;
+       u32 shared_int = 1;
+       u32 irq = adapter->pdev->irq;
+       int i;
+       int ret_val = 0;
+       int int_mode = E1000E_INT_MODE_LEGACY;
+
+       *data = 0;
+
+       /* NOTE: we don't test MSI/MSI-X interrupts here, yet */
+       if (adapter->int_mode == E1000E_INT_MODE_MSIX) {
+               int_mode = adapter->int_mode;
+               e1000e_reset_interrupt_capability(adapter);
+               adapter->int_mode = E1000E_INT_MODE_LEGACY;
+               e1000e_set_interrupt_capability(adapter);
+       }
+       /* Hook up test interrupt handler just for this test */
+       if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
+                        netdev)) {
+               shared_int = 0;
+       } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
+                netdev->name, netdev)) {
+               *data = 1;
+               ret_val = -1;
+               goto out;
+       }
+       e_info("testing %s interrupt\n", (shared_int ? "shared" : "unshared"));
+
+       /* Disable all the interrupts */
+       ew32(IMC, 0xFFFFFFFF);
+       msleep(10);
+
+       /* Test each interrupt */
+       for (i = 0; i < 10; i++) {
+               /* Interrupt to test */
+               mask = 1 << i;
+
+               if (adapter->flags & FLAG_IS_ICH) {
+                       switch (mask) {
+                       case E1000_ICR_RXSEQ:
+                               continue;
+                       case 0x00000100:
+                               if (adapter->hw.mac.type == e1000_ich8lan ||
+                                   adapter->hw.mac.type == e1000_ich9lan)
+                                       continue;
+                               break;
+                       default:
+                               break;
+                       }
+               }
+
+               if (!shared_int) {
+                       /*
+                        * Disable the interrupt to be reported in
+                        * the cause register and then force the same
+                        * interrupt and see if one gets posted.  If
+                        * an interrupt was posted to the bus, the
+                        * test failed.
+                        */
+                       adapter->test_icr = 0;
+                       ew32(IMC, mask);
+                       ew32(ICS, mask);
+                       msleep(10);
+
+                       if (adapter->test_icr & mask) {
+                               *data = 3;
+                               break;
+                       }
+               }
+
+               /*
+                * Enable the interrupt to be reported in
+                * the cause register and then force the same
+                * interrupt and see if one gets posted.  If
+                * an interrupt was not posted to the bus, the
+                * test failed.
+                */
+               adapter->test_icr = 0;
+               ew32(IMS, mask);
+               ew32(ICS, mask);
+               msleep(10);
+
+               if (!(adapter->test_icr & mask)) {
+                       *data = 4;
+                       break;
+               }
+
+               if (!shared_int) {
+                       /*
+                        * Disable the other interrupts to be reported in
+                        * the cause register and then force the other
+                        * interrupts and see if any get posted.  If
+                        * an interrupt was posted to the bus, the
+                        * test failed.
+                        */
+                       adapter->test_icr = 0;
+                       ew32(IMC, ~mask & 0x00007FFF);
+                       ew32(ICS, ~mask & 0x00007FFF);
+                       msleep(10);
+
+                       if (adapter->test_icr) {
+                               *data = 5;
+                               break;
+                       }
+               }
+       }
+
+       /* Disable all the interrupts */
+       ew32(IMC, 0xFFFFFFFF);
+       msleep(10);
+
+       /* Unhook test interrupt handler */
+       free_irq(irq, netdev);
+
+out:
+       if (int_mode == E1000E_INT_MODE_MSIX) {
+               e1000e_reset_interrupt_capability(adapter);
+               adapter->int_mode = int_mode;
+               e1000e_set_interrupt_capability(adapter);
+       }
+
+       return ret_val;
+}
+
+static void e1000_free_desc_rings(struct e1000_adapter *adapter)
+{
+       struct e1000_ring *tx_ring = &adapter->test_tx_ring;
+       struct e1000_ring *rx_ring = &adapter->test_rx_ring;
+       struct pci_dev *pdev = adapter->pdev;
+       int i;
+
+       if (tx_ring->desc && tx_ring->buffer_info) {
+               for (i = 0; i < tx_ring->count; i++) {
+                       if (tx_ring->buffer_info[i].dma)
+                               pci_unmap_single(pdev,
+                                       tx_ring->buffer_info[i].dma,
+                                       tx_ring->buffer_info[i].length,
+                                       PCI_DMA_TODEVICE);
+                       if (tx_ring->buffer_info[i].skb)
+                               dev_kfree_skb(tx_ring->buffer_info[i].skb);
+               }
+       }
+
+       if (rx_ring->desc && rx_ring->buffer_info) {
+               for (i = 0; i < rx_ring->count; i++) {
+                       if (rx_ring->buffer_info[i].dma)
+                               pci_unmap_single(pdev,
+                                       rx_ring->buffer_info[i].dma,
+                                       2048, PCI_DMA_FROMDEVICE);
+                       if (rx_ring->buffer_info[i].skb)
+                               dev_kfree_skb(rx_ring->buffer_info[i].skb);
+               }
+       }
+
+       if (tx_ring->desc) {
+               dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
+                                 tx_ring->dma);
+               tx_ring->desc = NULL;
+       }
+       if (rx_ring->desc) {
+               dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
+                                 rx_ring->dma);
+               rx_ring->desc = NULL;
+       }
+
+       kfree(tx_ring->buffer_info);
+       tx_ring->buffer_info = NULL;
+       kfree(rx_ring->buffer_info);
+       rx_ring->buffer_info = NULL;
+}
+
+static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
+{
+       struct e1000_ring *tx_ring = &adapter->test_tx_ring;
+       struct e1000_ring *rx_ring = &adapter->test_rx_ring;
+       struct pci_dev *pdev = adapter->pdev;
+       struct e1000_hw *hw = &adapter->hw;
+       u32 rctl;
+       int i;
+       int ret_val;
+
+       /* Setup Tx descriptor ring and Tx buffers */
+
+       if (!tx_ring->count)
+               tx_ring->count = E1000_DEFAULT_TXD;
+
+       tx_ring->buffer_info = kcalloc(tx_ring->count,
+                                      sizeof(struct e1000_buffer),
+                                      GFP_KERNEL);
+       if (!(tx_ring->buffer_info)) {
+               ret_val = 1;
+               goto err_nomem;
+       }
+
+       tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
+       tx_ring->size = ALIGN(tx_ring->size, 4096);
+       tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
+                                          &tx_ring->dma, GFP_KERNEL);
+       if (!tx_ring->desc) {
+               ret_val = 2;
+               goto err_nomem;
+       }
+       tx_ring->next_to_use = 0;
+       tx_ring->next_to_clean = 0;
+
+       ew32(TDBAL, ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
+       ew32(TDBAH, ((u64) tx_ring->dma >> 32));
+       ew32(TDLEN, tx_ring->count * sizeof(struct e1000_tx_desc));
+       ew32(TDH, 0);
+       ew32(TDT, 0);
+       ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN | E1000_TCTL_MULR |
+            E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
+            E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
+
+       for (i = 0; i < tx_ring->count; i++) {
+               struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
+               struct sk_buff *skb;
+               unsigned int skb_size = 1024;
+
+               skb = alloc_skb(skb_size, GFP_KERNEL);
+               if (!skb) {
+                       ret_val = 3;
+                       goto err_nomem;
+               }
+               skb_put(skb, skb_size);
+               tx_ring->buffer_info[i].skb = skb;
+               tx_ring->buffer_info[i].length = skb->len;
+               tx_ring->buffer_info[i].dma =
+                       pci_map_single(pdev, skb->data, skb->len,
+                                      PCI_DMA_TODEVICE);
+               if (pci_dma_mapping_error(tx_ring->buffer_info[i].dma)) {
+                       ret_val = 4;
+                       goto err_nomem;
+               }
+               tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
+               tx_desc->lower.data = cpu_to_le32(skb->len);
+               tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
+                                                  E1000_TXD_CMD_IFCS |
+                                                  E1000_TXD_CMD_RS);
+               tx_desc->upper.data = 0;
+       }
+
+       /* Setup Rx descriptor ring and Rx buffers */
+
+       if (!rx_ring->count)
+               rx_ring->count = E1000_DEFAULT_RXD;
+
+       rx_ring->buffer_info = kcalloc(rx_ring->count,
+                                      sizeof(struct e1000_buffer),
+                                      GFP_KERNEL);
+       if (!(rx_ring->buffer_info)) {
+               ret_val = 5;
+               goto err_nomem;
+       }
+
+       rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
+       rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
+                                          &rx_ring->dma, GFP_KERNEL);
+       if (!rx_ring->desc) {
+               ret_val = 6;
+               goto err_nomem;
+       }
+       rx_ring->next_to_use = 0;
+       rx_ring->next_to_clean = 0;
+
+       rctl = er32(RCTL);
+       ew32(RCTL, rctl & ~E1000_RCTL_EN);
+       ew32(RDBAL, ((u64) rx_ring->dma & 0xFFFFFFFF));
+       ew32(RDBAH, ((u64) rx_ring->dma >> 32));
+       ew32(RDLEN, rx_ring->size);
+       ew32(RDH, 0);
+       ew32(RDT, 0);
+       rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
+               E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_LPE |
+               E1000_RCTL_SBP | E1000_RCTL_SECRC |
+               E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
+               (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
+       ew32(RCTL, rctl);
+
+       for (i = 0; i < rx_ring->count; i++) {
+               struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
+               struct sk_buff *skb;
+
+               skb = alloc_skb(2048 + NET_IP_ALIGN, GFP_KERNEL);
+               if (!skb) {
+                       ret_val = 7;
+                       goto err_nomem;
+               }
+               skb_reserve(skb, NET_IP_ALIGN);
+               rx_ring->buffer_info[i].skb = skb;
+               rx_ring->buffer_info[i].dma =
+                       pci_map_single(pdev, skb->data, 2048,
+                                      PCI_DMA_FROMDEVICE);
+               if (pci_dma_mapping_error(rx_ring->buffer_info[i].dma)) {
+                       ret_val = 8;
+                       goto err_nomem;
+               }
+               rx_desc->buffer_addr =
+                       cpu_to_le64(rx_ring->buffer_info[i].dma);
+               memset(skb->data, 0x00, skb->len);
+       }
+
+       return 0;
+
+err_nomem:
+       e1000_free_desc_rings(adapter);
+       return ret_val;
+}
+
+static void e1000_phy_disable_receiver(struct e1000_adapter *adapter)
+{
+       /* Write out to PHY registers 29 and 30 to disable the Receiver. */
+       e1e_wphy(&adapter->hw, 29, 0x001F);
+       e1e_wphy(&adapter->hw, 30, 0x8FFC);
+       e1e_wphy(&adapter->hw, 29, 0x001A);
+       e1e_wphy(&adapter->hw, 30, 0x8FF0);
+}
+
+static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       u32 ctrl_reg = 0;
+       u32 stat_reg = 0;
+       u16 phy_reg = 0;
+
+       hw->mac.autoneg = 0;
+
+       if (hw->phy.type == e1000_phy_m88) {
+               /* Auto-MDI/MDIX Off */
+               e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
+               /* reset to update Auto-MDI/MDIX */
+               e1e_wphy(hw, PHY_CONTROL, 0x9140);
+               /* autoneg off */
+               e1e_wphy(hw, PHY_CONTROL, 0x8140);
+       } else if (hw->phy.type == e1000_phy_gg82563)
+               e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
+
+       ctrl_reg = er32(CTRL);
+
+       switch (hw->phy.type) {
+       case e1000_phy_ife:
+               /* force 100, set loopback */
+               e1e_wphy(hw, PHY_CONTROL, 0x6100);
+
+               /* Now set up the MAC to the same speed/duplex as the PHY. */
+               ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
+               ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
+                            E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
+                            E1000_CTRL_SPD_100 |/* Force Speed to 100 */
+                            E1000_CTRL_FD);     /* Force Duplex to FULL */
+               break;
+       case e1000_phy_bm:
+               /* Set Default MAC Interface speed to 1GB */
+               e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);
+               phy_reg &= ~0x0007;
+               phy_reg |= 0x006;
+               e1e_wphy(hw, PHY_REG(2, 21), phy_reg);
+               /* Assert SW reset for above settings to take effect */
+               e1000e_commit_phy(hw);
+               mdelay(1);
+               /* Force Full Duplex */
+               e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
+               e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);
+               /* Set Link Up (in force link) */
+               e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);
+               e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);
+               /* Force Link */
+               e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);
+               e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);
+               /* Set Early Link Enable */
+               e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
+               e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400);
+               /* fall through */
+       default:
+               /* force 1000, set loopback */
+               e1e_wphy(hw, PHY_CONTROL, 0x4140);
+               mdelay(250);
+
+               /* Now set up the MAC to the same speed/duplex as the PHY. */
+               ctrl_reg = er32(CTRL);
+               ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
+               ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
+                            E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
+                            E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
+                            E1000_CTRL_FD);     /* Force Duplex to FULL */
+
+               if (adapter->flags & FLAG_IS_ICH)
+                       ctrl_reg |= E1000_CTRL_SLU;     /* Set Link Up */
+       }
+
+       if (hw->phy.media_type == e1000_media_type_copper &&
+           hw->phy.type == e1000_phy_m88) {
+               ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
+       } else {
+               /*
+                * Set the ILOS bit on the fiber Nic if half duplex link is
+                * detected.
+                */
+               stat_reg = er32(STATUS);
+               if ((stat_reg & E1000_STATUS_FD) == 0)
+                       ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
+       }
+
+       ew32(CTRL, ctrl_reg);
+
+       /*
+        * Disable the receiver on the PHY so when a cable is plugged in, the
+        * PHY does not begin to autoneg when a cable is reconnected to the NIC.
+        */
+       if (hw->phy.type == e1000_phy_m88)
+               e1000_phy_disable_receiver(adapter);
+
+       udelay(500);
+
+       return 0;
+}
+
+static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       u32 ctrl = er32(CTRL);
+       int link = 0;
+
+       /* special requirements for 82571/82572 fiber adapters */
+
+       /*
+        * jump through hoops to make sure link is up because serdes
+        * link is hardwired up
+        */
+       ctrl |= E1000_CTRL_SLU;
+       ew32(CTRL, ctrl);
+
+       /* disable autoneg */
+       ctrl = er32(TXCW);
+       ctrl &= ~(1 << 31);
+       ew32(TXCW, ctrl);
+
+       link = (er32(STATUS) & E1000_STATUS_LU);
+
+       if (!link) {
+               /* set invert loss of signal */
+               ctrl = er32(CTRL);
+               ctrl |= E1000_CTRL_ILOS;
+               ew32(CTRL, ctrl);
+       }
+
+       /*
+        * special write to serdes control register to enable SerDes analog
+        * loopback
+        */
+#define E1000_SERDES_LB_ON 0x410
+       ew32(SCTL, E1000_SERDES_LB_ON);
+       msleep(10);
+
+       return 0;
+}
+
+/* only call this for fiber/serdes connections to es2lan */
+static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       u32 ctrlext = er32(CTRL_EXT);
+       u32 ctrl = er32(CTRL);
+
+       /*
+        * save CTRL_EXT to restore later, reuse an empty variable (unused
+        * on mac_type 80003es2lan)
+        */
+       adapter->tx_fifo_head = ctrlext;
+
+       /* clear the serdes mode bits, putting the device into mac loopback */
+       ctrlext &= ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
+       ew32(CTRL_EXT, ctrlext);
+
+       /* force speed to 1000/FD, link up */
+       ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+       ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
+                E1000_CTRL_SPD_1000 | E1000_CTRL_FD);
+       ew32(CTRL, ctrl);
+
+       /* set mac loopback */
+       ctrl = er32(RCTL);
+       ctrl |= E1000_RCTL_LBM_MAC;
+       ew32(RCTL, ctrl);
+
+       /* set testing mode parameters (no need to reset later) */
+#define KMRNCTRLSTA_OPMODE (0x1F << 16)
+#define KMRNCTRLSTA_OPMODE_1GB_FD_GMII 0x0582
+       ew32(KMRNCTRLSTA,
+            (KMRNCTRLSTA_OPMODE | KMRNCTRLSTA_OPMODE_1GB_FD_GMII));
+
+       return 0;
+}
+
+static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       u32 rctl;
+
+       if (hw->phy.media_type == e1000_media_type_fiber ||
+           hw->phy.media_type == e1000_media_type_internal_serdes) {
+               switch (hw->mac.type) {
+               case e1000_80003es2lan:
+                       return e1000_set_es2lan_mac_loopback(adapter);
+                       break;
+               case e1000_82571:
+               case e1000_82572:
+                       return e1000_set_82571_fiber_loopback(adapter);
+                       break;
+               default:
+                       rctl = er32(RCTL);
+                       rctl |= E1000_RCTL_LBM_TCVR;
+                       ew32(RCTL, rctl);
+                       return 0;
+               }
+       } else if (hw->phy.media_type == e1000_media_type_copper) {
+               return e1000_integrated_phy_loopback(adapter);
+       }
+
+       return 7;
+}
+
+static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       u32 rctl;
+       u16 phy_reg;
+
+       rctl = er32(RCTL);
+       rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
+       ew32(RCTL, rctl);
+
+       switch (hw->mac.type) {
+       case e1000_80003es2lan:
+               if (hw->phy.media_type == e1000_media_type_fiber ||
+                   hw->phy.media_type == e1000_media_type_internal_serdes) {
+                       /* restore CTRL_EXT, stealing space from tx_fifo_head */
+                       ew32(CTRL_EXT, adapter->tx_fifo_head);
+                       adapter->tx_fifo_head = 0;
+               }
+               /* fall through */
+       case e1000_82571:
+       case e1000_82572:
+               if (hw->phy.media_type == e1000_media_type_fiber ||
+                   hw->phy.media_type == e1000_media_type_internal_serdes) {
+#define E1000_SERDES_LB_OFF 0x400
+                       ew32(SCTL, E1000_SERDES_LB_OFF);
+                       msleep(10);
+                       break;
+               }
+               /* Fall Through */
+       default:
+               hw->mac.autoneg = 1;
+               if (hw->phy.type == e1000_phy_gg82563)
+                       e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x180);
+               e1e_rphy(hw, PHY_CONTROL, &phy_reg);
+               if (phy_reg & MII_CR_LOOPBACK) {
+                       phy_reg &= ~MII_CR_LOOPBACK;
+                       e1e_wphy(hw, PHY_CONTROL, phy_reg);
+                       e1000e_commit_phy(hw);
+               }
+               break;
+       }
+}
+
+static void e1000_create_lbtest_frame(struct sk_buff *skb,
+                                     unsigned int frame_size)
+{
+       memset(skb->data, 0xFF, frame_size);
+       frame_size &= ~1;
+       memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
+       memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
+       memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
+}
+
+static int e1000_check_lbtest_frame(struct sk_buff *skb,
+                                   unsigned int frame_size)
+{
+       frame_size &= ~1;
+       if (*(skb->data + 3) == 0xFF)
+               if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
+                  (*(skb->data + frame_size / 2 + 12) == 0xAF))
+                       return 0;
+       return 13;
+}
+
+static int e1000_run_loopback_test(struct e1000_adapter *adapter)
+{
+       struct e1000_ring *tx_ring = &adapter->test_tx_ring;
+       struct e1000_ring *rx_ring = &adapter->test_rx_ring;
+       struct pci_dev *pdev = adapter->pdev;
+       struct e1000_hw *hw = &adapter->hw;
+       int i, j, k, l;
+       int lc;
+       int good_cnt;
+       int ret_val = 0;
+       unsigned long time;
+
+       ew32(RDT, rx_ring->count - 1);
+
+       /*
+        * Calculate the loop count based on the largest descriptor ring
+        * The idea is to wrap the largest ring a number of times using 64
+        * send/receive pairs during each loop
+        */
+
+       if (rx_ring->count <= tx_ring->count)
+               lc = ((tx_ring->count / 64) * 2) + 1;
+       else
+               lc = ((rx_ring->count / 64) * 2) + 1;
+
+       k = 0;
+       l = 0;
+       for (j = 0; j <= lc; j++) { /* loop count loop */
+               for (i = 0; i < 64; i++) { /* send the packets */
+                       e1000_create_lbtest_frame(tx_ring->buffer_info[k].skb,
+                                                 1024);
+                       pci_dma_sync_single_for_device(pdev,
+                                       tx_ring->buffer_info[k].dma,
+                                       tx_ring->buffer_info[k].length,
+                                       PCI_DMA_TODEVICE);
+                       k++;
+                       if (k == tx_ring->count)
+                               k = 0;
+               }
+               ew32(TDT, k);
+               msleep(200);
+               time = jiffies; /* set the start time for the receive */
+               good_cnt = 0;
+               do { /* receive the sent packets */
+                       pci_dma_sync_single_for_cpu(pdev,
+                                       rx_ring->buffer_info[l].dma, 2048,
+                                       PCI_DMA_FROMDEVICE);
+
+                       ret_val = e1000_check_lbtest_frame(
+                                       rx_ring->buffer_info[l].skb, 1024);
+                       if (!ret_val)
+                               good_cnt++;
+                       l++;
+                       if (l == rx_ring->count)
+                               l = 0;
+                       /*
+                        * time + 20 msecs (200 msecs on 2.4) is more than
+                        * enough time to complete the receives, if it's
+                        * exceeded, break and error off
+                        */
+               } while (good_cnt < 64 && jiffies < (time + 20));
+               if (good_cnt != 64) {
+                       ret_val = 13; /* ret_val is the same as mis-compare */
+                       break;
+               }
+               if (jiffies >= (time + 20)) {
+                       ret_val = 14; /* error code for time out error */
+                       break;
+               }
+       } /* end loop count loop */
+       return ret_val;
+}
+
+static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
+{
+       /*
+        * PHY loopback cannot be performed if SoL/IDER
+        * sessions are active
+        */
+       if (e1000_check_reset_block(&adapter->hw)) {
+               e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
+               *data = 0;
+               goto out;
+       }
+
+       *data = e1000_setup_desc_rings(adapter);
+       if (*data)
+               goto out;
+
+       *data = e1000_setup_loopback_test(adapter);
+       if (*data)
+               goto err_loopback;
+
+       *data = e1000_run_loopback_test(adapter);
+       e1000_loopback_cleanup(adapter);
+
+err_loopback:
+       e1000_free_desc_rings(adapter);
+out:
+       return *data;
+}
+
+static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
+{
+       struct e1000_hw *hw = &adapter->hw;
+
+       *data = 0;
+       if (hw->phy.media_type == e1000_media_type_internal_serdes) {
+               int i = 0;
+               hw->mac.serdes_has_link = 0;
+
+               /*
+                * On some blade server designs, link establishment
+                * could take as long as 2-3 minutes
+                */
+               do {
+                       hw->mac.ops.check_for_link(hw);
+                       if (hw->mac.serdes_has_link)
+                               return *data;
+                       msleep(20);
+               } while (i++ < 3750);
+
+               *data = 1;
+       } else {
+               hw->mac.ops.check_for_link(hw);
+               if (hw->mac.autoneg)
+                       msleep(4000);
+
+               if (!(er32(STATUS) &
+                     E1000_STATUS_LU))
+                       *data = 1;
+       }
+       return *data;
+}
+
+static int e1000_diag_test_count(struct net_device *netdev)
+{
+       return E1000_TEST_LEN;
+}
+
+static void e1000_diag_test(struct net_device *netdev,
+                           struct ethtool_test *eth_test, u64 *data)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       u16 autoneg_advertised;
+       u8 forced_speed_duplex;
+       u8 autoneg;
+       int if_running = netif_running(netdev);
+
+       set_bit(__E1000_TESTING, &adapter->state);
+       if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
+               /* Offline tests */
+
+               /* save speed, duplex, autoneg settings */
+               autoneg_advertised = adapter->hw.phy.autoneg_advertised;
+               forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
+               autoneg = adapter->hw.mac.autoneg;
+
+               e_info("offline testing starting\n");
+
+               /*
+                * Link test performed before hardware reset so autoneg doesn't
+                * interfere with test result
+                */
+               if (e1000_link_test(adapter, &data[4]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               if (if_running)
+                       /* indicate we're in test mode */
+                       dev_close(netdev);
+               else
+                       e1000e_reset(adapter);
+
+               if (e1000_reg_test(adapter, &data[0]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               e1000e_reset(adapter);
+               if (e1000_eeprom_test(adapter, &data[1]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               e1000e_reset(adapter);
+               if (e1000_intr_test(adapter, &data[2]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               e1000e_reset(adapter);
+               /* make sure the phy is powered up */
+               e1000e_power_up_phy(adapter);
+               if (e1000_loopback_test(adapter, &data[3]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               /* restore speed, duplex, autoneg settings */
+               adapter->hw.phy.autoneg_advertised = autoneg_advertised;
+               adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
+               adapter->hw.mac.autoneg = autoneg;
+
+               /* force this routine to wait until autoneg complete/timeout */
+               adapter->hw.phy.autoneg_wait_to_complete = 1;
+               e1000e_reset(adapter);
+               adapter->hw.phy.autoneg_wait_to_complete = 0;
+
+               clear_bit(__E1000_TESTING, &adapter->state);
+               if (if_running)
+                       dev_open(netdev);
+       } else {
+               e_info("online testing starting\n");
+               /* Online tests */
+               if (e1000_link_test(adapter, &data[4]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               /* Online tests aren't run; pass by default */
+               data[0] = 0;
+               data[1] = 0;
+               data[2] = 0;
+               data[3] = 0;
+
+               clear_bit(__E1000_TESTING, &adapter->state);
+       }
+       msleep_interruptible(4 * 1000);
+}
+
+static void e1000_get_wol(struct net_device *netdev,
+                         struct ethtool_wolinfo *wol)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+
+       wol->supported = 0;
+       wol->wolopts = 0;
+
+       if (!(adapter->flags & FLAG_HAS_WOL))
+               return;
+
+       wol->supported = WAKE_UCAST | WAKE_MCAST |
+                        WAKE_BCAST | WAKE_MAGIC |
+                        WAKE_PHY | WAKE_ARP;
+
+       /* apply any specific unsupported masks here */
+       if (adapter->flags & FLAG_NO_WAKE_UCAST) {
+               wol->supported &= ~WAKE_UCAST;
+
+               if (adapter->wol & E1000_WUFC_EX)
+                       e_err("Interface does not support directed (unicast) "
+                             "frame wake-up packets\n");
+       }
+
+       if (adapter->wol & E1000_WUFC_EX)
+               wol->wolopts |= WAKE_UCAST;
+       if (adapter->wol & E1000_WUFC_MC)
+               wol->wolopts |= WAKE_MCAST;
+       if (adapter->wol & E1000_WUFC_BC)
+               wol->wolopts |= WAKE_BCAST;
+       if (adapter->wol & E1000_WUFC_MAG)
+               wol->wolopts |= WAKE_MAGIC;
+       if (adapter->wol & E1000_WUFC_LNKC)
+               wol->wolopts |= WAKE_PHY;
+       if (adapter->wol & E1000_WUFC_ARP)
+               wol->wolopts |= WAKE_ARP;
+       if (adapter->wol & E1000_WUFC_LNKC)
+               wol->wolopts |= WAKE_PHY;
+       if (adapter->wol & E1000_WUFC_ARP)
+               wol->wolopts |= WAKE_ARP;
+}
+
+static int e1000_set_wol(struct net_device *netdev,
+                        struct ethtool_wolinfo *wol)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+
+       if (wol->wolopts & WAKE_MAGICSECURE)
+               return -EOPNOTSUPP;
+
+       if (!(adapter->flags & FLAG_HAS_WOL))
+               return wol->wolopts ? -EOPNOTSUPP : 0;
+
+       /* these settings will always override what we currently have */
+       adapter->wol = 0;
+
+       if (wol->wolopts & WAKE_UCAST)
+               adapter->wol |= E1000_WUFC_EX;
+       if (wol->wolopts & WAKE_MCAST)
+               adapter->wol |= E1000_WUFC_MC;
+       if (wol->wolopts & WAKE_BCAST)
+               adapter->wol |= E1000_WUFC_BC;
+       if (wol->wolopts & WAKE_MAGIC)
+               adapter->wol |= E1000_WUFC_MAG;
+       if (wol->wolopts & WAKE_PHY)
+               adapter->wol |= E1000_WUFC_LNKC;
+       if (wol->wolopts & WAKE_ARP)
+               adapter->wol |= E1000_WUFC_ARP;
+
+       return 0;
+}
+
+/* toggle LED 4 times per second = 2 "blinks" per second */
+#define E1000_ID_INTERVAL      (HZ/4)
+
+/* bit defines for adapter->led_status */
+#define E1000_LED_ON           0
+
+static void e1000_led_blink_callback(unsigned long data)
+{
+       struct e1000_adapter *adapter = (struct e1000_adapter *) data;
+
+       if (test_and_change_bit(E1000_LED_ON, &adapter->led_status))
+               adapter->hw.mac.ops.led_off(&adapter->hw);
+       else
+               adapter->hw.mac.ops.led_on(&adapter->hw);
+
+       mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
+}
+
+static int e1000_phys_id(struct net_device *netdev, u32 data)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+
+       if (!data)
+               data = INT_MAX;
+
+       if ((hw->phy.type == e1000_phy_ife) ||
+           (hw->mac.type == e1000_82574)) {
+               if (!adapter->blink_timer.function) {
+                       init_timer(&adapter->blink_timer);
+                       adapter->blink_timer.function =
+                               e1000_led_blink_callback;
+                       adapter->blink_timer.data = (unsigned long) adapter;
+               }
+               mod_timer(&adapter->blink_timer, jiffies);
+               msleep_interruptible(data * 1000);
+               del_timer_sync(&adapter->blink_timer);
+               if (hw->phy.type == e1000_phy_ife)
+                       e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
+       } else {
+               e1000e_blink_led(hw);
+               msleep_interruptible(data * 1000);
+       }
+
+       hw->mac.ops.led_off(hw);
+       clear_bit(E1000_LED_ON, &adapter->led_status);
+       hw->mac.ops.cleanup_led(hw);
+
+       return 0;
+}
+
+static int e1000_get_coalesce(struct net_device *netdev,
+                             struct ethtool_coalesce *ec)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+
+       if (adapter->itr_setting <= 3)
+               ec->rx_coalesce_usecs = adapter->itr_setting;
+       else
+               ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
+
+       return 0;
+}
+
+static int e1000_set_coalesce(struct net_device *netdev,
+                             struct ethtool_coalesce *ec)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       struct e1000_hw *hw = &adapter->hw;
+
+       if ((ec->rx_coalesce_usecs > E1000_MAX_ITR_USECS) ||
+           ((ec->rx_coalesce_usecs > 3) &&
+            (ec->rx_coalesce_usecs < E1000_MIN_ITR_USECS)) ||
+           (ec->rx_coalesce_usecs == 2))
+               return -EINVAL;
+
+       if (ec->rx_coalesce_usecs <= 3) {
+               adapter->itr = 20000;
+               adapter->itr_setting = ec->rx_coalesce_usecs;
+       } else {
+               adapter->itr = (1000000 / ec->rx_coalesce_usecs);
+               adapter->itr_setting = adapter->itr & ~3;
+       }
+
+       if (adapter->itr_setting != 0)
+               ew32(ITR, 1000000000 / (adapter->itr * 256));
+       else
+               ew32(ITR, 0);
+
+       return 0;
+}
+
+static int e1000_nway_reset(struct net_device *netdev)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       if (netif_running(netdev))
+               e1000e_reinit_locked(adapter);
+       return 0;
+}
+
+static int e1000_get_stats_count(struct net_device *netdev)
+{
+       return E1000_STATS_LEN;
+}
+
+static void e1000_get_ethtool_stats(struct net_device *netdev,
+                                   struct ethtool_stats *stats,
+                                   u64 *data)
+{
+       struct e1000_adapter *adapter = netdev_priv(netdev);
+       int i;
+
+       e1000e_update_stats(adapter);
+       for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
+               char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
+               data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
+                       sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+       }
+}
+
+static void e1000_get_strings(struct net_device *netdev, u32 stringset,
+                             u8 *data)
+{
+       u8 *p = data;
+       int i;
+
+       switch (stringset) {
+       case ETH_SS_TEST:
+               memcpy(data, *e1000_gstrings_test, 
E1000_TEST_LEN*ETH_GSTRING_LEN);
+               break;
+       case ETH_SS_STATS:
+               for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
+                       memcpy(p, e1000_gstrings_stats[i].stat_string,
+                              ETH_GSTRING_LEN);
+                       p += ETH_GSTRING_LEN;
+               }
+               break;
+       }
+}
+
+static struct ethtool_ops e1000_ethtool_ops = {
+       .get_settings           = e1000_get_settings,
+       .set_settings           = e1000_set_settings,
+       .get_drvinfo            = e1000_get_drvinfo,
+       .get_regs_len           = e1000_get_regs_len,
+       .get_regs               = e1000_get_regs,
+       .get_wol                = e1000_get_wol,
+       .set_wol                = e1000_set_wol,
+       .get_msglevel           = e1000_get_msglevel,
+       .set_msglevel           = e1000_set_msglevel,
+       .nway_reset             = e1000_nway_reset,
+       .get_link               = e1000_get_link,
+       .get_eeprom_len         = e1000_get_eeprom_len,
+       .get_eeprom             = e1000_get_eeprom,
+       .set_eeprom             = e1000_set_eeprom,
+       .get_ringparam          = e1000_get_ringparam,
+       .set_ringparam          = e1000_set_ringparam,
+       .get_pauseparam         = e1000_get_pauseparam,
+       .set_pauseparam         = e1000_set_pauseparam,
+       .get_rx_csum            = e1000_get_rx_csum,
+       .set_rx_csum            = e1000_set_rx_csum,
+       .get_tx_csum            = e1000_get_tx_csum,
+       .set_tx_csum            = e1000_set_tx_csum,
+       .get_sg                 = ethtool_op_get_sg,
+       .set_sg                 = ethtool_op_set_sg,
+       .get_tso                = ethtool_op_get_tso,
+       .set_tso                = e1000_set_tso,
+       .self_test_count        = e1000_diag_test_count,
+       .self_test              = e1000_diag_test,
+       .get_strings            = e1000_get_strings,
+       .phys_id                = e1000_phys_id,
+       .get_stats_count        = e1000_get_stats_count,
+       .get_ethtool_stats      = e1000_get_ethtool_stats,
+       .get_coalesce           = e1000_get_coalesce,
+       .set_coalesce           = e1000_set_coalesce,
+};
+
+void e1000e_set_ethtool_ops(struct net_device *netdev)
+{
+       SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
+}
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/hw.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/hw.h   Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,903 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _E1000_HW_H_
+#define _E1000_HW_H_
+
+#include <linux/types.h>
+
+struct e1000_hw;
+struct e1000_adapter;
+
+#include "defines.h"
+
+#define er32(reg)      __er32(hw, E1000_##reg)
+#define ew32(reg,val)  __ew32(hw, E1000_##reg, (val))
+#define e1e_flush()    er32(STATUS)
+
+#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
+       (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
+
+#define E1000_READ_REG_ARRAY(a, reg, offset) \
+       (readl((a)->hw_addr + reg + ((offset) << 2)))
+
+enum e1e_registers {
+       E1000_CTRL     = 0x00000, /* Device Control - RW */
+       E1000_STATUS   = 0x00008, /* Device Status - RO */
+       E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
+       E1000_EERD     = 0x00014, /* EEPROM Read - RW */
+       E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
+       E1000_FLA      = 0x0001C, /* Flash Access - RW */
+       E1000_MDIC     = 0x00020, /* MDI Control - RW */
+       E1000_SCTL     = 0x00024, /* SerDes Control - RW */
+       E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
+       E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
+       E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
+       E1000_FCT      = 0x00030, /* Flow Control Type - RW */
+       E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
+       E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
+       E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
+       E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
+       E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
+       E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
+       E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
+       E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
+       E1000_IVAR     = 0x000E4, /* Interrupt Vector Allocation - RW */
+       E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
+#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
+       E1000_RCTL     = 0x00100, /* Rx Control - RW */
+       E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
+       E1000_TXCW     = 0x00178, /* Tx Configuration Word - RW */
+       E1000_RXCW     = 0x00180, /* Rx Configuration Word - RO */
+       E1000_TCTL     = 0x00400, /* Tx Control - RW */
+       E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
+       E1000_TIPG     = 0x00410, /* Tx Inter-packet gap -RW */
+       E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
+       E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
+       E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
+       E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
+       E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
+       E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
+       E1000_PBS      = 0x01008, /* Packet Buffer Size */
+       E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
+       E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
+       E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
+       E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
+       E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
+       E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
+       E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
+       E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
+       E1000_RDBAL    = 0x02800, /* Rx Descriptor Base Address Low - RW */
+       E1000_RDBAH    = 0x02804, /* Rx Descriptor Base Address High - RW */
+       E1000_RDLEN    = 0x02808, /* Rx Descriptor Length - RW */
+       E1000_RDH      = 0x02810, /* Rx Descriptor Head - RW */
+       E1000_RDT      = 0x02818, /* Rx Descriptor Tail - RW */
+       E1000_RDTR     = 0x02820, /* Rx Delay Timer - RW */
+       E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
+#define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
+       E1000_RADV     = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
+
+/* Convenience macros
+ *
+ * Note: "_n" is the queue number of the register to be written to.
+ *
+ * Example usage:
+ * E1000_RDBAL_REG(current_rx_queue)
+ *
+ */
+#define E1000_RDBAL_REG(_n)   (E1000_RDBAL + (_n << 8))
+       E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
+       E1000_TDBAL    = 0x03800, /* Tx Descriptor Base Address Low - RW */
+       E1000_TDBAH    = 0x03804, /* Tx Descriptor Base Address High - RW */
+       E1000_TDLEN    = 0x03808, /* Tx Descriptor Length - RW */
+       E1000_TDH      = 0x03810, /* Tx Descriptor Head - RW */
+       E1000_TDT      = 0x03818, /* Tx Descriptor Tail - RW */
+       E1000_TIDV     = 0x03820, /* Tx Interrupt Delay Value - RW */
+       E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
+#define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
+       E1000_TADV     = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
+       E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
+#define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
+       E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
+       E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
+       E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
+       E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
+       E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
+       E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
+       E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
+       E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
+       E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
+       E1000_COLC     = 0x04028, /* Collision Count - R/clr */
+       E1000_DC       = 0x04030, /* Defer Count - R/clr */
+       E1000_TNCRS    = 0x04034, /* Tx-No CRS - R/clr */
+       E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
+       E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
+       E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
+       E1000_XONRXC   = 0x04048, /* XON Rx Count - R/clr */
+       E1000_XONTXC   = 0x0404C, /* XON Tx Count - R/clr */
+       E1000_XOFFRXC  = 0x04050, /* XOFF Rx Count - R/clr */
+       E1000_XOFFTXC  = 0x04054, /* XOFF Tx Count - R/clr */
+       E1000_FCRUC    = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
+       E1000_PRC64    = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
+       E1000_PRC127   = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
+       E1000_PRC255   = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
+       E1000_PRC511   = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
+       E1000_PRC1023  = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
+       E1000_PRC1522  = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
+       E1000_GPRC     = 0x04074, /* Good Packets Rx Count - R/clr */
+       E1000_BPRC     = 0x04078, /* Broadcast Packets Rx Count - R/clr */
+       E1000_MPRC     = 0x0407C, /* Multicast Packets Rx Count - R/clr */
+       E1000_GPTC     = 0x04080, /* Good Packets Tx Count - R/clr */
+       E1000_GORCL    = 0x04088, /* Good Octets Rx Count Low - R/clr */
+       E1000_GORCH    = 0x0408C, /* Good Octets Rx Count High - R/clr */
+       E1000_GOTCL    = 0x04090, /* Good Octets Tx Count Low - R/clr */
+       E1000_GOTCH    = 0x04094, /* Good Octets Tx Count High - R/clr */
+       E1000_RNBC     = 0x040A0, /* Rx No Buffers Count - R/clr */
+       E1000_RUC      = 0x040A4, /* Rx Undersize Count - R/clr */
+       E1000_RFC      = 0x040A8, /* Rx Fragment Count - R/clr */
+       E1000_ROC      = 0x040AC, /* Rx Oversize Count - R/clr */
+       E1000_RJC      = 0x040B0, /* Rx Jabber Count - R/clr */
+       E1000_MGTPRC   = 0x040B4, /* Management Packets Rx Count - R/clr */
+       E1000_MGTPDC   = 0x040B8, /* Management Packets Dropped Count - R/clr */
+       E1000_MGTPTC   = 0x040BC, /* Management Packets Tx Count - R/clr */
+       E1000_TORL     = 0x040C0, /* Total Octets Rx Low - R/clr */
+       E1000_TORH     = 0x040C4, /* Total Octets Rx High - R/clr */
+       E1000_TOTL     = 0x040C8, /* Total Octets Tx Low - R/clr */
+       E1000_TOTH     = 0x040CC, /* Total Octets Tx High - R/clr */
+       E1000_TPR      = 0x040D0, /* Total Packets Rx - R/clr */
+       E1000_TPT      = 0x040D4, /* Total Packets Tx - R/clr */
+       E1000_PTC64    = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
+       E1000_PTC127   = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
+       E1000_PTC255   = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
+       E1000_PTC511   = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
+       E1000_PTC1023  = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
+       E1000_PTC1522  = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
+       E1000_MPTC     = 0x040F0, /* Multicast Packets Tx Count - R/clr */
+       E1000_BPTC     = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
+       E1000_TSCTC    = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
+       E1000_TSCTFC   = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
+       E1000_IAC      = 0x04100, /* Interrupt Assertion Count */
+       E1000_ICRXPTC  = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
+       E1000_ICRXATC  = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
+       E1000_ICTXPTC  = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
+       E1000_ICTXATC  = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
+       E1000_ICTXQEC  = 0x04118, /* Irq Cause Tx Queue Empty Count */
+       E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
+       E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
+       E1000_ICRXOC   = 0x04124, /* Irq Cause Receiver Overrun Count */
+       E1000_RXCSUM   = 0x05000, /* Rx Checksum Control - RW */
+       E1000_RFCTL    = 0x05008, /* Receive Filter Control */
+       E1000_MTA      = 0x05200, /* Multicast Table Array - RW Array */
+       E1000_RA       = 0x05400, /* Receive Address - RW Array */
+       E1000_VFTA     = 0x05600, /* VLAN Filter Table Array - RW Array */
+       E1000_WUC      = 0x05800, /* Wakeup Control - RW */
+       E1000_WUFC     = 0x05808, /* Wakeup Filter Control - RW */
+       E1000_WUS      = 0x05810, /* Wakeup Status - RO */
+       E1000_MANC     = 0x05820, /* Management Control - RW */
+       E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
+       E1000_HOST_IF  = 0x08800, /* Host Interface */
+
+       E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
+       E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
+       E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
+       E1000_GCR       = 0x05B00, /* PCI-Ex Control */
+       E1000_FACTPS    = 0x05B30, /* Function Active and Power State to MNG */
+       E1000_SWSM      = 0x05B50, /* SW Semaphore */
+       E1000_FWSM      = 0x05B54, /* FW Semaphore */
+       E1000_HICR      = 0x08F00, /* Host Interface Control */
+};
+
+/* RSS registers */
+
+/* IGP01E1000 Specific Registers */
+#define IGP01E1000_PHY_PORT_CONFIG     0x10 /* Port Config */
+#define IGP01E1000_PHY_PORT_STATUS     0x11 /* Status */
+#define IGP01E1000_PHY_PORT_CTRL       0x12 /* Control */
+#define IGP01E1000_PHY_LINK_HEALTH     0x13 /* PHY Link Health */
+#define IGP02E1000_PHY_POWER_MGMT      0x19 /* Power Management */
+#define IGP01E1000_PHY_PAGE_SELECT     0x1F /* Page Select */
+#define BM_PHY_PAGE_SELECT             22   /* Page Select for BM */
+#define IGP_PAGE_SHIFT                 5
+#define PHY_REG_MASK                   0x1F
+
+#define BM_WUC_PAGE                    800
+#define BM_WUC_ADDRESS_OPCODE          0x11
+#define BM_WUC_DATA_OPCODE             0x12
+#define BM_WUC_ENABLE_PAGE             769
+#define BM_WUC_ENABLE_REG              17
+#define BM_WUC_ENABLE_BIT              (1 << 2)
+#define BM_WUC_HOST_WU_BIT             (1 << 4)
+
+#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
+#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
+#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
+
+#define IGP01E1000_PHY_PCS_INIT_REG    0x00B4
+#define IGP01E1000_PHY_POLARITY_MASK   0x0078
+
+#define IGP01E1000_PSCR_AUTO_MDIX      0x1000
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
+
+#define IGP01E1000_PSCFR_SMART_SPEED   0x0080
+
+#define IGP02E1000_PM_SPD              0x0001 /* Smart Power Down */
+#define IGP02E1000_PM_D0_LPLU          0x0002 /* For D0a states */
+#define IGP02E1000_PM_D3_LPLU          0x0004 /* For all other states */
+
+#define IGP01E1000_PLHR_SS_DOWNGRADE   0x8000
+
+#define IGP01E1000_PSSR_POLARITY_REVERSED      0x0002
+#define IGP01E1000_PSSR_MDIX                   0x0008
+#define IGP01E1000_PSSR_SPEED_MASK             0xC000
+#define IGP01E1000_PSSR_SPEED_1000MBPS         0xC000
+
+#define IGP02E1000_PHY_CHANNEL_NUM             4
+#define IGP02E1000_PHY_AGC_A                   0x11B1
+#define IGP02E1000_PHY_AGC_B                   0x12B1
+#define IGP02E1000_PHY_AGC_C                   0x14B1
+#define IGP02E1000_PHY_AGC_D                   0x18B1
+
+#define IGP02E1000_AGC_LENGTH_SHIFT    9 /* Course - 15:13, Fine - 12:9 */
+#define IGP02E1000_AGC_LENGTH_MASK     0x7F
+#define IGP02E1000_AGC_RANGE           15
+
+/* manage.c */
+#define E1000_VFTA_ENTRY_SHIFT         5
+#define E1000_VFTA_ENTRY_MASK          0x7F
+#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK        0x1F
+
+#define E1000_HICR_EN                  0x01  /* Enable bit - RO */
+/* Driver sets this bit when done to put command in RAM */
+#define E1000_HICR_C                   0x02
+#define E1000_HICR_FW_RESET_ENABLE     0x40
+#define E1000_HICR_FW_RESET            0x80
+
+#define E1000_FWSM_MODE_MASK           0xE
+#define E1000_FWSM_MODE_SHIFT          1
+
+#define E1000_MNG_IAMT_MODE            0x3
+#define E1000_MNG_DHCP_COOKIE_LENGTH   0x10
+#define E1000_MNG_DHCP_COOKIE_OFFSET   0x6F0
+#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
+#define E1000_MNG_DHCP_TX_PAYLOAD_CMD  64
+#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING   0x1
+#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN      0x2
+
+/* nvm.c */
+#define E1000_STM_OPCODE  0xDB00
+
+#define E1000_KMRNCTRLSTA_OFFSET       0x001F0000
+#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
+#define E1000_KMRNCTRLSTA_REN          0x00200000
+#define E1000_KMRNCTRLSTA_DIAG_OFFSET  0x3    /* Kumeran Diagnostic */
+#define E1000_KMRNCTRLSTA_DIAG_NELPBK  0x1000 /* Nearend Loopback mode */
+
+#define IFE_PHY_EXTENDED_STATUS_CONTROL        0x10
+#define IFE_PHY_SPECIAL_CONTROL                0x11 /* 100BaseTx PHY Special 
Control */
+#define IFE_PHY_SPECIAL_CONTROL_LED    0x1B /* PHY Special and LED Control */
+#define IFE_PHY_MDIX_CONTROL           0x1C /* MDI/MDI-X Control */
+
+/* IFE PHY Extended Status Control */
+#define IFE_PESC_POLARITY_REVERSED     0x0100
+
+/* IFE PHY Special Control */
+#define IFE_PSC_AUTO_POLARITY_DISABLE          0x0010
+#define IFE_PSC_FORCE_POLARITY                 0x0020
+
+/* IFE PHY Special Control and LED Control */
+#define IFE_PSCL_PROBE_MODE            0x0020
+#define IFE_PSCL_PROBE_LEDS_OFF                0x0006 /* Force LEDs 0 and 2 
off */
+#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
+
+/* IFE PHY MDIX Control */
+#define IFE_PMC_MDIX_STATUS    0x0020 /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_FORCE_MDIX     0x0040 /* 1=force MDI-X, 0=force MDI */
+#define IFE_PMC_AUTO_MDIX      0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
+
+#define E1000_CABLE_LENGTH_UNDEFINED   0xFF
+
+#define E1000_DEV_ID_82571EB_COPPER            0x105E
+#define E1000_DEV_ID_82571EB_FIBER             0x105F
+#define E1000_DEV_ID_82571EB_SERDES            0x1060
+#define E1000_DEV_ID_82571EB_QUAD_COPPER       0x10A4
+#define E1000_DEV_ID_82571PT_QUAD_COPPER       0x10D5
+#define E1000_DEV_ID_82571EB_QUAD_FIBER                0x10A5
+#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP    0x10BC
+#define E1000_DEV_ID_82571EB_SERDES_DUAL       0x10D9
+#define E1000_DEV_ID_82571EB_SERDES_QUAD       0x10DA
+#define E1000_DEV_ID_82572EI_COPPER            0x107D
+#define E1000_DEV_ID_82572EI_FIBER             0x107E
+#define E1000_DEV_ID_82572EI_SERDES            0x107F
+#define E1000_DEV_ID_82572EI                   0x10B9
+#define E1000_DEV_ID_82573E                    0x108B
+#define E1000_DEV_ID_82573E_IAMT               0x108C
+#define E1000_DEV_ID_82573L                    0x109A
+#define E1000_DEV_ID_82574L                    0x10D3
+
+#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT    0x1096
+#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT    0x1098
+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT    0x10BA
+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT    0x10BB
+
+#define E1000_DEV_ID_ICH8_IGP_M_AMT            0x1049
+#define E1000_DEV_ID_ICH8_IGP_AMT              0x104A
+#define E1000_DEV_ID_ICH8_IGP_C                        0x104B
+#define E1000_DEV_ID_ICH8_IFE                  0x104C
+#define E1000_DEV_ID_ICH8_IFE_GT               0x10C4
+#define E1000_DEV_ID_ICH8_IFE_G                        0x10C5
+#define E1000_DEV_ID_ICH8_IGP_M                        0x104D
+#define E1000_DEV_ID_ICH9_IGP_AMT              0x10BD
+#define E1000_DEV_ID_ICH9_BM                   0x10E5
+#define E1000_DEV_ID_ICH9_IGP_M_AMT            0x10F5
+#define E1000_DEV_ID_ICH9_IGP_M                        0x10BF
+#define E1000_DEV_ID_ICH9_IGP_M_V              0x10CB
+#define E1000_DEV_ID_ICH9_IGP_C                        0x294C
+#define E1000_DEV_ID_ICH9_IFE                  0x10C0
+#define E1000_DEV_ID_ICH9_IFE_GT               0x10C3
+#define E1000_DEV_ID_ICH9_IFE_G                        0x10C2
+#define E1000_DEV_ID_ICH10_R_BM_LM             0x10CC
+#define E1000_DEV_ID_ICH10_R_BM_LF             0x10CD
+#define E1000_DEV_ID_ICH10_R_BM_V              0x10CE
+#define E1000_DEV_ID_ICH10_D_BM_LM             0x10DE
+#define E1000_DEV_ID_ICH10_D_BM_LF             0x10DF
+
+#define E1000_REVISION_4 4
+
+#define E1000_FUNC_1 1
+
+enum e1000_mac_type {
+       e1000_82571,
+       e1000_82572,
+       e1000_82573,
+       e1000_82574,
+       e1000_80003es2lan,
+       e1000_ich8lan,
+       e1000_ich9lan,
+       e1000_ich10lan,
+};
+
+enum e1000_media_type {
+       e1000_media_type_unknown = 0,
+       e1000_media_type_copper = 1,
+       e1000_media_type_fiber = 2,
+       e1000_media_type_internal_serdes = 3,
+       e1000_num_media_types
+};
+
+enum e1000_nvm_type {
+       e1000_nvm_unknown = 0,
+       e1000_nvm_none,
+       e1000_nvm_eeprom_spi,
+       e1000_nvm_flash_hw,
+       e1000_nvm_flash_sw
+};
+
+enum e1000_nvm_override {
+       e1000_nvm_override_none = 0,
+       e1000_nvm_override_spi_small,
+       e1000_nvm_override_spi_large
+};
+
+enum e1000_phy_type {
+       e1000_phy_unknown = 0,
+       e1000_phy_none,
+       e1000_phy_m88,
+       e1000_phy_igp,
+       e1000_phy_igp_2,
+       e1000_phy_gg82563,
+       e1000_phy_igp_3,
+       e1000_phy_ife,
+       e1000_phy_bm,
+};
+
+enum e1000_bus_width {
+       e1000_bus_width_unknown = 0,
+       e1000_bus_width_pcie_x1,
+       e1000_bus_width_pcie_x2,
+       e1000_bus_width_pcie_x4 = 4,
+       e1000_bus_width_32,
+       e1000_bus_width_64,
+       e1000_bus_width_reserved
+};
+
+enum e1000_1000t_rx_status {
+       e1000_1000t_rx_status_not_ok = 0,
+       e1000_1000t_rx_status_ok,
+       e1000_1000t_rx_status_undefined = 0xFF
+};
+
+enum e1000_rev_polarity{
+       e1000_rev_polarity_normal = 0,
+       e1000_rev_polarity_reversed,
+       e1000_rev_polarity_undefined = 0xFF
+};
+
+enum e1000_fc_type {
+       e1000_fc_none = 0,
+       e1000_fc_rx_pause,
+       e1000_fc_tx_pause,
+       e1000_fc_full,
+       e1000_fc_default = 0xFF
+};
+
+enum e1000_ms_type {
+       e1000_ms_hw_default = 0,
+       e1000_ms_force_master,
+       e1000_ms_force_slave,
+       e1000_ms_auto
+};
+
+enum e1000_smart_speed {
+       e1000_smart_speed_default = 0,
+       e1000_smart_speed_on,
+       e1000_smart_speed_off
+};
+
+/* Receive Descriptor */
+struct e1000_rx_desc {
+       __le64 buffer_addr; /* Address of the descriptor's data buffer */
+       __le16 length;      /* Length of data DMAed into data buffer */
+       __le16 csum;    /* Packet checksum */
+       u8  status;      /* Descriptor status */
+       u8  errors;      /* Descriptor Errors */
+       __le16 special;
+};
+
+/* Receive Descriptor - Extended */
+union e1000_rx_desc_extended {
+       struct {
+               __le64 buffer_addr;
+               __le64 reserved;
+       } read;
+       struct {
+               struct {
+                       __le32 mrq;           /* Multiple Rx Queues */
+                       union {
+                               __le32 rss;         /* RSS Hash */
+                               struct {
+                                       __le16 ip_id;  /* IP id */
+                                       __le16 csum;   /* Packet Checksum */
+                               } csum_ip;
+                       } hi_dword;
+               } lower;
+               struct {
+                       __le32 status_error;     /* ext status/error */
+                       __le16 length;
+                       __le16 vlan;         /* VLAN tag */
+               } upper;
+       } wb;  /* writeback */
+};
+
+#define MAX_PS_BUFFERS 4
+/* Receive Descriptor - Packet Split */
+union e1000_rx_desc_packet_split {
+       struct {
+               /* one buffer for protocol header(s), three data buffers */
+               __le64 buffer_addr[MAX_PS_BUFFERS];
+       } read;
+       struct {
+               struct {
+                       __le32 mrq;           /* Multiple Rx Queues */
+                       union {
+                               __le32 rss;           /* RSS Hash */
+                               struct {
+                                       __le16 ip_id;    /* IP id */
+                                       __le16 csum;     /* Packet Checksum */
+                               } csum_ip;
+                       } hi_dword;
+               } lower;
+               struct {
+                       __le32 status_error;     /* ext status/error */
+                       __le16 length0;   /* length of buffer 0 */
+                       __le16 vlan;         /* VLAN tag */
+               } middle;
+               struct {
+                       __le16 header_status;
+                       __le16 length[3];       /* length of buffers 1-3 */
+               } upper;
+               __le64 reserved;
+       } wb; /* writeback */
+};
+
+/* Transmit Descriptor */
+struct e1000_tx_desc {
+       __le64 buffer_addr;      /* Address of the descriptor's data buffer */
+       union {
+               __le32 data;
+               struct {
+                       __le16 length;    /* Data buffer length */
+                       u8 cso; /* Checksum offset */
+                       u8 cmd; /* Descriptor control */
+               } flags;
+       } lower;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;     /* Descriptor status */
+                       u8 css; /* Checksum start */
+                       __le16 special;
+               } fields;
+       } upper;
+};
+
+/* Offload Context Descriptor */
+struct e1000_context_desc {
+       union {
+               __le32 ip_config;
+               struct {
+                       u8 ipcss;      /* IP checksum start */
+                       u8 ipcso;      /* IP checksum offset */
+                       __le16 ipcse;     /* IP checksum end */
+               } ip_fields;
+       } lower_setup;
+       union {
+               __le32 tcp_config;
+               struct {
+                       u8 tucss;      /* TCP checksum start */
+                       u8 tucso;      /* TCP checksum offset */
+                       __le16 tucse;     /* TCP checksum end */
+               } tcp_fields;
+       } upper_setup;
+       __le32 cmd_and_length;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;     /* Descriptor status */
+                       u8 hdr_len;    /* Header length */
+                       __le16 mss;       /* Maximum segment size */
+               } fields;
+       } tcp_seg_setup;
+};
+
+/* Offload data descriptor */
+struct e1000_data_desc {
+       __le64 buffer_addr;   /* Address of the descriptor's buffer address */
+       union {
+               __le32 data;
+               struct {
+                       __le16 length;    /* Data buffer length */
+                       u8 typ_len_ext;
+                       u8 cmd;
+               } flags;
+       } lower;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;     /* Descriptor status */
+                       u8 popts;      /* Packet Options */
+                       __le16 special;   /* */
+               } fields;
+       } upper;
+};
+
+/* Statistics counters collected by the MAC */
+struct e1000_hw_stats {
+       u64 crcerrs;
+       u64 algnerrc;
+       u64 symerrs;
+       u64 rxerrc;
+       u64 mpc;
+       u64 scc;
+       u64 ecol;
+       u64 mcc;
+       u64 latecol;
+       u64 colc;
+       u64 dc;
+       u64 tncrs;
+       u64 sec;
+       u64 cexterr;
+       u64 rlec;
+       u64 xonrxc;
+       u64 xontxc;
+       u64 xoffrxc;
+       u64 xofftxc;
+       u64 fcruc;
+       u64 prc64;
+       u64 prc127;
+       u64 prc255;
+       u64 prc511;
+       u64 prc1023;
+       u64 prc1522;
+       u64 gprc;
+       u64 bprc;
+       u64 mprc;
+       u64 gptc;
+       u64 gorc;
+       u64 gotc;
+       u64 rnbc;
+       u64 ruc;
+       u64 rfc;
+       u64 roc;
+       u64 rjc;
+       u64 mgprc;
+       u64 mgpdc;
+       u64 mgptc;
+       u64 tor;
+       u64 tot;
+       u64 tpr;
+       u64 tpt;
+       u64 ptc64;
+       u64 ptc127;
+       u64 ptc255;
+       u64 ptc511;
+       u64 ptc1023;
+       u64 ptc1522;
+       u64 mptc;
+       u64 bptc;
+       u64 tsctc;
+       u64 tsctfc;
+       u64 iac;
+       u64 icrxptc;
+       u64 icrxatc;
+       u64 ictxptc;
+       u64 ictxatc;
+       u64 ictxqec;
+       u64 ictxqmtc;
+       u64 icrxdmtc;
+       u64 icrxoc;
+};
+
+struct e1000_phy_stats {
+       u32 idle_errors;
+       u32 receive_errors;
+};
+
+struct e1000_host_mng_dhcp_cookie {
+       u32 signature;
+       u8  status;
+       u8  reserved0;
+       u16 vlan_id;
+       u32 reserved1;
+       u16 reserved2;
+       u8  reserved3;
+       u8  checksum;
+};
+
+/* Host Interface "Rev 1" */
+struct e1000_host_command_header {
+       u8 command_id;
+       u8 command_length;
+       u8 command_options;
+       u8 checksum;
+};
+
+#define E1000_HI_MAX_DATA_LENGTH     252
+struct e1000_host_command_info {
+       struct e1000_host_command_header command_header;
+       u8 command_data[E1000_HI_MAX_DATA_LENGTH];
+};
+
+/* Host Interface "Rev 2" */
+struct e1000_host_mng_command_header {
+       u8  command_id;
+       u8  checksum;
+       u16 reserved1;
+       u16 reserved2;
+       u16 command_length;
+};
+
+#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
+struct e1000_host_mng_command_info {
+       struct e1000_host_mng_command_header command_header;
+       u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
+};
+
+/* Function pointers and static data for the MAC. */
+struct e1000_mac_operations {
+       bool (*check_mng_mode)(struct e1000_hw *);
+       s32  (*check_for_link)(struct e1000_hw *);
+       s32  (*cleanup_led)(struct e1000_hw *);
+       void (*clear_hw_cntrs)(struct e1000_hw *);
+       s32  (*get_bus_info)(struct e1000_hw *);
+       s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
+       s32  (*led_on)(struct e1000_hw *);
+       s32  (*led_off)(struct e1000_hw *);
+       void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
+       s32  (*reset_hw)(struct e1000_hw *);
+       s32  (*init_hw)(struct e1000_hw *);
+       s32  (*setup_link)(struct e1000_hw *);
+       s32  (*setup_physical_interface)(struct e1000_hw *);
+};
+
+/* Function pointers for the PHY. */
+struct e1000_phy_operations {
+       s32  (*acquire_phy)(struct e1000_hw *);
+       s32  (*check_reset_block)(struct e1000_hw *);
+       s32  (*commit_phy)(struct e1000_hw *);
+       s32  (*force_speed_duplex)(struct e1000_hw *);
+       s32  (*get_cfg_done)(struct e1000_hw *hw);
+       s32  (*get_cable_length)(struct e1000_hw *);
+       s32  (*get_phy_info)(struct e1000_hw *);
+       s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
+       void (*release_phy)(struct e1000_hw *);
+       s32  (*reset_phy)(struct e1000_hw *);
+       s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
+       s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
+       s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
+};
+
+/* Function pointers for the NVM. */
+struct e1000_nvm_operations {
+       s32  (*acquire_nvm)(struct e1000_hw *);
+       s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
+       void (*release_nvm)(struct e1000_hw *);
+       s32  (*update_nvm)(struct e1000_hw *);
+       s32  (*valid_led_default)(struct e1000_hw *, u16 *);
+       s32  (*validate_nvm)(struct e1000_hw *);
+       s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
+};
+
+struct e1000_mac_info {
+       struct e1000_mac_operations ops;
+
+       u8 addr[6];
+       u8 perm_addr[6];
+
+       enum e1000_mac_type type;
+
+       u32 collision_delta;
+       u32 ledctl_default;
+       u32 ledctl_mode1;
+       u32 ledctl_mode2;
+       u32 mc_filter_type;
+       u32 tx_packet_delta;
+       u32 txcw;
+
+       u16 current_ifs_val;
+       u16 ifs_max_val;
+       u16 ifs_min_val;
+       u16 ifs_ratio;
+       u16 ifs_step_size;
+       u16 mta_reg_count;
+       u16 rar_entry_count;
+
+       u8  forced_speed_duplex;
+
+       bool arc_subsystem_valid;
+       bool autoneg;
+       bool autoneg_failed;
+       bool get_link_status;
+       bool in_ifs_mode;
+       bool serdes_has_link;
+       bool tx_pkt_filtering;
+};
+
+struct e1000_phy_info {
+       struct e1000_phy_operations ops;
+
+       enum e1000_phy_type type;
+
+       enum e1000_1000t_rx_status local_rx;
+       enum e1000_1000t_rx_status remote_rx;
+       enum e1000_ms_type ms_type;
+       enum e1000_ms_type original_ms_type;
+       enum e1000_rev_polarity cable_polarity;
+       enum e1000_smart_speed smart_speed;
+
+       u32 addr;
+       u32 id;
+       u32 reset_delay_us; /* in usec */
+       u32 revision;
+
+       enum e1000_media_type media_type;
+
+       u16 autoneg_advertised;
+       u16 autoneg_mask;
+       u16 cable_length;
+       u16 max_cable_length;
+       u16 min_cable_length;
+
+       u8 mdix;
+
+       bool disable_polarity_correction;
+       bool is_mdix;
+       bool polarity_correction;
+       bool speed_downgraded;
+       bool autoneg_wait_to_complete;
+};
+
+struct e1000_nvm_info {
+       struct e1000_nvm_operations ops;
+
+       enum e1000_nvm_type type;
+       enum e1000_nvm_override override;
+
+       u32 flash_bank_size;
+       u32 flash_base_addr;
+
+       u16 word_size;
+       u16 delay_usec;
+       u16 address_bits;
+       u16 opcode_bits;
+       u16 page_size;
+};
+
+struct e1000_bus_info {
+       enum e1000_bus_width width;
+
+       u16 func;
+};
+
+struct e1000_fc_info {
+       u32 high_water;          /* Flow control high-water mark */
+       u32 low_water;           /* Flow control low-water mark */
+       u16 pause_time;          /* Flow control pause timer */
+       bool send_xon;           /* Flow control send XON */
+       bool strict_ieee;        /* Strict IEEE mode */
+       enum e1000_fc_type type; /* Type of flow control */
+       enum e1000_fc_type original_type;
+};
+
+struct e1000_dev_spec_82571 {
+       bool laa_is_present;
+       bool alt_mac_addr_is_present;
+};
+
+struct e1000_shadow_ram {
+       u16  value;
+       bool modified;
+};
+
+#define E1000_ICH8_SHADOW_RAM_WORDS            2048
+
+struct e1000_dev_spec_ich8lan {
+       bool kmrn_lock_loss_workaround_enabled;
+       struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
+};
+
+struct e1000_hw {
+       struct e1000_adapter *adapter;
+
+       u8 __iomem *hw_addr;
+       u8 __iomem *flash_address;
+
+       struct e1000_mac_info  mac;
+       struct e1000_fc_info   fc;
+       struct e1000_phy_info  phy;
+       struct e1000_nvm_info  nvm;
+       struct e1000_bus_info  bus;
+       struct e1000_host_mng_dhcp_cookie mng_cookie;
+
+       union {
+               struct e1000_dev_spec_82571     e82571;
+               struct e1000_dev_spec_ich8lan   ich8lan;
+       } dev_spec;
+};
+
+#ifdef DEBUG
+#define hw_dbg(hw, format, arg...) \
+       printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
+#else
+static inline int __attribute__ ((format (printf, 2, 3)))
+hw_dbg(struct e1000_hw *hw, const char *format, ...)
+{
+       return 0;
+}
+#endif
+
+#endif
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/ich8lan.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/ich8lan.c      Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,2568 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/*
+ * 82562G-2 10/100 Network Connection
+ * 82562GT 10/100 Network Connection
+ * 82562GT-2 10/100 Network Connection
+ * 82562V 10/100 Network Connection
+ * 82562V-2 10/100 Network Connection
+ * 82566DC-2 Gigabit Network Connection
+ * 82566DC Gigabit Network Connection
+ * 82566DM-2 Gigabit Network Connection
+ * 82566DM Gigabit Network Connection
+ * 82566MC Gigabit Network Connection
+ * 82566MM Gigabit Network Connection
+ * 82567LM Gigabit Network Connection
+ * 82567LF Gigabit Network Connection
+ * 82567LM-2 Gigabit Network Connection
+ * 82567LF-2 Gigabit Network Connection
+ * 82567V-2 Gigabit Network Connection
+ * 82567LF-3 Gigabit Network Connection
+ * 82567LM-3 Gigabit Network Connection
+ * 82567LM-4 Gigabit Network Connection
+ */
+
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include "e1000.h"
+
+#define ICH_FLASH_GFPREG               0x0000
+#define ICH_FLASH_HSFSTS               0x0004
+#define ICH_FLASH_HSFCTL               0x0006
+#define ICH_FLASH_FADDR                        0x0008
+#define ICH_FLASH_FDATA0               0x0010
+#define ICH_FLASH_PR0                  0x0074
+
+#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT        500
+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT        3000000
+#define ICH_FLASH_LINEAR_ADDR_MASK     0x00FFFFFF
+#define ICH_FLASH_CYCLE_REPEAT_COUNT   10
+
+#define ICH_CYCLE_READ                 0
+#define ICH_CYCLE_WRITE                        2
+#define ICH_CYCLE_ERASE                        3
+
+#define FLASH_GFPREG_BASE_MASK         0x1FFF
+#define FLASH_SECTOR_ADDR_SHIFT                12
+
+#define ICH_FLASH_SEG_SIZE_256         256
+#define ICH_FLASH_SEG_SIZE_4K          4096
+#define ICH_FLASH_SEG_SIZE_8K          8192
+#define ICH_FLASH_SEG_SIZE_64K         65536
+
+
+#define E1000_ICH_FWSM_RSPCIPHY        0x00000040 /* Reset PHY on PCI Reset */
+
+#define E1000_ICH_MNG_IAMT_MODE                0x2
+
+#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
+                                (ID_LED_DEF1_OFF2 <<  8) | \
+                                (ID_LED_DEF1_ON2  <<  4) | \
+                                (ID_LED_DEF1_DEF2))
+
+#define E1000_ICH_NVM_SIG_WORD         0x13
+#define E1000_ICH_NVM_SIG_MASK         0xC000
+
+#define E1000_ICH8_LAN_INIT_TIMEOUT    1500
+
+#define E1000_FEXTNVM_SW_CONFIG                1
+#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ 
*/
+
+#define PCIE_ICH8_SNOOP_ALL            PCIE_NO_SNOOP_ALL
+
+#define E1000_ICH_RAR_ENTRIES          7
+
+#define PHY_PAGE_SHIFT 5
+#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
+                          ((reg) & MAX_PHY_REG_ADDRESS))
+#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
+#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
+
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS   0x0002
+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
+#define IGP3_VR_CTRL_MODE_SHUTDOWN     0x0200
+
+/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
+/* Offset 04h HSFSTS */
+union ich8_hws_flash_status {
+       struct ich8_hsfsts {
+               u16 flcdone    :1; /* bit 0 Flash Cycle Done */
+               u16 flcerr     :1; /* bit 1 Flash Cycle Error */
+               u16 dael       :1; /* bit 2 Direct Access error Log */
+               u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
+               u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
+               u16 reserved1  :2; /* bit 13:6 Reserved */
+               u16 reserved2  :6; /* bit 13:6 Reserved */
+               u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
+               u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
+       } hsf_status;
+       u16 regval;
+};
+
+/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
+/* Offset 06h FLCTL */
+union ich8_hws_flash_ctrl {
+       struct ich8_hsflctl {
+               u16 flcgo      :1;   /* 0 Flash Cycle Go */
+               u16 flcycle    :2;   /* 2:1 Flash Cycle */
+               u16 reserved   :5;   /* 7:3 Reserved  */
+               u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
+               u16 flockdn    :6;   /* 15:10 Reserved */
+       } hsf_ctrl;
+       u16 regval;
+};
+
+/* ICH Flash Region Access Permissions */
+union ich8_hws_flash_regacc {
+       struct ich8_flracc {
+               u32 grra      :8; /* 0:7 GbE region Read Access */
+               u32 grwa      :8; /* 8:15 GbE region Write Access */
+               u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
+               u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
+       } hsf_flregacc;
+       u16 regval;
+};
+
+/* ICH Flash Protected Region */
+union ich8_flash_protected_range {
+       struct ich8_pr {
+               u32 base:13;     /* 0:12 Protected Range Base */
+               u32 reserved1:2; /* 13:14 Reserved */
+               u32 rpe:1;       /* 15 Read Protection Enable */
+               u32 limit:13;    /* 16:28 Protected Range Limit */
+               u32 reserved2:2; /* 29:30 Reserved */
+               u32 wpe:1;       /* 31 Write Protection Enable */
+       } range;
+       u32 regval;
+};
+
+static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
+static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
+static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
+static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
+static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
+static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
+                                               u32 offset, u8 byte);
+static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
+                                        u8 *data);
+static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
+                                        u16 *data);
+static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                        u8 size, u16 *data);
+static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
+static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
+static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
+
+static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
+{
+       return readw(hw->flash_address + reg);
+}
+
+static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
+{
+       return readl(hw->flash_address + reg);
+}
+
+static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
+{
+       writew(val, hw->flash_address + reg);
+}
+
+static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
+{
+       writel(val, hw->flash_address + reg);
+}
+
+#define er16flash(reg)         __er16flash(hw, (reg))
+#define er32flash(reg)         __er32flash(hw, (reg))
+#define ew16flash(reg,val)     __ew16flash(hw, (reg), (val))
+#define ew32flash(reg,val)     __ew32flash(hw, (reg), (val))
+
+/**
+ *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific PHY parameters and function pointers.
+ **/
+static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 i = 0;
+
+       phy->addr                       = 1;
+       phy->reset_delay_us             = 100;
+
+       /*
+        * We may need to do this twice - once for IGP and if that fails,
+        * we'll set BM func pointers and try again
+        */
+       ret_val = e1000e_determine_phy_address(hw);
+       if (ret_val) {
+               hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
+               hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
+               ret_val = e1000e_determine_phy_address(hw);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       phy->id = 0;
+       while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
+              (i++ < 100)) {
+               msleep(1);
+               ret_val = e1000e_get_phy_id(hw);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       /* Verify phy id */
+       switch (phy->id) {
+       case IGP03E1000_E_PHY_ID:
+               phy->type = e1000_phy_igp_3;
+               phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+               break;
+       case IFE_E_PHY_ID:
+       case IFE_PLUS_E_PHY_ID:
+       case IFE_C_E_PHY_ID:
+               phy->type = e1000_phy_ife;
+               phy->autoneg_mask = E1000_ALL_NOT_GIG;
+               break;
+       case BME1000_E_PHY_ID:
+               phy->type = e1000_phy_bm;
+               phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+               hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
+               hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
+               hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
+               break;
+       default:
+               return -E1000_ERR_PHY;
+               break;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific NVM parameters and function
+ *  pointers.
+ **/
+static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 gfpreg;
+       u32 sector_base_addr;
+       u32 sector_end_addr;
+       u16 i;
+
+       /* Can't read flash registers if the register set isn't mapped. */
+       if (!hw->flash_address) {
+               hw_dbg(hw, "ERROR: Flash registers not mapped\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       nvm->type = e1000_nvm_flash_sw;
+
+       gfpreg = er32flash(ICH_FLASH_GFPREG);
+
+       /*
+        * sector_X_addr is a "sector"-aligned address (4096 bytes)
+        * Add 1 to sector_end_addr since this sector is included in
+        * the overall size.
+        */
+       sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
+       sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
+
+       /* flash_base_addr is byte-aligned */
+       nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
+
+       /*
+        * find total size of the NVM, then cut in half since the total
+        * size represents two separate NVM banks.
+        */
+       nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
+                               << FLASH_SECTOR_ADDR_SHIFT;
+       nvm->flash_bank_size /= 2;
+       /* Adjust to word count */
+       nvm->flash_bank_size /= sizeof(u16);
+
+       nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
+
+       /* Clear shadow ram */
+       for (i = 0; i < nvm->word_size; i++) {
+               dev_spec->shadow_ram[i].modified = 0;
+               dev_spec->shadow_ram[i].value    = 0xFFFF;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific MAC parameters and function
+ *  pointers.
+ **/
+static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       struct e1000_mac_info *mac = &hw->mac;
+
+       /* Set media type function pointer */
+       hw->phy.media_type = e1000_media_type_copper;
+
+       /* Set mta register count */
+       mac->mta_reg_count = 32;
+       /* Set rar entry count */
+       mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
+       if (mac->type == e1000_ich8lan)
+               mac->rar_entry_count--;
+       /* Set if manageability features are enabled. */
+       mac->arc_subsystem_valid = 1;
+
+       /* Enable PCS Lock-loss workaround for ICH8 */
+       if (mac->type == e1000_ich8lan)
+               e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
+
+       return 0;
+}
+
+static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
+{
+       struct e1000_hw *hw = &adapter->hw;
+       s32 rc;
+
+       rc = e1000_init_mac_params_ich8lan(adapter);
+       if (rc)
+               return rc;
+
+       rc = e1000_init_nvm_params_ich8lan(hw);
+       if (rc)
+               return rc;
+
+       rc = e1000_init_phy_params_ich8lan(hw);
+       if (rc)
+               return rc;
+
+       if ((adapter->hw.mac.type == e1000_ich8lan) &&
+           (adapter->hw.phy.type == e1000_phy_igp_3))
+               adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
+
+       return 0;
+}
+
+/**
+ *  e1000_acquire_swflag_ich8lan - Acquire software control flag
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquires the software control flag for performing NVM and PHY
+ *  operations.  This is a function pointer entry point only called by
+ *  read/write routines for the PHY and NVM parts.
+ **/
+static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
+{
+       u32 extcnf_ctrl;
+       u32 timeout = PHY_CFG_TIMEOUT;
+
+       while (timeout) {
+               extcnf_ctrl = er32(EXTCNF_CTRL);
+               extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
+               ew32(EXTCNF_CTRL, extcnf_ctrl);
+
+               extcnf_ctrl = er32(EXTCNF_CTRL);
+               if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
+                       break;
+               mdelay(1);
+               timeout--;
+       }
+
+       if (!timeout) {
+               hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_release_swflag_ich8lan - Release software control flag
+ *  @hw: pointer to the HW structure
+ *
+ *  Releases the software control flag for performing NVM and PHY operations.
+ *  This is a function pointer entry point only called by read/write
+ *  routines for the PHY and NVM parts.
+ **/
+static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
+{
+       u32 extcnf_ctrl;
+
+       extcnf_ctrl = er32(EXTCNF_CTRL);
+       extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
+       ew32(EXTCNF_CTRL, extcnf_ctrl);
+}
+
+/**
+ *  e1000_check_mng_mode_ich8lan - Checks management mode
+ *  @hw: pointer to the HW structure
+ *
+ *  This checks if the adapter has manageability enabled.
+ *  This is a function pointer entry point only called by read/write
+ *  routines for the PHY and NVM parts.
+ **/
+static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
+{
+       u32 fwsm = er32(FWSM);
+
+       return (fwsm & E1000_FWSM_MODE_MASK) ==
+               (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
+}
+
+/**
+ *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
+ *  @hw: pointer to the HW structure
+ *
+ *  Checks if firmware is blocking the reset of the PHY.
+ *  This is a function pointer entry point only called by
+ *  reset routines.
+ **/
+static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
+{
+       u32 fwsm;
+
+       fwsm = er32(FWSM);
+
+       return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
+}
+
+/**
+ *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
+ *  @hw: pointer to the HW structure
+ *
+ *  Forces the speed and duplex settings of the PHY.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 data;
+       bool link;
+
+       if (phy->type != e1000_phy_ife) {
+               ret_val = e1000e_phy_force_speed_duplex_igp(hw);
+               return ret_val;
+       }
+
+       ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
+       if (ret_val)
+               return ret_val;
+
+       e1000e_phy_force_speed_duplex_setup(hw, &data);
+
+       ret_val = e1e_wphy(hw, PHY_CONTROL, data);
+       if (ret_val)
+               return ret_val;
+
+       /* Disable MDI-X support for 10/100 */
+       ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
+       if (ret_val)
+               return ret_val;
+
+       data &= ~IFE_PMC_AUTO_MDIX;
+       data &= ~IFE_PMC_FORCE_MDIX;
+
+       ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
+       if (ret_val)
+               return ret_val;
+
+       hw_dbg(hw, "IFE PMC: %X\n", data);
+
+       udelay(1);
+
+       if (phy->autoneg_wait_to_complete) {
+               hw_dbg(hw, "Waiting for forced speed/duplex link on IFE 
phy.\n");
+
+               ret_val = e1000e_phy_has_link_generic(hw,
+                                                    PHY_FORCE_LIMIT,
+                                                    100000,
+                                                    &link);
+               if (ret_val)
+                       return ret_val;
+
+               if (!link)
+                       hw_dbg(hw, "Link taking longer than expected.\n");
+
+               /* Try once more */
+               ret_val = e1000e_phy_has_link_generic(hw,
+                                                    PHY_FORCE_LIMIT,
+                                                    100000,
+                                                    &link);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
+ *  @hw: pointer to the HW structure
+ *
+ *  Resets the PHY
+ *  This is a function pointer entry point called by drivers
+ *  or other shared routines.
+ **/
+static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 i;
+       u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
+       s32 ret_val;
+       u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
+       u16 word_addr, reg_data, reg_addr, phy_page = 0;
+
+       ret_val = e1000e_phy_hw_reset_generic(hw);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * Initialize the PHY from the NVM on ICH platforms.  This
+        * is needed due to an issue where the NVM configuration is
+        * not properly autoloaded after power transitions.
+        * Therefore, after each PHY reset, we will load the
+        * configuration data out of the NVM manually.
+        */
+       if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
+               struct e1000_adapter *adapter = hw->adapter;
+
+               /* Check if SW needs configure the PHY */
+               if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
+                   (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
+                       sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
+               else
+                       sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
+
+               data = er32(FEXTNVM);
+               if (!(data & sw_cfg_mask))
+                       return 0;
+
+               /* Wait for basic configuration completes before proceeding*/
+               do {
+                       data = er32(STATUS);
+                       data &= E1000_STATUS_LAN_INIT_DONE;
+                       udelay(100);
+               } while ((!data) && --loop);
+
+               /*
+                * If basic configuration is incomplete before the above loop
+                * count reaches 0, loading the configuration from NVM will
+                * leave the PHY in a bad state possibly resulting in no link.
+                */
+               if (loop == 0) {
+                       hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
+               }
+
+               /* Clear the Init Done bit for the next init event */
+               data = er32(STATUS);
+               data &= ~E1000_STATUS_LAN_INIT_DONE;
+               ew32(STATUS, data);
+
+               /*
+                * Make sure HW does not configure LCD from PHY
+                * extended configuration before SW configuration
+                */
+               data = er32(EXTCNF_CTRL);
+               if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
+                       return 0;
+
+               cnf_size = er32(EXTCNF_SIZE);
+               cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
+               cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
+               if (!cnf_size)
+                       return 0;
+
+               cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
+               cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
+
+               /* Configure LCD from extended configuration region. */
+
+               /* cnf_base_addr is in DWORD */
+               word_addr = (u16)(cnf_base_addr << 1);
+
+               for (i = 0; i < cnf_size; i++) {
+                       ret_val = e1000_read_nvm(hw,
+                                               (word_addr + i * 2),
+                                               1,
+                                               &reg_data);
+                       if (ret_val)
+                               return ret_val;
+
+                       ret_val = e1000_read_nvm(hw,
+                                               (word_addr + i * 2 + 1),
+                                               1,
+                                               &reg_addr);
+                       if (ret_val)
+                               return ret_val;
+
+                       /* Save off the PHY page for future writes. */
+                       if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
+                               phy_page = reg_data;
+                               continue;
+                       }
+
+                       reg_addr |= phy_page;
+
+                       ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
+                       if (ret_val)
+                               return ret_val;
+               }
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
+ *  @hw: pointer to the HW structure
+ *
+ *  Populates "phy" structure with various feature states.
+ *  This function is only called by other family-specific
+ *  routines.
+ **/
+static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 data;
+       bool link;
+
+       ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
+       if (ret_val)
+               return ret_val;
+
+       if (!link) {
+               hw_dbg(hw, "Phy info is only valid if link is up\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
+       if (ret_val)
+               return ret_val;
+       phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
+
+       if (phy->polarity_correction) {
+               ret_val = e1000_check_polarity_ife_ich8lan(hw);
+               if (ret_val)
+                       return ret_val;
+       } else {
+               /* Polarity is forced */
+               phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
+                                     ? e1000_rev_polarity_reversed
+                                     : e1000_rev_polarity_normal;
+       }
+
+       ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
+       if (ret_val)
+               return ret_val;
+
+       phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
+
+       /* The following parameters are undefined for 10/100 operation. */
+       phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
+       phy->local_rx = e1000_1000t_rx_status_undefined;
+       phy->remote_rx = e1000_1000t_rx_status_undefined;
+
+       return 0;
+}
+
+/**
+ *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
+ *  @hw: pointer to the HW structure
+ *
+ *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
+ *  This is a function pointer entry point called by drivers
+ *  or other shared routines.
+ **/
+static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
+{
+       switch (hw->phy.type) {
+       case e1000_phy_ife:
+               return e1000_get_phy_info_ife_ich8lan(hw);
+               break;
+       case e1000_phy_igp_3:
+       case e1000_phy_bm:
+               return e1000e_get_phy_info_igp(hw);
+               break;
+       default:
+               break;
+       }
+
+       return -E1000_ERR_PHY_TYPE;
+}
+
+/**
+ *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
+ *  @hw: pointer to the HW structure
+ *
+ *  Polarity is determined on the polarity reversal feature being enabled.
+ *  This function is only called by other family-specific
+ *  routines.
+ **/
+static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 phy_data, offset, mask;
+
+       /*
+        * Polarity is determined based on the reversal feature being enabled.
+        */
+       if (phy->polarity_correction) {
+               offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
+               mask    = IFE_PESC_POLARITY_REVERSED;
+       } else {
+               offset  = IFE_PHY_SPECIAL_CONTROL;
+               mask    = IFE_PSC_FORCE_POLARITY;
+       }
+
+       ret_val = e1e_rphy(hw, offset, &phy_data);
+
+       if (!ret_val)
+               phy->cable_polarity = (phy_data & mask)
+                                     ? e1000_rev_polarity_reversed
+                                     : e1000_rev_polarity_normal;
+
+       return ret_val;
+}
+
+/**
+ *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
+ *  @hw: pointer to the HW structure
+ *  @active: TRUE to enable LPLU, FALSE to disable
+ *
+ *  Sets the LPLU D0 state according to the active flag.  When
+ *  activating LPLU this function also disables smart speed
+ *  and vice versa.  LPLU will not be activated unless the
+ *  device autonegotiation advertisement meets standards of
+ *  either 10 or 10/100 or 10/100/1000 at all duplexes.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 phy_ctrl;
+       s32 ret_val = 0;
+       u16 data;
+
+       if (phy->type == e1000_phy_ife)
+               return ret_val;
+
+       phy_ctrl = er32(PHY_CTRL);
+
+       if (active) {
+               phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               /*
+                * Call gig speed drop workaround on LPLU before accessing
+                * any PHY registers
+                */
+               if ((hw->mac.type == e1000_ich8lan) &&
+                   (hw->phy.type == e1000_phy_igp_3))
+                       e1000e_gig_downshift_workaround_ich8lan(hw);
+
+               /* When LPLU is enabled, we should disable SmartSpeed */
+               ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
+               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
+               if (ret_val)
+                       return ret_val;
+       } else {
+               phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               /*
+                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                * during Dx states where the power conservation is most
+                * important.  During driver activity we should enable
+                * SmartSpeed, so performance is maintained.
+                */
+               if (phy->smart_speed == e1000_smart_speed_on) {
+                       ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          data);
+                       if (ret_val)
+                               return ret_val;
+               } else if (phy->smart_speed == e1000_smart_speed_off) {
+                       ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          data);
+                       if (ret_val)
+                               return ret_val;
+               }
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
+ *  @hw: pointer to the HW structure
+ *  @active: TRUE to enable LPLU, FALSE to disable
+ *
+ *  Sets the LPLU D3 state according to the active flag.  When
+ *  activating LPLU this function also disables smart speed
+ *  and vice versa.  LPLU will not be activated unless the
+ *  device autonegotiation advertisement meets standards of
+ *  either 10 or 10/100 or 10/100/1000 at all duplexes.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 phy_ctrl;
+       s32 ret_val;
+       u16 data;
+
+       phy_ctrl = er32(PHY_CTRL);
+
+       if (!active) {
+               phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+               /*
+                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
+                * during Dx states where the power conservation is most
+                * important.  During driver activity we should enable
+                * SmartSpeed, so performance is maintained.
+                */
+               if (phy->smart_speed == e1000_smart_speed_on) {
+                       ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          data);
+                       if (ret_val)
+                               return ret_val;
+               } else if (phy->smart_speed == e1000_smart_speed_off) {
+                       ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          &data);
+                       if (ret_val)
+                               return ret_val;
+
+                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                          data);
+                       if (ret_val)
+                               return ret_val;
+               }
+       } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
+                  (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+                  (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+               phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
+               ew32(PHY_CTRL, phy_ctrl);
+
+               /*
+                * Call gig speed drop workaround on LPLU before accessing
+                * any PHY registers
+                */
+               if ((hw->mac.type == e1000_ich8lan) &&
+                   (hw->phy.type == e1000_phy_igp_3))
+                       e1000e_gig_downshift_workaround_ich8lan(hw);
+
+               /* When LPLU is enabled, we should disable SmartSpeed */
+               ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
+               if (ret_val)
+                       return ret_val;
+
+               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
+ *  @hw: pointer to the HW structure
+ *  @bank:  pointer to the variable that returns the active bank
+ *
+ *  Reads signature byte from the NVM using the flash access registers.
+ **/
+static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       /* flash bank size is in words */
+       u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
+       u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
+       u8 bank_high_byte = 0;
+
+       if (hw->mac.type != e1000_ich10lan) {
+               if (er32(EECD) & E1000_EECD_SEC1VAL)
+                       *bank = 1;
+               else
+                       *bank = 0;
+       } else {
+               /*
+                * Make sure the signature for bank 0 is valid,
+                * if not check for bank1
+                */
+               e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
+               if ((bank_high_byte & 0xC0) == 0x80) {
+                       *bank = 0;
+               } else {
+                       /*
+                        * find if segment 1 is valid by verifying
+                        * bit 15:14 = 10b in word 0x13
+                        */
+                       e1000_read_flash_byte_ich8lan(hw,
+                                                     act_offset + bank1_offset,
+                                                     &bank_high_byte);
+
+                       /* bank1 has a valid signature equivalent to SEC1V */
+                       if ((bank_high_byte & 0xC0) == 0x80) {
+                               *bank = 1;
+                       } else {
+                               hw_dbg(hw, "ERROR: EEPROM not present\n");
+                               return -E1000_ERR_NVM;
+                       }
+               }
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the word(s) to read.
+ *  @words: Size of data to read in words
+ *  @data: Pointer to the word(s) to read at offset.
+ *
+ *  Reads a word(s) from the NVM using the flash access registers.
+ **/
+static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
+                                 u16 *data)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 act_offset;
+       s32 ret_val;
+       u32 bank = 0;
+       u16 i, word;
+
+       if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
+           (words == 0)) {
+               hw_dbg(hw, "nvm parameter(s) out of bounds\n");
+               return -E1000_ERR_NVM;
+       }
+
+       ret_val = e1000_acquire_swflag_ich8lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
+       if (ret_val)
+               return ret_val;
+
+       act_offset = (bank) ? nvm->flash_bank_size : 0;
+       act_offset += offset;
+
+       for (i = 0; i < words; i++) {
+               if ((dev_spec->shadow_ram) &&
+                   (dev_spec->shadow_ram[offset+i].modified)) {
+                       data[i] = dev_spec->shadow_ram[offset+i].value;
+               } else {
+                       ret_val = e1000_read_flash_word_ich8lan(hw,
+                                                               act_offset + i,
+                                                               &word);
+                       if (ret_val)
+                               break;
+                       data[i] = word;
+               }
+       }
+
+       e1000_release_swflag_ich8lan(hw);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_flash_cycle_init_ich8lan - Initialize flash
+ *  @hw: pointer to the HW structure
+ *
+ *  This function does initial flash setup so that a new read/write/erase cycle
+ *  can be started.
+ **/
+static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
+{
+       union ich8_hws_flash_status hsfsts;
+       s32 ret_val = -E1000_ERR_NVM;
+       s32 i = 0;
+
+       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+
+       /* Check if the flash descriptor is valid */
+       if (hsfsts.hsf_status.fldesvalid == 0) {
+               hw_dbg(hw, "Flash descriptor invalid.  "
+                        "SW Sequencing must be used.");
+               return -E1000_ERR_NVM;
+       }
+
+       /* Clear FCERR and DAEL in hw status by writing 1 */
+       hsfsts.hsf_status.flcerr = 1;
+       hsfsts.hsf_status.dael = 1;
+
+       ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
+
+       /*
+        * Either we should have a hardware SPI cycle in progress
+        * bit to check against, in order to start a new cycle or
+        * FDONE bit should be changed in the hardware so that it
+        * is 1 after hardware reset, which can then be used as an
+        * indication whether a cycle is in progress or has been
+        * completed.
+        */
+
+       if (hsfsts.hsf_status.flcinprog == 0) {
+               /*
+                * There is no cycle running at present,
+                * so we can start a cycle
+                * Begin by setting Flash Cycle Done.
+                */
+               hsfsts.hsf_status.flcdone = 1;
+               ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
+               ret_val = 0;
+       } else {
+               /*
+                * otherwise poll for sometime so the current
+                * cycle has a chance to end before giving up.
+                */
+               for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
+                       hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
+                       if (hsfsts.hsf_status.flcinprog == 0) {
+                               ret_val = 0;
+                               break;
+                       }
+                       udelay(1);
+               }
+               if (ret_val == 0) {
+                       /*
+                        * Successful in waiting for previous cycle to timeout,
+                        * now set the Flash Cycle Done.
+                        */
+                       hsfsts.hsf_status.flcdone = 1;
+                       ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
+               } else {
+                       hw_dbg(hw, "Flash controller busy, cannot get access");
+               }
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
+ *  @hw: pointer to the HW structure
+ *  @timeout: maximum time to wait for completion
+ *
+ *  This function starts a flash cycle and waits for its completion.
+ **/
+static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
+{
+       union ich8_hws_flash_ctrl hsflctl;
+       union ich8_hws_flash_status hsfsts;
+       s32 ret_val = -E1000_ERR_NVM;
+       u32 i = 0;
+
+       /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
+       hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+       hsflctl.hsf_ctrl.flcgo = 1;
+       ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+       /* wait till FDONE bit is set to 1 */
+       do {
+               hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+               if (hsfsts.hsf_status.flcdone == 1)
+                       break;
+               udelay(1);
+       } while (i++ < timeout);
+
+       if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
+               return 0;
+
+       return ret_val;
+}
+
+/**
+ *  e1000_read_flash_word_ich8lan - Read word from flash
+ *  @hw: pointer to the HW structure
+ *  @offset: offset to data location
+ *  @data: pointer to the location for storing the data
+ *
+ *  Reads the flash word at offset into data.  Offset is converted
+ *  to bytes before read.
+ **/
+static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
+                                        u16 *data)
+{
+       /* Must convert offset into bytes. */
+       offset <<= 1;
+
+       return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
+}
+
+/**
+ *  e1000_read_flash_byte_ich8lan - Read byte from flash
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset of the byte to read.
+ *  @data: Pointer to a byte to store the value read.
+ *
+ *  Reads a single byte from the NVM using the flash access registers.
+ **/
+static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
+                                        u8 *data)
+{
+       s32 ret_val;
+       u16 word = 0;
+
+       ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
+       if (ret_val)
+               return ret_val;
+
+       *data = (u8)word;
+
+       return 0;
+}
+
+/**
+ *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the byte or word to read.
+ *  @size: Size of data to read, 1=byte 2=word
+ *  @data: Pointer to the word to store the value read.
+ *
+ *  Reads a byte or word from the NVM using the flash access registers.
+ **/
+static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                        u8 size, u16 *data)
+{
+       union ich8_hws_flash_status hsfsts;
+       union ich8_hws_flash_ctrl hsflctl;
+       u32 flash_linear_addr;
+       u32 flash_data = 0;
+       s32 ret_val = -E1000_ERR_NVM;
+       u8 count = 0;
+
+       if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
+               return -E1000_ERR_NVM;
+
+       flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
+                           hw->nvm.flash_base_addr;
+
+       do {
+               udelay(1);
+               /* Steps */
+               ret_val = e1000_flash_cycle_init_ich8lan(hw);
+               if (ret_val != 0)
+                       break;
+
+               hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+               /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
+               hsflctl.hsf_ctrl.fldbcount = size - 1;
+               hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
+               ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+               ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
+
+               ret_val = e1000_flash_cycle_ich8lan(hw,
+                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
+
+               /*
+                * Check if FCERR is set to 1, if set to 1, clear it
+                * and try the whole sequence a few more times, else
+                * read in (shift in) the Flash Data0, the order is
+                * least significant byte first msb to lsb
+                */
+               if (ret_val == 0) {
+                       flash_data = er32flash(ICH_FLASH_FDATA0);
+                       if (size == 1) {
+                               *data = (u8)(flash_data & 0x000000FF);
+                       } else if (size == 2) {
+                               *data = (u16)(flash_data & 0x0000FFFF);
+                       }
+                       break;
+               } else {
+                       /*
+                        * If we've gotten here, then things are probably
+                        * completely hosed, but if the error condition is
+                        * detected, it won't hurt to give it another try...
+                        * ICH_FLASH_CYCLE_REPEAT_COUNT times.
+                        */
+                       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+                       if (hsfsts.hsf_status.flcerr == 1) {
+                               /* Repeat for some time before giving up. */
+                               continue;
+                       } else if (hsfsts.hsf_status.flcdone == 0) {
+                               hw_dbg(hw, "Timeout error - flash cycle "
+                                        "did not complete.");
+                               break;
+                       }
+               }
+       } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the word(s) to write.
+ *  @words: Size of data to write in words
+ *  @data: Pointer to the word(s) to write at offset.
+ *
+ *  Writes a byte or word to the NVM using the flash access registers.
+ **/
+static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
+                                  u16 *data)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       s32 ret_val;
+       u16 i;
+
+       if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
+           (words == 0)) {
+               hw_dbg(hw, "nvm parameter(s) out of bounds\n");
+               return -E1000_ERR_NVM;
+       }
+
+       ret_val = e1000_acquire_swflag_ich8lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       for (i = 0; i < words; i++) {
+               dev_spec->shadow_ram[offset+i].modified = 1;
+               dev_spec->shadow_ram[offset+i].value = data[i];
+       }
+
+       e1000_release_swflag_ich8lan(hw);
+
+       return 0;
+}
+
+/**
+ *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
+ *  @hw: pointer to the HW structure
+ *
+ *  The NVM checksum is updated by calling the generic update_nvm_checksum,
+ *  which writes the checksum to the shadow ram.  The changes in the shadow
+ *  ram are then committed to the EEPROM by processing each bank at a time
+ *  checking for the modified bit and writing only the pending changes.
+ *  After a successful commit, the shadow ram is cleared and is ready for
+ *  future writes.
+ **/
+static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
+       s32 ret_val;
+       u16 data;
+
+       ret_val = e1000e_update_nvm_checksum_generic(hw);
+       if (ret_val)
+               return ret_val;
+
+       if (nvm->type != e1000_nvm_flash_sw)
+               return ret_val;
+
+       ret_val = e1000_acquire_swflag_ich8lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       /*
+        * We're writing to the opposite bank so if we're on bank 1,
+        * write to bank 0 etc.  We also need to erase the segment that
+        * is going to be written
+        */
+       ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
+       if (ret_val)
+               return ret_val;
+
+       if (bank == 0) {
+               new_bank_offset = nvm->flash_bank_size;
+               old_bank_offset = 0;
+               e1000_erase_flash_bank_ich8lan(hw, 1);
+       } else {
+               old_bank_offset = nvm->flash_bank_size;
+               new_bank_offset = 0;
+               e1000_erase_flash_bank_ich8lan(hw, 0);
+       }
+
+       for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
+               /*
+                * Determine whether to write the value stored
+                * in the other NVM bank or a modified value stored
+                * in the shadow RAM
+                */
+               if (dev_spec->shadow_ram[i].modified) {
+                       data = dev_spec->shadow_ram[i].value;
+               } else {
+                       e1000_read_flash_word_ich8lan(hw,
+                                                     i + old_bank_offset,
+                                                     &data);
+               }
+
+               /*
+                * If the word is 0x13, then make sure the signature bits
+                * (15:14) are 11b until the commit has completed.
+                * This will allow us to write 10b which indicates the
+                * signature is valid.  We want to do this after the write
+                * has completed so that we don't mark the segment valid
+                * while the write is still in progress
+                */
+               if (i == E1000_ICH_NVM_SIG_WORD)
+                       data |= E1000_ICH_NVM_SIG_MASK;
+
+               /* Convert offset to bytes. */
+               act_offset = (i + new_bank_offset) << 1;
+
+               udelay(100);
+               /* Write the bytes to the new bank. */
+               ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
+                                                              act_offset,
+                                                              (u8)data);
+               if (ret_val)
+                       break;
+
+               udelay(100);
+               ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
+                                                         act_offset + 1,
+                                                         (u8)(data >> 8));
+               if (ret_val)
+                       break;
+       }
+
+       /*
+        * Don't bother writing the segment valid bits if sector
+        * programming failed.
+        */
+       if (ret_val) {
+               /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
+               hw_dbg(hw, "Flash commit failed.\n");
+               e1000_release_swflag_ich8lan(hw);
+               return ret_val;
+       }
+
+       /*
+        * Finally validate the new segment by setting bit 15:14
+        * to 10b in word 0x13 , this can be done without an
+        * erase as well since these bits are 11 to start with
+        * and we need to change bit 14 to 0b
+        */
+       act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
+       e1000_read_flash_word_ich8lan(hw, act_offset, &data);
+       data &= 0xBFFF;
+       ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
+                                                      act_offset * 2 + 1,
+                                                      (u8)(data >> 8));
+       if (ret_val) {
+               e1000_release_swflag_ich8lan(hw);
+               return ret_val;
+       }
+
+       /*
+        * And invalidate the previously valid segment by setting
+        * its signature word (0x13) high_byte to 0b. This can be
+        * done without an erase because flash erase sets all bits
+        * to 1's. We can write 1's to 0's without an erase
+        */
+       act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
+       ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
+       if (ret_val) {
+               e1000_release_swflag_ich8lan(hw);
+               return ret_val;
+       }
+
+       /* Great!  Everything worked, we can now clear the cached entries. */
+       for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
+               dev_spec->shadow_ram[i].modified = 0;
+               dev_spec->shadow_ram[i].value = 0xFFFF;
+       }
+
+       e1000_release_swflag_ich8lan(hw);
+
+       /*
+        * Reload the EEPROM, or else modifications will not appear
+        * until after the next adapter reset.
+        */
+       e1000e_reload_nvm(hw);
+       msleep(10);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
+ *  @hw: pointer to the HW structure
+ *
+ *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
+ *  If the bit is 0, that the EEPROM had been modified, but the checksum was 
not
+ *  calculated, in which case we need to calculate the checksum and set bit 6.
+ **/
+static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 data;
+
+       /*
+        * Read 0x19 and check bit 6.  If this bit is 0, the checksum
+        * needs to be fixed.  This bit is an indication that the NVM
+        * was prepared by OEM software and did not calculate the
+        * checksum...a likely scenario.
+        */
+       ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
+       if (ret_val)
+               return ret_val;
+
+       if ((data & 0x40) == 0) {
+               data |= 0x40;
+               ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000e_update_nvm_checksum(hw);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       return e1000e_validate_nvm_checksum_generic(hw);
+}
+
+/**
+ *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
+ *  @hw: pointer to the HW structure
+ *
+ *  To prevent malicious write/erase of the NVM, set it to be read-only
+ *  so that the hardware ignores all write/erase cycles of the NVM via
+ *  the flash control registers.  The shadow-ram copy of the NVM will
+ *  still be updated, however any updates to this copy will not stick
+ *  across driver reloads.
+ **/
+void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
+{
+       union ich8_flash_protected_range pr0;
+       union ich8_hws_flash_status hsfsts;
+       u32 gfpreg;
+       s32 ret_val;
+
+       ret_val = e1000_acquire_swflag_ich8lan(hw);
+       if (ret_val)
+               return;
+
+       gfpreg = er32flash(ICH_FLASH_GFPREG);
+
+       /* Write-protect GbE Sector of NVM */
+       pr0.regval = er32flash(ICH_FLASH_PR0);
+       pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
+       pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
+       pr0.range.wpe = true;
+       ew32flash(ICH_FLASH_PR0, pr0.regval);
+
+       /*
+        * Lock down a subset of GbE Flash Control Registers, e.g.
+        * PR0 to prevent the write-protection from being lifted.
+        * Once FLOCKDN is set, the registers protected by it cannot
+        * be written until FLOCKDN is cleared by a hardware reset.
+        */
+       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+       hsfsts.hsf_status.flockdn = true;
+       ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
+
+       e1000_release_swflag_ich8lan(hw);
+}
+
+/**
+ *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset (in bytes) of the byte/word to read.
+ *  @size: Size of data to read, 1=byte 2=word
+ *  @data: The byte(s) to write to the NVM.
+ *
+ *  Writes one/two bytes to the NVM using the flash access registers.
+ **/
+static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+                                         u8 size, u16 data)
+{
+       union ich8_hws_flash_status hsfsts;
+       union ich8_hws_flash_ctrl hsflctl;
+       u32 flash_linear_addr;
+       u32 flash_data = 0;
+       s32 ret_val;
+       u8 count = 0;
+
+       if (size < 1 || size > 2 || data > size * 0xff ||
+           offset > ICH_FLASH_LINEAR_ADDR_MASK)
+               return -E1000_ERR_NVM;
+
+       flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
+                           hw->nvm.flash_base_addr;
+
+       do {
+               udelay(1);
+               /* Steps */
+               ret_val = e1000_flash_cycle_init_ich8lan(hw);
+               if (ret_val)
+                       break;
+
+               hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+               /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
+               hsflctl.hsf_ctrl.fldbcount = size -1;
+               hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
+               ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+               ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
+
+               if (size == 1)
+                       flash_data = (u32)data & 0x00FF;
+               else
+                       flash_data = (u32)data;
+
+               ew32flash(ICH_FLASH_FDATA0, flash_data);
+
+               /*
+                * check if FCERR is set to 1 , if set to 1, clear it
+                * and try the whole sequence a few more times else done
+                */
+               ret_val = e1000_flash_cycle_ich8lan(hw,
+                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
+               if (!ret_val)
+                       break;
+
+               /*
+                * If we're here, then things are most likely
+                * completely hosed, but if the error condition
+                * is detected, it won't hurt to give it another
+                * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
+                */
+               hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+               if (hsfsts.hsf_status.flcerr == 1)
+                       /* Repeat for some time before giving up. */
+                       continue;
+               if (hsfsts.hsf_status.flcdone == 0) {
+                       hw_dbg(hw, "Timeout error - flash cycle "
+                                "did not complete.");
+                       break;
+               }
+       } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The index of the byte to read.
+ *  @data: The byte to write to the NVM.
+ *
+ *  Writes a single byte to the NVM using the flash access registers.
+ **/
+static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
+                                         u8 data)
+{
+       u16 word = (u16)data;
+
+       return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
+}
+
+/**
+ *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
+ *  @hw: pointer to the HW structure
+ *  @offset: The offset of the byte to write.
+ *  @byte: The byte to write to the NVM.
+ *
+ *  Writes a single byte to the NVM using the flash access registers.
+ *  Goes through a retry algorithm before giving up.
+ **/
+static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
+                                               u32 offset, u8 byte)
+{
+       s32 ret_val;
+       u16 program_retries;
+
+       ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
+       if (!ret_val)
+               return ret_val;
+
+       for (program_retries = 0; program_retries < 100; program_retries++) {
+               hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
+               udelay(100);
+               ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
+               if (!ret_val)
+                       break;
+       }
+       if (program_retries == 100)
+               return -E1000_ERR_NVM;
+
+       return 0;
+}
+
+/**
+ *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
+ *  @hw: pointer to the HW structure
+ *  @bank: 0 for first bank, 1 for second bank, etc.
+ *
+ *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
+ *  bank N is 4096 * N + flash_reg_addr.
+ **/
+static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
+{
+       struct e1000_nvm_info *nvm = &hw->nvm;
+       union ich8_hws_flash_status hsfsts;
+       union ich8_hws_flash_ctrl hsflctl;
+       u32 flash_linear_addr;
+       /* bank size is in 16bit words - adjust to bytes */
+       u32 flash_bank_size = nvm->flash_bank_size * 2;
+       s32 ret_val;
+       s32 count = 0;
+       s32 iteration;
+       s32 sector_size;
+       s32 j;
+
+       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+
+       /*
+        * Determine HW Sector size: Read BERASE bits of hw flash status
+        * register
+        * 00: The Hw sector is 256 bytes, hence we need to erase 16
+        *     consecutive sectors.  The start index for the nth Hw sector
+        *     can be calculated as = bank * 4096 + n * 256
+        * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
+        *     The start index for the nth Hw sector can be calculated
+        *     as = bank * 4096
+        * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
+        *     (ich9 only, otherwise error condition)
+        * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
+        */
+       switch (hsfsts.hsf_status.berasesz) {
+       case 0:
+               /* Hw sector size 256 */
+               sector_size = ICH_FLASH_SEG_SIZE_256;
+               iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
+               break;
+       case 1:
+               sector_size = ICH_FLASH_SEG_SIZE_4K;
+               iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
+               break;
+       case 2:
+               if (hw->mac.type == e1000_ich9lan) {
+                       sector_size = ICH_FLASH_SEG_SIZE_8K;
+                       iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
+               } else {
+                       return -E1000_ERR_NVM;
+               }
+               break;
+       case 3:
+               sector_size = ICH_FLASH_SEG_SIZE_64K;
+               iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
+               break;
+       default:
+               return -E1000_ERR_NVM;
+       }
+
+       /* Start with the base address, then add the sector offset. */
+       flash_linear_addr = hw->nvm.flash_base_addr;
+       flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
+
+       for (j = 0; j < iteration ; j++) {
+               do {
+                       /* Steps */
+                       ret_val = e1000_flash_cycle_init_ich8lan(hw);
+                       if (ret_val)
+                               return ret_val;
+
+                       /*
+                        * Write a value 11 (block Erase) in Flash
+                        * Cycle field in hw flash control
+                        */
+                       hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
+                       hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
+                       ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
+
+                       /*
+                        * Write the last 24 bits of an index within the
+                        * block into Flash Linear address field in Flash
+                        * Address.
+                        */
+                       flash_linear_addr += (j * sector_size);
+                       ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
+
+                       ret_val = e1000_flash_cycle_ich8lan(hw,
+                                              ICH_FLASH_ERASE_COMMAND_TIMEOUT);
+                       if (ret_val == 0)
+                               break;
+
+                       /*
+                        * Check if FCERR is set to 1.  If 1,
+                        * clear it and try the whole sequence
+                        * a few more times else Done
+                        */
+                       hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
+                       if (hsfsts.hsf_status.flcerr == 1)
+                               /* repeat for some time before giving up */
+                               continue;
+                       else if (hsfsts.hsf_status.flcdone == 0)
+                               return ret_val;
+               } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_valid_led_default_ich8lan - Set the default LED settings
+ *  @hw: pointer to the HW structure
+ *  @data: Pointer to the LED settings
+ *
+ *  Reads the LED default settings from the NVM to data.  If the NVM LED
+ *  settings is all 0's or F's, set the LED default to a valid LED default
+ *  setting.
+ **/
+static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
+{
+       s32 ret_val;
+
+       ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
+       if (ret_val) {
+               hw_dbg(hw, "NVM Read Error\n");
+               return ret_val;
+       }
+
+       if (*data == ID_LED_RESERVED_0000 ||
+           *data == ID_LED_RESERVED_FFFF)
+               *data = ID_LED_DEFAULT_ICH8LAN;
+
+       return 0;
+}
+
+/**
+ *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
+ *  @hw: pointer to the HW structure
+ *
+ *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
+ *  register, so the the bus width is hard coded.
+ **/
+static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_bus_info *bus = &hw->bus;
+       s32 ret_val;
+
+       ret_val = e1000e_get_bus_info_pcie(hw);
+
+       /*
+        * ICH devices are "PCI Express"-ish.  They have
+        * a configuration space, but do not contain
+        * PCI Express Capability registers, so bus width
+        * must be hardcoded.
+        */
+       if (bus->width == e1000_bus_width_unknown)
+               bus->width = e1000_bus_width_pcie_x1;
+
+       return ret_val;
+}
+
+/**
+ *  e1000_reset_hw_ich8lan - Reset the hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  Does a full reset of the hardware which includes a reset of the PHY and
+ *  MAC.
+ **/
+static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
+{
+       u32 ctrl, icr, kab;
+       s32 ret_val;
+
+       /*
+        * Prevent the PCI-E bus from sticking if there is no TLP connection
+        * on the last TLP read/write transaction when MAC is reset.
+        */
+       ret_val = e1000e_disable_pcie_master(hw);
+       if (ret_val) {
+               hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+       }
+
+       hw_dbg(hw, "Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       /*
+        * Disable the Transmit and Receive units.  Then delay to allow
+        * any pending transactions to complete before we hit the MAC
+        * with the global reset.
+        */
+       ew32(RCTL, 0);
+       ew32(TCTL, E1000_TCTL_PSP);
+       e1e_flush();
+
+       msleep(10);
+
+       /* Workaround for ICH8 bit corruption issue in FIFO memory */
+       if (hw->mac.type == e1000_ich8lan) {
+               /* Set Tx and Rx buffer allocation to 8k apiece. */
+               ew32(PBA, E1000_PBA_8K);
+               /* Set Packet Buffer Size to 16k. */
+               ew32(PBS, E1000_PBS_16K);
+       }
+
+       ctrl = er32(CTRL);
+
+       if (!e1000_check_reset_block(hw)) {
+               /*
+                * PHY HW reset requires MAC CORE reset at the same
+                * time to make sure the interface between MAC and the
+                * external PHY is reset.
+                */
+               ctrl |= E1000_CTRL_PHY_RST;
+       }
+       ret_val = e1000_acquire_swflag_ich8lan(hw);
+       hw_dbg(hw, "Issuing a global reset to ich8lan");
+       ew32(CTRL, (ctrl | E1000_CTRL_RST));
+       msleep(20);
+
+       ret_val = e1000e_get_auto_rd_done(hw);
+       if (ret_val) {
+               /*
+                * When auto config read does not complete, do not
+                * return with an error. This can happen in situations
+                * where there is no eeprom and prevents getting link.
+                */
+               hw_dbg(hw, "Auto Read Done did not complete\n");
+       }
+
+       ew32(IMC, 0xffffffff);
+       icr = er32(ICR);
+
+       kab = er32(KABGTXD);
+       kab |= E1000_KABGTXD_BGSQLBIAS;
+       ew32(KABGTXD, kab);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_init_hw_ich8lan - Initialize the hardware
+ *  @hw: pointer to the HW structure
+ *
+ *  Prepares the hardware for transmit and receive by doing the following:
+ *   - initialize hardware bits
+ *   - initialize LED identification
+ *   - setup receive address registers
+ *   - setup flow control
+ *   - setup transmit descriptors
+ *   - clear statistics
+ **/
+static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 ctrl_ext, txdctl, snoop;
+       s32 ret_val;
+       u16 i;
+
+       e1000_initialize_hw_bits_ich8lan(hw);
+
+       /* Initialize identification LED */
+       ret_val = e1000e_id_led_init(hw);
+       if (ret_val) {
+               hw_dbg(hw, "Error initializing identification LED\n");
+               return ret_val;
+       }
+
+       /* Setup the receive address. */
+       e1000e_init_rx_addrs(hw, mac->rar_entry_count);
+
+       /* Zero out the Multicast HASH table */
+       hw_dbg(hw, "Zeroing the MTA\n");
+       for (i = 0; i < mac->mta_reg_count; i++)
+               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
+
+       /* Setup link and flow control */
+       ret_val = e1000_setup_link_ich8lan(hw);
+
+       /* Set the transmit descriptor write-back policy for both queues */
+       txdctl = er32(TXDCTL(0));
+       txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
+                E1000_TXDCTL_FULL_TX_DESC_WB;
+       txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
+                E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
+       ew32(TXDCTL(0), txdctl);
+       txdctl = er32(TXDCTL(1));
+       txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
+                E1000_TXDCTL_FULL_TX_DESC_WB;
+       txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
+                E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
+       ew32(TXDCTL(1), txdctl);
+
+       /*
+        * ICH8 has opposite polarity of no_snoop bits.
+        * By default, we should use snoop behavior.
+        */
+       if (mac->type == e1000_ich8lan)
+               snoop = PCIE_ICH8_SNOOP_ALL;
+       else
+               snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
+       e1000e_set_pcie_no_snoop(hw, snoop);
+
+       ctrl_ext = er32(CTRL_EXT);
+       ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
+       ew32(CTRL_EXT, ctrl_ext);
+
+       /*
+        * Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000_clear_hw_cntrs_ich8lan(hw);
+
+       return 0;
+}
+/**
+ *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
+ *  @hw: pointer to the HW structure
+ *
+ *  Sets/Clears required hardware bits necessary for correctly setting up the
+ *  hardware for transmit and receive.
+ **/
+static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
+{
+       u32 reg;
+
+       /* Extended Device Control */
+       reg = er32(CTRL_EXT);
+       reg |= (1 << 22);
+       ew32(CTRL_EXT, reg);
+
+       /* Transmit Descriptor Control 0 */
+       reg = er32(TXDCTL(0));
+       reg |= (1 << 22);
+       ew32(TXDCTL(0), reg);
+
+       /* Transmit Descriptor Control 1 */
+       reg = er32(TXDCTL(1));
+       reg |= (1 << 22);
+       ew32(TXDCTL(1), reg);
+
+       /* Transmit Arbitration Control 0 */
+       reg = er32(TARC(0));
+       if (hw->mac.type == e1000_ich8lan)
+               reg |= (1 << 28) | (1 << 29);
+       reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
+       ew32(TARC(0), reg);
+
+       /* Transmit Arbitration Control 1 */
+       reg = er32(TARC(1));
+       if (er32(TCTL) & E1000_TCTL_MULR)
+               reg &= ~(1 << 28);
+       else
+               reg |= (1 << 28);
+       reg |= (1 << 24) | (1 << 26) | (1 << 30);
+       ew32(TARC(1), reg);
+
+       /* Device Status */
+       if (hw->mac.type == e1000_ich8lan) {
+               reg = er32(STATUS);
+               reg &= ~(1 << 31);
+               ew32(STATUS, reg);
+       }
+}
+
+/**
+ *  e1000_setup_link_ich8lan - Setup flow control and link settings
+ *  @hw: pointer to the HW structure
+ *
+ *  Determines which flow control settings to use, then configures flow
+ *  control.  Calls the appropriate media-specific link configuration
+ *  function.  Assuming the adapter has a valid link partner, a valid link
+ *  should be established.  Assumes the hardware has previously been reset
+ *  and the transmitter and receiver are not enabled.
+ **/
+static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+
+       if (e1000_check_reset_block(hw))
+               return 0;
+
+       /*
+        * ICH parts do not have a word in the NVM to determine
+        * the default flow control setting, so we explicitly
+        * set it to full.
+        */
+       if (hw->fc.type == e1000_fc_default)
+               hw->fc.type = e1000_fc_full;
+
+       hw->fc.original_type = hw->fc.type;
+
+       hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
+
+       /* Continue to configure the copper link. */
+       ret_val = e1000_setup_copper_link_ich8lan(hw);
+       if (ret_val)
+               return ret_val;
+
+       ew32(FCTTV, hw->fc.pause_time);
+
+       return e1000e_set_fc_watermarks(hw);
+}
+
+/**
+ *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
+ *  @hw: pointer to the HW structure
+ *
+ *  Configures the kumeran interface to the PHY to wait the appropriate time
+ *  when polling the PHY, then call the generic setup_copper_link to finish
+ *  configuring the copper link.
+ **/
+static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       s32 ret_val;
+       u16 reg_data;
+
+       ctrl = er32(CTRL);
+       ctrl |= E1000_CTRL_SLU;
+       ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ew32(CTRL, ctrl);
+
+       /*
+        * Set the mac to wait the maximum time between each iteration
+        * and increase the max iterations when polling the phy;
+        * this fixes erroneous timeouts at 10Mbps.
+        */
+       ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
+       if (ret_val)
+               return ret_val;
+       ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
+       if (ret_val)
+               return ret_val;
+       reg_data |= 0x3F;
+       ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
+       if (ret_val)
+               return ret_val;
+
+       if (hw->phy.type == e1000_phy_igp_3) {
+               ret_val = e1000e_copper_link_setup_igp(hw);
+               if (ret_val)
+                       return ret_val;
+       } else if (hw->phy.type == e1000_phy_bm) {
+               ret_val = e1000e_copper_link_setup_m88(hw);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       if (hw->phy.type == e1000_phy_ife) {
+               ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
+               if (ret_val)
+                       return ret_val;
+
+               reg_data &= ~IFE_PMC_AUTO_MDIX;
+
+               switch (hw->phy.mdix) {
+               case 1:
+                       reg_data &= ~IFE_PMC_FORCE_MDIX;
+                       break;
+               case 2:
+                       reg_data |= IFE_PMC_FORCE_MDIX;
+                       break;
+               case 0:
+               default:
+                       reg_data |= IFE_PMC_AUTO_MDIX;
+                       break;
+               }
+               ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
+               if (ret_val)
+                       return ret_val;
+       }
+       return e1000e_setup_copper_link(hw);
+}
+
+/**
+ *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
+ *  @hw: pointer to the HW structure
+ *  @speed: pointer to store current link speed
+ *  @duplex: pointer to store the current link duplex
+ *
+ *  Calls the generic get_speed_and_duplex to retrieve the current link
+ *  information and then calls the Kumeran lock loss workaround for links at
+ *  gigabit speeds.
+ **/
+static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
+                                         u16 *duplex)
+{
+       s32 ret_val;
+
+       ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
+       if (ret_val)
+               return ret_val;
+
+       if ((hw->mac.type == e1000_ich8lan) &&
+           (hw->phy.type == e1000_phy_igp_3) &&
+           (*speed == SPEED_1000)) {
+               ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
+       }
+
+       return ret_val;
+}
+
+/**
+ *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
+ *  @hw: pointer to the HW structure
+ *
+ *  Work-around for 82566 Kumeran PCS lock loss:
+ *  On link status change (i.e. PCI reset, speed change) and link is up and
+ *  speed is gigabit-
+ *    0) if workaround is optionally disabled do nothing
+ *    1) wait 1ms for Kumeran link to come up
+ *    2) check Kumeran Diagnostic register PCS lock loss bit
+ *    3) if not set the link is locked (all is good), otherwise...
+ *    4) reset the PHY
+ *    5) repeat up to 10 times
+ *  Note: this is only called for IGP3 copper when speed is 1gb.
+ **/
+static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+       u32 phy_ctrl;
+       s32 ret_val;
+       u16 i, data;
+       bool link;
+
+       if (!dev_spec->kmrn_lock_loss_workaround_enabled)
+               return 0;
+
+       /*
+        * Make sure link is up before proceeding.  If not just return.
+        * Attempting this while link is negotiating fouled up link
+        * stability
+        */
+       ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
+       if (!link)
+               return 0;
+
+       for (i = 0; i < 10; i++) {
+               /* read once to clear */
+               ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
+               if (ret_val)
+                       return ret_val;
+               /* and again to get new status */
+               ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
+               if (ret_val)
+                       return ret_val;
+
+               /* check for PCS lock */
+               if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
+                       return 0;
+
+               /* Issue PHY reset */
+               e1000_phy_hw_reset(hw);
+               mdelay(5);
+       }
+       /* Disable GigE link negotiation */
+       phy_ctrl = er32(PHY_CTRL);
+       phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
+                    E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+       ew32(PHY_CTRL, phy_ctrl);
+
+       /*
+        * Call gig speed drop workaround on Gig disable before accessing
+        * any PHY registers
+        */
+       e1000e_gig_downshift_workaround_ich8lan(hw);
+
+       /* unable to acquire PCS lock */
+       return -E1000_ERR_PHY;
+}
+
+/**
+ *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
+ *  @hw: pointer to the HW structure
+ *  @state: boolean value used to set the current Kumeran workaround state
+ *
+ *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
+ *  /disabled - FALSE).
+ **/
+void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
+                                                bool state)
+{
+       struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
+
+       if (hw->mac.type != e1000_ich8lan) {
+               hw_dbg(hw, "Workaround applies to ICH8 only.\n");
+               return;
+       }
+
+       dev_spec->kmrn_lock_loss_workaround_enabled = state;
+}
+
+/**
+ *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
+ *  @hw: pointer to the HW structure
+ *
+ *  Workaround for 82566 power-down on D3 entry:
+ *    1) disable gigabit link
+ *    2) write VR power-down enable
+ *    3) read it back
+ *  Continue if successful, else issue LCD reset and repeat
+ **/
+void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
+{
+       u32 reg;
+       u16 data;
+       u8  retry = 0;
+
+       if (hw->phy.type != e1000_phy_igp_3)
+               return;
+
+       /* Try the workaround twice (if needed) */
+       do {
+               /* Disable link */
+               reg = er32(PHY_CTRL);
+               reg |= (E1000_PHY_CTRL_GBE_DISABLE |
+                       E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+               ew32(PHY_CTRL, reg);
+
+               /*
+                * Call gig speed drop workaround on Gig disable before
+                * accessing any PHY registers
+                */
+               if (hw->mac.type == e1000_ich8lan)
+                       e1000e_gig_downshift_workaround_ich8lan(hw);
+
+               /* Write VR power-down enable */
+               e1e_rphy(hw, IGP3_VR_CTRL, &data);
+               data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
+               e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
+
+               /* Read it back and test */
+               e1e_rphy(hw, IGP3_VR_CTRL, &data);
+               data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
+               if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
+                       break;
+
+               /* Issue PHY reset and repeat at most one more time */
+               reg = er32(CTRL);
+               ew32(CTRL, reg | E1000_CTRL_PHY_RST);
+               retry++;
+       } while (retry);
+}
+
+/**
+ *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
+ *  @hw: pointer to the HW structure
+ *
+ *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
+ *  LPLU, Gig disable, MDIC PHY reset):
+ *    1) Set Kumeran Near-end loopback
+ *    2) Clear Kumeran Near-end loopback
+ *  Should only be called for ICH8[m] devices with IGP_3 Phy.
+ **/
+void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 reg_data;
+
+       if ((hw->mac.type != e1000_ich8lan) ||
+           (hw->phy.type != e1000_phy_igp_3))
+               return;
+
+       ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
+                                     &reg_data);
+       if (ret_val)
+               return;
+       reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
+       ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
+                                      reg_data);
+       if (ret_val)
+               return;
+       reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
+       ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
+                                      reg_data);
+}
+
+/**
+ *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
+ *  @hw: pointer to the HW structure
+ *
+ *  During S0 to Sx transition, it is possible the link remains at gig
+ *  instead of negotiating to a lower speed.  Before going to Sx, set
+ *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
+ *  to a lower speed.
+ *
+ *  Should only be called for ICH9 and ICH10 devices.
+ **/
+void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
+{
+       u32 phy_ctrl;
+
+       if ((hw->mac.type == e1000_ich10lan) ||
+           (hw->mac.type == e1000_ich9lan)) {
+               phy_ctrl = er32(PHY_CTRL);
+               phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
+                           E1000_PHY_CTRL_GBE_DISABLE;
+               ew32(PHY_CTRL, phy_ctrl);
+       }
+
+       return;
+}
+
+/**
+ *  e1000_cleanup_led_ich8lan - Restore the default LED operation
+ *  @hw: pointer to the HW structure
+ *
+ *  Return the LED back to the default configuration.
+ **/
+static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
+{
+       if (hw->phy.type == e1000_phy_ife)
+               return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
+
+       ew32(LEDCTL, hw->mac.ledctl_default);
+       return 0;
+}
+
+/**
+ *  e1000_led_on_ich8lan - Turn LEDs on
+ *  @hw: pointer to the HW structure
+ *
+ *  Turn on the LEDs.
+ **/
+static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
+{
+       if (hw->phy.type == e1000_phy_ife)
+               return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
+                               (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
+
+       ew32(LEDCTL, hw->mac.ledctl_mode2);
+       return 0;
+}
+
+/**
+ *  e1000_led_off_ich8lan - Turn LEDs off
+ *  @hw: pointer to the HW structure
+ *
+ *  Turn off the LEDs.
+ **/
+static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
+{
+       if (hw->phy.type == e1000_phy_ife)
+               return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
+                              (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
+
+       ew32(LEDCTL, hw->mac.ledctl_mode1);
+       return 0;
+}
+
+/**
+ *  e1000_get_cfg_done_ich8lan - Read config done bit
+ *  @hw: pointer to the HW structure
+ *
+ *  Read the management control register for the config done bit for
+ *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
+ *  to read the config done bit, so an error is *ONLY* logged and returns
+ *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
+ *  would not be able to be reset or change link.
+ **/
+static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
+{
+       u32 bank = 0;
+
+       e1000e_get_cfg_done(hw);
+
+       /* If EEPROM is not marked present, init the IGP 3 PHY manually */
+       if (hw->mac.type != e1000_ich10lan) {
+               if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
+                   (hw->phy.type == e1000_phy_igp_3)) {
+                       e1000e_phy_init_script_igp3(hw);
+               }
+       } else {
+               if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
+                       /* Maybe we should do a basic PHY config */
+                       hw_dbg(hw, "EEPROM not present\n");
+                       return -E1000_ERR_CONFIG;
+               }
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears hardware counters specific to the silicon family and calls
+ *  clear_hw_cntrs_generic to clear all general purpose counters.
+ **/
+static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
+{
+       u32 temp;
+
+       e1000e_clear_hw_cntrs_base(hw);
+
+       temp = er32(ALGNERRC);
+       temp = er32(RXERRC);
+       temp = er32(TNCRS);
+       temp = er32(CEXTERR);
+       temp = er32(TSCTC);
+       temp = er32(TSCTFC);
+
+       temp = er32(MGTPRC);
+       temp = er32(MGTPDC);
+       temp = er32(MGTPTC);
+
+       temp = er32(IAC);
+       temp = er32(ICRXOC);
+
+}
+
+static struct e1000_mac_operations ich8_mac_ops = {
+       .check_mng_mode         = e1000_check_mng_mode_ich8lan,
+       .check_for_link         = e1000e_check_for_copper_link,
+       .cleanup_led            = e1000_cleanup_led_ich8lan,
+       .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
+       .get_bus_info           = e1000_get_bus_info_ich8lan,
+       .get_link_up_info       = e1000_get_link_up_info_ich8lan,
+       .led_on                 = e1000_led_on_ich8lan,
+       .led_off                = e1000_led_off_ich8lan,
+       .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
+       .reset_hw               = e1000_reset_hw_ich8lan,
+       .init_hw                = e1000_init_hw_ich8lan,
+       .setup_link             = e1000_setup_link_ich8lan,
+       .setup_physical_interface= e1000_setup_copper_link_ich8lan,
+};
+
+static struct e1000_phy_operations ich8_phy_ops = {
+       .acquire_phy            = e1000_acquire_swflag_ich8lan,
+       .check_reset_block      = e1000_check_reset_block_ich8lan,
+       .commit_phy             = NULL,
+       .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
+       .get_cfg_done           = e1000_get_cfg_done_ich8lan,
+       .get_cable_length       = e1000e_get_cable_length_igp_2,
+       .get_phy_info           = e1000_get_phy_info_ich8lan,
+       .read_phy_reg           = e1000e_read_phy_reg_igp,
+       .release_phy            = e1000_release_swflag_ich8lan,
+       .reset_phy              = e1000_phy_hw_reset_ich8lan,
+       .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
+       .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
+       .write_phy_reg          = e1000e_write_phy_reg_igp,
+};
+
+static struct e1000_nvm_operations ich8_nvm_ops = {
+       .acquire_nvm            = e1000_acquire_swflag_ich8lan,
+       .read_nvm               = e1000_read_nvm_ich8lan,
+       .release_nvm            = e1000_release_swflag_ich8lan,
+       .update_nvm             = e1000_update_nvm_checksum_ich8lan,
+       .valid_led_default      = e1000_valid_led_default_ich8lan,
+       .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
+       .write_nvm              = e1000_write_nvm_ich8lan,
+};
+
+struct e1000_info e1000_ich8_info = {
+       .mac                    = e1000_ich8lan,
+       .flags                  = FLAG_HAS_WOL
+                                 | FLAG_IS_ICH
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_HAS_AMT
+                                 | FLAG_HAS_FLASH
+                                 | FLAG_APME_IN_WUC,
+       .pba                    = 8,
+       .get_variants           = e1000_get_variants_ich8lan,
+       .mac_ops                = &ich8_mac_ops,
+       .phy_ops                = &ich8_phy_ops,
+       .nvm_ops                = &ich8_nvm_ops,
+};
+
+struct e1000_info e1000_ich9_info = {
+       .mac                    = e1000_ich9lan,
+       .flags                  = FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_IS_ICH
+                                 | FLAG_HAS_WOL
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_HAS_AMT
+                                 | FLAG_HAS_ERT
+                                 | FLAG_HAS_FLASH
+                                 | FLAG_APME_IN_WUC,
+       .pba                    = 10,
+       .get_variants           = e1000_get_variants_ich8lan,
+       .mac_ops                = &ich8_mac_ops,
+       .phy_ops                = &ich8_phy_ops,
+       .nvm_ops                = &ich8_nvm_ops,
+};
+
+struct e1000_info e1000_ich10_info = {
+       .mac                    = e1000_ich10lan,
+       .flags                  = FLAG_HAS_JUMBO_FRAMES
+                                 | FLAG_IS_ICH
+                                 | FLAG_HAS_WOL
+                                 | FLAG_RX_CSUM_ENABLED
+                                 | FLAG_HAS_CTRLEXT_ON_LOAD
+                                 | FLAG_HAS_AMT
+                                 | FLAG_HAS_ERT
+                                 | FLAG_HAS_FLASH
+                                 | FLAG_APME_IN_WUC,
+       .pba                    = 10,
+       .get_variants           = e1000_get_variants_ich8lan,
+       .mac_ops                = &ich8_mac_ops,
+       .phy_ops                = &ich8_phy_ops,
+       .nvm_ops                = &ich8_nvm_ops,
+};
diff -r be85b1d7a52b -r 2ee6febdd4f9 drivers/net/e1000e/lib.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/e1000e/lib.c  Tue Feb 17 11:25:22 2009 +0000
@@ -0,0 +1,2501 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@xxxxxxxxx>
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include "e1000.h"
+
+enum e1000_mng_mode {
+       e1000_mng_mode_none = 0,
+       e1000_mng_mode_asf,
+       e1000_mng_mode_pt,
+       e1000_mng_mode_ipmi,
+       e1000_mng_mode_host_if_only
+};
+
+#define E1000_FACTPS_MNGCG             0x20000000
+
+/* Intel(R) Active Management Technology signature */
+#define E1000_IAMT_SIGNATURE           0x544D4149
+
+/**
+ *  e1000e_get_bus_info_pcie - Get PCIe bus information
+ *  @hw: pointer to the HW structure
+ *
+ *  Determines and stores the system bus information for a particular
+ *  network interface.  The following bus information is determined and stored:
+ *  bus speed, bus width, type (PCIe), and PCIe function.
+ **/
+s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
+{
+       struct e1000_bus_info *bus = &hw->bus;
+       struct e1000_adapter *adapter = hw->adapter;
+       u32 status;
+       u16 pcie_link_status, pci_header_type, cap_offset;
+
+       cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
+       if (!cap_offset) {
+               bus->width = e1000_bus_width_unknown;
+       } else {
+               pci_read_config_word(adapter->pdev,
+                                    cap_offset + PCIE_LINK_STATUS,
+                                    &pcie_link_status);
+               bus->width = (enum e1000_bus_width)((pcie_link_status &
+                                                    PCIE_LINK_WIDTH_MASK) >>
+                                                   PCIE_LINK_WIDTH_SHIFT);
+       }
+
+       pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
+                            &pci_header_type);
+       if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
+               status = er32(STATUS);
+               bus->func = (status & E1000_STATUS_FUNC_MASK)
+                           >> E1000_STATUS_FUNC_SHIFT;
+       } else {
+               bus->func = 0;
+       }
+
+       return 0;
+}
+
+/**
+ *  e1000e_write_vfta - Write value to VLAN filter table
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset in VLAN filter table
+ *  @value: register value written to VLAN filter table
+ *
+ *  Writes value at the given offset in the register array which stores
+ *  the VLAN filter table.
+ **/
+void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
+{
+       E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
+       e1e_flush();
+}
+
+/**
+ *  e1000e_init_rx_addrs - Initialize receive address's
+ *  @hw: pointer to the HW structure
+ *  @rar_count: receive address registers
+ *
+ *  Setups the receive address registers by setting the base receive address
+ *  register to the devices MAC address and clearing all the other receive
+ *  address registers to 0.
+ **/
+void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
+{
+       u32 i;
+
+       /* Setup the receive address */
+       hw_dbg(hw, "Programming MAC Address into RAR[0]\n");
+
+       e1000e_rar_set(hw, hw->mac.addr, 0);
+
+       /* Zero out the other (rar_entry_count - 1) receive addresses */
+       hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1);
+       for (i = 1; i < rar_count; i++) {
+               E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
+               e1e_flush();
+               E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
+               e1e_flush();
+       }
+}
+
+/**
+ *  e1000e_rar_set - Set receive address register
+ *  @hw: pointer to the HW structure
+ *  @addr: pointer to the receive address
+ *  @index: receive address array register
+ *
+ *  Sets the receive address array register at index to the address passed
+ *  in by addr.
+ **/
+void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
+{
+       u32 rar_low, rar_high;
+
+       /*
+        * HW expects these in little endian so we reverse the byte order
+        * from network order (big endian) to little endian
+        */
+       rar_low = ((u32) addr[0] |

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