# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1232120639 0
# Node ID c1320922d05e56c61190cd5df0dc105fe6fe4e7a
# Parent 3c9b66b1798dd920a49d9511176aa0c03af9bc00
x86: Tighten MSR access checks so only dom0 can access cpufreq MSRs,
and then only when it is the cpufreq controller.
Signed-off-by: Keir Fraser <keir.fraser@xxxxxxxxxx>
---
xen/arch/x86/traps.c | 20 ++++++++++----------
1 files changed, 10 insertions(+), 10 deletions(-)
diff -r 3c9b66b1798d -r c1320922d05e xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Fri Jan 16 15:32:12 2009 +0000
+++ b/xen/arch/x86/traps.c Fri Jan 16 15:43:59 2009 +0000
@@ -1632,6 +1632,12 @@ void (*pv_post_outb_hook)(unsigned int p
# define read_sreg(regs, sr) read_segment_register(sr)
#endif
+static int is_cpufreq_controller(struct domain *d)
+{
+ return ((cpufreq_controller == FREQCTL_dom0_kernel) &&
+ (d->domain_id == 0));
+}
+
static int emulate_privileged_op(struct cpu_user_regs *regs)
{
struct vcpu *v = current;
@@ -2143,7 +2149,7 @@ static int emulate_privileged_op(struct
case MSR_K8_PSTATE7:
if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
goto fail;
- if ( cpufreq_controller != FREQCTL_dom0_kernel )
+ if ( !is_cpufreq_controller(v->domain) )
break;
if ( wrmsr_safe(regs->ecx, eax, edx) != 0 )
goto fail;
@@ -2181,16 +2187,11 @@ static int emulate_privileged_op(struct
case MSR_IA32_MPERF:
case MSR_IA32_APERF:
case MSR_IA32_PERF_CTL:
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
- goto fail;
- if ( cpufreq_controller != FREQCTL_dom0_kernel )
- break;
- if ( wrmsr_safe(regs->ecx, eax, edx) != 0 )
- goto fail;
- break;
case MSR_IA32_THERM_CONTROL:
if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
goto fail;
+ if ( !is_cpufreq_controller(v->domain) )
+ break;
if ( wrmsr_safe(regs->ecx, eax, edx) != 0 )
goto fail;
break;
@@ -2249,7 +2250,7 @@ static int emulate_privileged_op(struct
case MSR_K8_PSTATE7:
if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
goto fail;
- if ( cpufreq_controller != FREQCTL_dom0_kernel )
+ if ( !is_cpufreq_controller(v->domain) )
{
regs->eax = regs->edx = 0;
break;
@@ -2267,7 +2268,6 @@ static int emulate_privileged_op(struct
MSR_IA32_MISC_ENABLE_XTPR_DISABLE;
break;
case MSR_EFER:
- case MSR_IA32_THERM_CONTROL:
case MSR_AMD_PATCHLEVEL:
default:
if ( rdmsr_hypervisor_regs(regs->ecx, &l, &h) )
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