# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1220264941 -3600
# Node ID b6eea72ea9dcdce3286648db71f84590817a12e1
# Parent 86b956d8cf046d071c828ca9e461311f68fc0c6e
x86: allow Dom0 to control a few more MSR bits
Linux 2.6.27 adds code to enable extended config space accesses in the
Northbridge Configuration MSR; Xen should allow Dom0 to control the
respective bit.
Likewise, 2.6.26 added support to enable the MMIO config space access
method for certain Sun systems, so similarly Xen should allow Dom0 to
control the respective fields of the MMIO Configuration Base Address
Register.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
---
xen/arch/x86/traps.c | 31 +++++++++++++++++++++++++++++++
xen/include/asm-x86/msr-index.h | 12 ++++++++++++
2 files changed, 43 insertions(+)
diff -r 86b956d8cf04 -r b6eea72ea9dc xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Mon Sep 01 10:52:05 2008 +0100
+++ b/xen/arch/x86/traps.c Mon Sep 01 11:29:01 2008 +0100
@@ -2116,6 +2116,36 @@ static int emulate_privileged_op(struct
if ( wrmsr_safe(regs->ecx, eax, edx) != 0 )
goto fail;
break;
+ case MSR_AMD64_NB_CFG:
+ if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+ boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+ goto fail;
+ if ( !IS_PRIV(v->domain) )
+ break;
+ if ( (rdmsr_safe(MSR_AMD64_NB_CFG, l, h) != 0) ||
+ (eax != l) ||
+ ((edx ^ h) & ~(1 << (AMD64_NB_CFG_CF8_EXT_ENABLE_BIT - 32))) )
+ goto invalid;
+ if ( wrmsr_safe(MSR_AMD64_NB_CFG, eax, edx) != 0 )
+ goto fail;
+ break;
+ case MSR_FAM10H_MMIO_CONF_BASE:
+ if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+ boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+ goto fail;
+ if ( !IS_PRIV(v->domain) )
+ break;
+ if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) ||
+ (((((u64)h << 32) | l) ^ res) &
+ ~((1 << FAM10H_MMIO_CONF_ENABLE_BIT) |
+ (FAM10H_MMIO_CONF_BUSRANGE_MASK <<
+ FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
+ ((u64)FAM10H_MMIO_CONF_BASE_MASK <<
+ FAM10H_MMIO_CONF_BASE_SHIFT))) )
+ goto invalid;
+ if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, eax, edx) != 0 )
+ goto fail;
+ break;
case MSR_IA32_PERF_CTL:
if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
goto fail;
@@ -2129,6 +2159,7 @@ static int emulate_privileged_op(struct
break;
if ( (rdmsr_safe(regs->ecx, l, h) != 0) ||
(eax != l) || (edx != h) )
+ invalid:
gdprintk(XENLOG_WARNING, "Domain attempted WRMSR %p from "
"%08x:%08x to %08x:%08x.\n",
_p(regs->ecx), h, l, edx, eax);
diff -r 86b956d8cf04 -r b6eea72ea9dc xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Mon Sep 01 10:52:05 2008 +0100
+++ b/xen/include/asm-x86/msr-index.h Mon Sep 01 11:29:01 2008 +0100
@@ -194,10 +194,22 @@
#define _K8_VMCR_SVME_DISABLE 4
#define K8_VMCR_SVME_DISABLE (1 << _K8_VMCR_SVME_DISABLE)
+/* AMD64 MSRs */
+#define MSR_AMD64_NB_CFG 0xc001001f
+#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
+
/* AMD Family10h machine check MSRs */
#define MSR_F10_MC4_MISC1 0xc0000408
#define MSR_F10_MC4_MISC2 0xc0000409
#define MSR_F10_MC4_MISC3 0xc000040A
+
+/* Other AMD Fam10h MSRs */
+#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
+#define FAM10H_MMIO_CONF_ENABLE_BIT 0
+#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
+#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
+#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff
+#define FAM10H_MMIO_CONF_BASE_SHIFT 20
/* K6 MSRs */
#define MSR_K6_EFER 0xc0000080
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