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[Xen-changelog] [xen-unstable] [IA64] Consolidate non-virtualized PSR bi

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Subject: [Xen-changelog] [xen-unstable] [IA64] Consolidate non-virtualized PSR bits into macro
From: Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>
Date: Sat, 16 Jun 2007 05:42:01 -0700
Delivery-date: Sat, 16 Jun 2007 05:40:27 -0700
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# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1180631930 21600
# Node ID c0afc89cda750efb741e60b3ba6b7990512e1e6c
# Parent  409f9849fa68e181627a28d97a430d3fd85f07b6
[IA64] Consolidate non-virtualized PSR bits into macro

Signed-off-by: Alex Williamson <alex.williamson@xxxxxx>
---
 xen/arch/ia64/xen/vcpu.c |   22 ++++++++++------------
 1 files changed, 10 insertions(+), 12 deletions(-)

diff -r 409f9849fa68 -r c0afc89cda75 xen/arch/ia64/xen/vcpu.c
--- a/xen/arch/ia64/xen/vcpu.c  Thu May 31 11:05:33 2007 -0600
+++ b/xen/arch/ia64/xen/vcpu.c  Thu May 31 11:18:50 2007 -0600
@@ -51,6 +51,14 @@ typedef union {
 #define        IA64_PTA_BASE_BIT       15
 #define        IA64_PTA_LFMT           (1UL << IA64_PTA_VF_BIT)
 #define        IA64_PTA_SZ(x)          (x##UL << IA64_PTA_SZ_BIT)
+
+#define IA64_PSR_NON_VIRT_BITS                         \
+       (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC |      \
+        IA64_PSR_MFL| IA64_PSR_MFH| IA64_PSR_PK |      \
+        IA64_PSR_DFL| IA64_PSR_SP | IA64_PSR_DB |      \
+        IA64_PSR_LP | IA64_PSR_TB | IA64_PSR_ID |      \
+        IA64_PSR_DA | IA64_PSR_DD | IA64_PSR_SS |      \
+        IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
 
 unsigned long vcpu_verbose = 0;
 
@@ -455,12 +463,7 @@ IA64FAULT vcpu_set_psr(VCPU * vcpu, u64 
        u64 enabling_interrupts = 0;
 
        /* Copy non-virtualized bits.  */
-       newpsr.val = val & (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC |
-                           IA64_PSR_MFL| IA64_PSR_MFH| IA64_PSR_PK |
-                           IA64_PSR_DFL| IA64_PSR_SP | IA64_PSR_DB |
-                           IA64_PSR_LP | IA64_PSR_TB | IA64_PSR_ID |
-                           IA64_PSR_DA | IA64_PSR_DD | IA64_PSR_SS |
-                           IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA);
+       newpsr.val = val & IA64_PSR_NON_VIRT_BITS;
 
        /* Bits forced to 1 (psr.si, psr.is and psr.mc are forced to 0)  */
        newpsr.val |= IA64_PSR_DI;
@@ -518,12 +521,7 @@ u64 vcpu_get_psr(VCPU * vcpu)
        ipsr.i64 = regs->cr_ipsr;
 
        /* Copy non-virtualized bits.  */
-       newpsr.i64 = ipsr.i64 & (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC |
-                                IA64_PSR_MFL| IA64_PSR_MFH| IA64_PSR_PK |
-                                IA64_PSR_DFL| IA64_PSR_SP | IA64_PSR_DB |
-                                IA64_PSR_LP | IA64_PSR_TB | IA64_PSR_ID |
-                                IA64_PSR_DA | IA64_PSR_DD | IA64_PSR_SS |
-                                IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA);
+       newpsr.i64 = ipsr.i64 & IA64_PSR_NON_VIRT_BITS;
 
        /* Bits forced to 1 (psr.si and psr.is are forced to 0)  */
        newpsr.i64 |= IA64_PSR_DI;

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