# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID aa8ca06d209e34db5ae2573e0fcc22c602ce6510
# Parent 9e9d8696fb553784750237d77119d4785d057a68
[IA64] xenctx shows more registers for ia64
This patch adds more user registers to show them to xenctx for ia64.
Tested domU/domVTi on ia64.
Sample is the below.
# ./xenctx 1 0
iip: e000000000000810
ipsr: 00001012087a6010 b0: a000000100068a70
b6: a00000010014ff60 b7: e000000000000800
cr_ifs: 800000000000050a ar_unat: 0000000000000000
ar_pfs: 8000000000000209 ar_rsc: 0000000000000008
ar_rnat: 0000000000000000 ar_bspstore: a000000100c19030
ar_fpsr: 0009804c8a70433f event_callback_ip: a000000100067a20
pr: 000000000005aa85 loadrs: 0000000000780000
iva: a000000100008000 dcr: 0000000000007e04
r1: a0000001010369a0
r2: 0000000000001000 r3: 8000000000000209
r4: 0000000000000000 r5: 0000000000000000
r6: 0000000000000000 r7: 0000000000000000
r8: a000000100068a70 r9: 0000000000000100
r10: 0000000000000000 r11: 0000000000050ac5
sp: a000000100c1fd80 tp: a000000100c18000
r14: 0000000000000001 r15: 0000000000000000
r16: fffffffffff04c18 r17: a000000100c1fdb0
r18: a000000100c1fdb1 r19: a000000100c1fe90
r20: a000000100c1fe10 r21: 0000000000000000
r22: 0000000000000001 r23: 0000000000000000
r24: a000000100e5a448 r25: a000000100c18f10
r26: ffffffffffff0030 r27: 0000000000000000
r28: 000000000000001d r29: 0000000000000000
r30: 0000000000000000 r31: 0000000000000000
itr: P rid va pa ps ed pl ar a d ma key
[0] 1 000005 a000000100000000 0000004000000 1a 64M 1 2 3 1 1 0 WB 000000
[1] 1 000007 e000000000000000 0000000000000 18 16M 1 2 3 1 1 0 WB 000000
[2] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[3] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[4] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[5] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[6] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[7] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
dtr: P rid va pa ps ed pl ar a d ma key
[0] 1 000005 a000000100000000 0000004000000 1a 64M 1 2 3 1 1 0 WB 000000
[1] 1 000007 ffffffffffff0000 0000000010000 10 64K 1 2 3 1 1 0 WB 000000
[2] 1 000007 e000000000000000 0000000000000 18 16M 1 2 3 1 1 0 WB 000000
[3] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[4] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[5] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[6] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
[7] 0 000000 0000000000000000 0000000000000 00 0 0 0 0 0 0 WB 000000
Signed-off-by: Akio Takebe <takebe_akio@xxxxxxxxxxxxxx>
Signed-off-by: Masaki Kanno <kanno.masaki@xxxxxxxxxxxxxx>
---
tools/xentrace/xenctx.c | 108 +++++++++++++++++++++++++++++++++++++++++++++---
1 files changed, 103 insertions(+), 5 deletions(-)
diff -r 9e9d8696fb55 -r aa8ca06d209e tools/xentrace/xenctx.c
--- a/tools/xentrace/xenctx.c Tue Oct 24 09:49:31 2006 -0600
+++ b/tools/xentrace/xenctx.c Tue Oct 24 10:08:30 2006 -0600
@@ -268,16 +268,68 @@ void print_ctx(vcpu_guest_context_t *ctx
}
#elif defined(__ia64__)
+
+#define PTE_ED_SHIFT 52
+#define PTE_ED_MASK 1
+#define PTE_PPN_SHIFT 12
+#define PTE_PPN_MASK 0x3fffffffff
+#define PTE_AR_SHIFT 9
+#define PTE_AR_MASK 7
+#define PTE_PL_SHIFT 7
+#define PTE_PL_MASK 3
+#define PTE_D_SHIFT 6
+#define PTE_D_MASK 1
+#define PTE_A_SHIFT 5
+#define PTE_A_MASK 1
+#define PTE_MA_SHIFT 2
+#define PTE_MA_MASK 7
+#define PTE_P_SHIFT 0
+#define PTE_P_MASK 1
+#define ITIR_KEY_SHIFT 8
+#define ITIR_KEY_MASK 0xffffff
+#define ITIR_PS_SHIFT 2
+#define ITIR_PS_MASK 0x3f
+#define ITIR_PS_MIN 12
+#define ITIR_PS_MAX 28
+#define RR_RID_SHIFT 8
+#define RR_RID_MASK 0xffffff
+
void print_ctx(vcpu_guest_context_t *ctx1)
{
struct cpu_user_regs *regs = &ctx1->user_regs;
-
- printf("iip: %016lx ", regs->cr_iip);
+ struct vcpu_extra_regs *er = &ctx1->extra_regs;
+ int i, ps_val, ma_val;
+ unsigned long pa;
+
+ const char ps[][5] = {" 4K", " 8K", " 16K", " ",
+ " 64K", " ", "256K", " ",
+ " 1M", " ", " 4M", " ",
+ " 16M", " ", " 64M", " ",
+ "256M"};
+ const char ma[][4] = {"WB ", " ", " ", " ",
+ "UC ", "UCE", "WC ", "Nat"};
+
+ printf(" iip: %016lx ", regs->cr_iip);
print_symbol(regs->cr_iip);
printf("\n");
- printf("psr: %016lu ", regs->cr_ipsr);
- printf(" b0: %016lx\n", regs->b0);
-
+ printf(" ipsr: %016lx ", regs->cr_ipsr);
+ printf(" b0: %016lx\n", regs->b0);
+ printf(" b6: %016lx ", regs->b6);
+ printf(" b7: %016lx\n", regs->b7);
+ printf(" cr_ifs: %016lx ", regs->cr_ifs);
+ printf(" ar_unat: %016lx\n", regs->ar_unat);
+ printf(" ar_pfs: %016lx ", regs->ar_pfs);
+ printf(" ar_rsc: %016lx\n", regs->ar_rsc);
+ printf(" ar_rnat: %016lx ", regs->ar_rnat);
+ printf(" ar_bspstore: %016lx\n", regs->ar_bspstore);
+ printf(" ar_fpsr: %016lx ", regs->ar_fpsr);
+ printf(" event_callback_ip: %016lx\n", er->event_callback_ip);
+ printf(" pr: %016lx ", regs->pr);
+ printf(" loadrs: %016lx\n", regs->loadrs);
+ printf(" iva: %016lx ", er->iva);
+ printf(" dcr: %016lx\n", er->dcr);
+
+ printf("\n");
printf(" r1: %016lx\n", regs->r1);
printf(" r2: %016lx ", regs->r2);
printf(" r3: %016lx\n", regs->r3);
@@ -310,6 +362,52 @@ void print_ctx(vcpu_guest_context_t *ctx
printf(" r30: %016lx ", regs->r30);
printf(" r31: %016lx\n", regs->r31);
+ printf("\n itr: P rid va pa ps ed pl "
+ "ar a d ma key\n");
+ for (i = 0; i < 8; i++) {
+ ps_val = er->itrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
+ ma_val = er->itrs[i].pte >> PTE_MA_SHIFT & PTE_MA_MASK;
+ pa = (er->itrs[i].pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
+ PTE_PPN_SHIFT;
+ pa = (pa >> ps_val) << ps_val;
+ printf(" [%d] %ld %06lx %016lx %013lx %02x %s %ld %ld %ld %ld "
+ "%ld %d %s %06lx\n", i,
+ er->itrs[i].pte >> PTE_P_SHIFT & PTE_P_MASK,
+ er->itrs[i].rid >> RR_RID_SHIFT & RR_RID_MASK,
+ er->itrs[i].vadr, pa, ps_val,
+ ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
+ ps[ps_val - ITIR_PS_MIN] : " "),
+ er->itrs[i].pte >> PTE_ED_SHIFT & PTE_ED_MASK,
+ er->itrs[i].pte >> PTE_PL_SHIFT & PTE_PL_MASK,
+ er->itrs[i].pte >> PTE_AR_SHIFT & PTE_AR_MASK,
+ er->itrs[i].pte >> PTE_A_SHIFT & PTE_A_MASK,
+ er->itrs[i].pte >> PTE_D_SHIFT & PTE_D_MASK,
+ ma_val, ma[ma_val],
+ er->itrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
+ }
+ printf("\n dtr: P rid va pa ps ed pl "
+ "ar a d ma key\n");
+ for (i = 0; i < 8; i++) {
+ ps_val = er->dtrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
+ ma_val = er->dtrs[i].pte >> PTE_MA_SHIFT & PTE_MA_MASK;
+ pa = (er->dtrs[i].pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
+ PTE_PPN_SHIFT;
+ pa = (pa >> ps_val) << ps_val;
+ printf(" [%d] %ld %06lx %016lx %013lx %02x %s %ld %ld %ld %ld "
+ "%ld %d %s %06lx\n", i,
+ er->dtrs[i].pte >> PTE_P_SHIFT & PTE_P_MASK,
+ er->dtrs[i].rid >> RR_RID_SHIFT & RR_RID_MASK,
+ er->dtrs[i].vadr, pa, ps_val,
+ ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
+ ps[ps_val - ITIR_PS_MIN] : " "),
+ er->dtrs[i].pte >> PTE_ED_SHIFT & PTE_ED_MASK,
+ er->dtrs[i].pte >> PTE_PL_SHIFT & PTE_PL_MASK,
+ er->dtrs[i].pte >> PTE_AR_SHIFT & PTE_AR_MASK,
+ er->dtrs[i].pte >> PTE_A_SHIFT & PTE_A_MASK,
+ er->dtrs[i].pte >> PTE_D_SHIFT & PTE_D_MASK,
+ ma_val, ma[ma_val],
+ er->dtrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
+ }
}
#endif
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