# HG changeset patch
# User kfraser@xxxxxxxxxxxxxxxxxxxxx
# Node ID 5ab400346b13b4a824ec11d36131aa748a79198a
# Parent 8905ffc1a3c842fdb297c2e6f5153cfee9cb369d
[HVM] Fix MSR read/write and add extra info when
write to MSR_EFER fails.
Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>
---
xen/arch/x86/hvm/svm/svm.c | 15 ++++++++-------
xen/arch/x86/hvm/vmx/vmx.c | 13 +++++++------
2 files changed, 15 insertions(+), 13 deletions(-)
diff -r 8905ffc1a3c8 -r 5ab400346b13 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c Wed Sep 27 09:29:46 2006 +0100
+++ b/xen/arch/x86/hvm/svm/svm.c Wed Sep 27 10:17:03 2006 +0100
@@ -282,7 +282,7 @@ static inline int long_mode_do_msr_read(
switch (regs->ecx)
{
case MSR_EFER:
- msr_content = vmcb->efer;
+ msr_content = vmcb->efer;
msr_content &= ~EFER_SVME;
break;
@@ -320,14 +320,14 @@ static inline int long_mode_do_msr_read(
HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n",
msr_content);
- regs->eax = msr_content & 0xffffffff;
- regs->edx = msr_content >> 32;
+ regs->eax = (u32)(msr_content >> 0);
+ regs->edx = (u32)(msr_content >> 32);
return 1;
}
static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
{
- u64 msr_content = regs->eax | ((u64)regs->edx << 32);
+ u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
struct vcpu *vc = current;
struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
@@ -342,7 +342,8 @@ static inline int long_mode_do_msr_write
/* offending reserved bit will cause #GP */
if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
{
- printk("trying to set reserved bit in EFER\n");
+ printk("Trying to set reserved bit in EFER: %016llx\n",
+ msr_content);
svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
return 0;
}
@@ -355,7 +356,7 @@ static inline int long_mode_do_msr_write
!test_bit(SVM_CPU_STATE_PAE_ENABLED,
&vc->arch.hvm_svm.cpu_state) )
{
- printk("trying to set LME bit when "
+ printk("Trying to set LME bit when "
"in paging mode or PAE bit is not set\n");
svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
return 0;
@@ -1997,7 +1998,7 @@ static inline void svm_do_msr_access(
else
{
inst_len = __get_instruction_length(vmcb, INSTR_WRMSR, NULL);
- msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
+ msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
switch (regs->ecx)
{
diff -r 8905ffc1a3c8 -r 5ab400346b13 xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c Wed Sep 27 09:29:46 2006 +0100
+++ b/xen/arch/x86/hvm/vmx/vmx.c Wed Sep 27 10:17:03 2006 +0100
@@ -269,15 +269,15 @@ static inline int long_mode_do_msr_read(
HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
- regs->eax = msr_content & 0xffffffff;
- regs->edx = msr_content >> 32;
+ regs->eax = (u32)(msr_content >> 0);
+ regs->edx = (u32)(msr_content >> 32);
return 1;
}
static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
{
- u64 msr_content = regs->eax | ((u64)regs->edx << 32);
+ u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
struct vcpu *v = current;
struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
@@ -290,7 +290,8 @@ static inline int long_mode_do_msr_write
/* offending reserved bit will cause #GP */
if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
{
- printk("trying to set reserved bit in EFER\n");
+ printk("Trying to set reserved bit in EFER: %016llx\n",
+ msr_content);
vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
return 0;
}
@@ -303,7 +304,7 @@ static inline int long_mode_do_msr_write
!test_bit(VMX_CPU_STATE_PAE_ENABLED,
&v->arch.hvm_vmx.cpu_state) )
{
- printk("trying to set LME bit when "
+ printk("Trying to set LME bit when "
"in paging mode or PAE bit is not set\n");
vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
return 0;
@@ -1924,7 +1925,7 @@ static inline void vmx_do_msr_write(stru
(unsigned long)regs->ecx, (unsigned long)regs->eax,
(unsigned long)regs->edx);
- msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
+ msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
switch (regs->ecx) {
case MSR_IA32_TIME_STAMP_COUNTER:
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