# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID 4acc6d51f3893d2b0c33c021f459ac12482858d9
# Parent 27ccf13dc3b7c37eadcc84f2682995ab3afc2543
[IA64] Optimize windows boot
Better handle multiple page size on the same region in windows OS,
Windows can boot within 2 minute in my box.
Signed-off-by: Anthony Xu <anthony.xu@xxxxxxxxx>
---
xen/arch/ia64/vmx/vtlb.c | 94 ++++++++++++++++++++++++-----------------
xen/include/asm-ia64/vmmu.h | 2
xen/include/asm-ia64/vmx_vpd.h | 3 +
3 files changed, 61 insertions(+), 38 deletions(-)
diff -r 27ccf13dc3b7 -r 4acc6d51f389 xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c Tue Aug 01 14:44:04 2006 -0600
+++ b/xen/arch/ia64/vmx/vtlb.c Tue Aug 01 14:58:20 2006 -0600
@@ -242,26 +242,31 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte)
void vtlb_purge(VCPU *v, u64 va, u64 ps)
{
+ thash_data_t *cur;
+ u64 start, end, curadr, size, psbits, tag, def_size;
+ ia64_rr vrr;
thash_cb_t *hcb = &v->arch.vtlb;
- thash_data_t *cur;
- u64 start, end, size, tag, rid, def_size;
- ia64_rr vrr;
vcpu_get_rr(v, va, &vrr.rrval);
- rid = vrr.rid;
+ psbits = VMX(v, psbits[(va >> 61)]);
size = PSIZE(ps);
start = va & (-size);
end = start + size;
- def_size = PSIZE(vrr.ps);
- while(start < end){
- cur = vsa_thash(hcb->pta, start, vrr.rrval, &tag);
- while (cur) {
- if (cur->etag == tag)
- cur->etag = 1UL << 63;
- cur = cur->next;
- }
- start += def_size;
- }
-// machine_tlb_purge(va, ps);
+ while (psbits) {
+ curadr = start;
+ ps = __ffs(psbits);
+ psbits &= ~(1UL << ps);
+ def_size = PSIZE(ps);
+ vrr.ps = ps;
+ while (curadr < end) {
+ cur = vsa_thash(hcb->pta, curadr, vrr.rrval, &tag);
+ while (cur) {
+ if (cur->etag == tag && cur->ps == ps)
+ cur->etag = 1UL << 63;
+ cur = cur->next;
+ }
+ curadr += def_size;
+ }
+ }
}
@@ -333,14 +338,15 @@ thash_data_t *__alloc_chain(thash_cb_t *
* 3: The caller need to make sure the new entry will not overlap
* with any existed entry.
*/
-void vtlb_insert(thash_cb_t *hcb, u64 pte, u64 itir, u64 va)
-{
- thash_data_t *hash_table, *cch;
+void vtlb_insert(VCPU *v, u64 pte, u64 itir, u64 va)
+{
+ thash_data_t *hash_table, *cch;
/* int flag; */
ia64_rr vrr;
/* u64 gppn, ppns, ppne; */
u64 tag, len;
- vcpu_get_rr(current, va, &vrr.rrval);
+ thash_cb_t *hcb = &v->arch.vtlb;
+ vcpu_get_rr(v, va, &vrr.rrval);
#ifdef VTLB_DEBUG
if (vrr.ps != itir_ps(itir)) {
// machine_tlb_insert(hcb->vcpu, entry);
@@ -349,6 +355,8 @@ void vtlb_insert(thash_cb_t *hcb, u64 pt
return;
}
#endif
+ vrr.ps = itir_ps(itir);
+ VMX(v, psbits[va >> 61]) |= (1UL << vrr.ps);
hash_table = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
if( INVALID_TLB(hash_table) ) {
len = hash_table->len;
@@ -446,9 +454,10 @@ void thash_purge_and_insert(VCPU *v, u64
{
u64 ps;//, va;
u64 phy_pte;
- ia64_rr vrr;
+ ia64_rr vrr, mrr;
ps = itir_ps(itir);
vcpu_get_rr(current, ifa, &vrr.rrval);
+ mrr.rrval = ia64_get_rr(ifa);
// if (vrr.ps != itir_ps(itir)) {
// printf("not preferred ps with va: 0x%lx vrr.ps=%d ps=%ld\n",
// ifa, vrr.ps, itir_ps(itir));
@@ -462,30 +471,33 @@ void thash_purge_and_insert(VCPU *v, u64
pte &= ~_PAGE_MA_MASK;
phy_pte = translate_phy_pte(v, &pte, itir, ifa);
- if (vrr.ps <= PAGE_SHIFT) {
+ vtlb_purge(v, ifa, ps);
+ vhpt_purge(v, ifa, ps);
+ if (ps == mrr.ps) {
if(!(pte&VTLB_PTE_IO)){
- vhpt_purge(v, ifa, ps);
vmx_vhpt_insert(&v->arch.vhpt, phy_pte, itir, ifa);
}
else{
- vhpt_purge(v, ifa, ps);
- vtlb_insert(&v->arch.vtlb, pte, itir, ifa);
+ vtlb_insert(v, pte, itir, ifa);
vcpu_quick_region_set(PSCBX(v,tc_regions),ifa);
}
}
- else{
- vhpt_purge(v, ifa, ps);
- vtlb_insert(&v->arch.vtlb, pte, itir, ifa);
+ else if (ps > mrr.ps) {
+ vtlb_insert(v, pte, itir, ifa);
vcpu_quick_region_set(PSCBX(v,tc_regions),ifa);
if(!(pte&VTLB_PTE_IO)){
vmx_vhpt_insert(&v->arch.vhpt, phy_pte, itir, ifa);
}
}
+ else {
+ // ps < mrr.ps, this is not supported
+ panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
+ }
}
else{
phy_pte = translate_phy_pte(v, &pte, itir, ifa);
if(ps!=PAGE_SHIFT){
- vtlb_insert(&v->arch.vtlb, pte, itir, ifa);
+ vtlb_insert(v, pte, itir, ifa);
vcpu_quick_region_set(PSCBX(v,tc_regions),ifa);
}
machine_tlb_purge(ifa, ps);
@@ -507,11 +519,15 @@ void thash_purge_all(VCPU *v)
vtlb =&v->arch.vtlb;
vhpt =&v->arch.vhpt;
+ for (num = 0; num < 8; num++)
+ VMX(v, psbits[num]) = 0;
+
head=vtlb->hash;
num = (vtlb->hash_sz/sizeof(thash_data_t));
do{
head->page_flags = 0;
head->etag = 1UL<<63;
+ head->itir = 0;
head->next = 0;
head++;
num--;
@@ -543,7 +559,7 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
thash_data_t *vtlb_lookup(VCPU *v, u64 va,int is_data)
{
thash_data_t *cch;
- u64 tag;
+ u64 psbits, ps, tag;
ia64_rr vrr;
thash_cb_t * hcb= &v->arch.vtlb;
@@ -552,15 +568,19 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
if(vcpu_quick_region_check(v->arch.tc_regions,va)==0)
return NULL;
-
+ psbits = VMX(v, psbits[(va >> 61)]);
vcpu_get_rr(v,va,&vrr.rrval);
- cch = vsa_thash( hcb->pta, va, vrr.rrval, &tag);
-
- do{
- if(cch->etag == tag)
- return cch;
- cch = cch->next;
- }while(cch);
+ while (psbits) {
+ ps = __ffs(psbits);
+ psbits &= ~(1UL << ps);
+ vrr.ps = ps;
+ cch = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
+ do {
+ if (cch->etag == tag && cch->ps == ps)
+ return cch;
+ cch = cch->next;
+ } while(cch);
+ }
return NULL;
}
diff -r 27ccf13dc3b7 -r 4acc6d51f389 xen/include/asm-ia64/vmmu.h
--- a/xen/include/asm-ia64/vmmu.h Tue Aug 01 14:44:04 2006 -0600
+++ b/xen/include/asm-ia64/vmmu.h Tue Aug 01 14:58:20 2006 -0600
@@ -302,7 +302,7 @@ extern int fetch_code(struct vcpu *vcpu,
extern int fetch_code(struct vcpu *vcpu, u64 gip, u64 *code1, u64 *code2);
extern void emulate_io_inst(struct vcpu *vcpu, u64 padr, u64 ma);
extern int vhpt_enabled(struct vcpu *vcpu, uint64_t vadr, vhpt_ref_t ref);
-extern void vtlb_insert(thash_cb_t *hcb, u64 pte, u64 itir, u64 va);
+extern void vtlb_insert(struct vcpu *vcpu, u64 pte, u64 itir, u64 va);
extern u64 translate_phy_pte(struct vcpu *v, u64 *pte, u64 itir, u64 va);
extern void thash_vhpt_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa);
extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);
diff -r 27ccf13dc3b7 -r 4acc6d51f389 xen/include/asm-ia64/vmx_vpd.h
--- a/xen/include/asm-ia64/vmx_vpd.h Tue Aug 01 14:44:04 2006 -0600
+++ b/xen/include/asm-ia64/vmx_vpd.h Tue Aug 01 14:58:20 2006 -0600
@@ -77,6 +77,9 @@ struct arch_vmx_struct {
vtime_t vtm;
struct vlapic vlapic;
unsigned long vrr[8];
+ /* if the corresponding bit is 1, then this page size is
+ used in this region */
+ unsigned long psbits[8];
unsigned long vkr[8];
unsigned long cr_iipa; /* for emulation */
unsigned long cr_isr; /* for emulation */
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