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[Xen-changelog] [xen-unstable] [qemu patches] Update patches for changes

To: xen-changelog@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-changelog] [xen-unstable] [qemu patches] Update patches for changeset 10943:1de1bb6a51c5.
From: Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>
Date: Fri, 04 Aug 2006 12:10:22 +0000
Delivery-date: Fri, 04 Aug 2006 05:13:56 -0700
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# HG changeset patch
# User chris@xxxxxxxxxxxxxxxxxxxxxxxx
# Node ID 23166260f6ce22206e59e4767d386133ffe1b76b
# Parent  1de1bb6a51c565924aa44645c67a4305a5a8c69a
[qemu patches] Update patches for changeset 10943:1de1bb6a51c5.

Signed-off-by: Christian Limpach <Christian.Limpach@xxxxxxxxxxxxx>
---
 tools/ioemu/patches/acpi-timer-support |  226 +++++++++++++++++++--------------
 1 files changed, 132 insertions(+), 94 deletions(-)

diff -r 1de1bb6a51c5 -r 23166260f6ce tools/ioemu/patches/acpi-timer-support
--- a/tools/ioemu/patches/acpi-timer-support    Fri Aug 04 11:33:41 2006 +0100
+++ b/tools/ioemu/patches/acpi-timer-support    Fri Aug 04 11:34:01 2006 +0100
@@ -1,116 +1,118 @@ diff -r 45c8b171d210 hw/piix4acpi.c
-diff -r 45c8b171d210 hw/piix4acpi.c
---- a/hw/piix4acpi.c   Wed Jun 28 20:33:30 2006 +0100
-+++ b/hw/piix4acpi.c   Thu Jun 29 09:34:35 2006 +0100
-@@ -49,6 +49,13 @@ AcpiDeviceState *acpi_device_table;
+Index: ioemu/hw/piix4acpi.c
+===================================================================
+--- ioemu.orig/hw/piix4acpi.c  2006-08-04 10:57:28.922994985 +0100
++++ ioemu/hw/piix4acpi.c       2006-08-04 11:23:48.127374982 +0100
+@@ -24,31 +24,30 @@
+  */
+ 
+ #include "vl.h"
+-#define FREQUENCE_PMTIMER  3753425
++#define FREQUENCE_PMTIMER  3579545
+ /* acpi register bit define here  */
+ 
+-/* PM1_STS                                            */
+-#define TMROF_STS       (1 << 0)
+-#define BM_STS                  (1 << 4)
+-#define GBL_STS         (1 << 5)
+-#define PWRBTN_STS      (1 << 8)
+-#define RTC_STS         (1 << 10)
++/* PM1_STS */
++#define TMROF_STS         (1 << 0)
++#define BM_STS            (1 << 4)
++#define GBL_STS           (1 << 5)
++#define PWRBTN_STS        (1 << 8)
++#define RTC_STS           (1 << 10)
+ #define PRBTNOR_STS       (1 << 11)
+-#define WAK_STS         (1 << 15)
+-/* PM1_EN                                             */
++#define WAK_STS           (1 << 15)
++/* PM1_EN */
+ #define TMROF_EN          (1 << 0)
+ #define GBL_EN            (1 << 5)
+ #define PWRBTN_EN         (1 << 8)
+-#define RTC_EN          (1 << 10)
+-/* PM1_CNT                                            */
++#define RTC_EN            (1 << 10)
++/* PM1_CNT */
+ #define SCI_EN            (1 << 0)
+ #define GBL_RLS           (1 << 2)
+-#define SLP_EN          (1 << 13)
++#define SLP_EN            (1 << 13)
+ 
+ typedef struct AcpiDeviceState AcpiDeviceState;
  AcpiDeviceState *acpi_device_table;
  
- /* Bits of PM1a register define here  */
-+typedef struct PMTState {
-+    uint32_t count;
-+    int irq;
-+    uint64_t next_pm_time;
-+    QEMUTimer *pm_timer;
-+}PMTState;
-+
+-/* Bits of PM1a register define here  */
  typedef struct PM1Event_BLK {
      uint16_t pm1_status; /* pm1a_EVT_BLK */
      uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
-@@ -63,13 +70,80 @@ typedef struct PCIAcpiState {
+@@ -61,17 +60,11 @@
+     uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
+     uint16_t pm1_control; /* pm1a_ECNT_BLK */
      uint32_t pm1_timer; /* pmtmr_BLK */
++    uint64_t old_vmck_ticks /* using vm_clock counter */
  } PCIAcpiState;
  
-+static PMTState *pmtimer_state;
  static PCIAcpiState *acpi_state;
-+
-+static void pmtimer_save(QEMUFile *f, void *opaque)
-+{
-+    PMTState *s = opaque;
-+
-+    qemu_put_be32s(f, &s->count);
-+    qemu_put_be32s(f, &s->irq);
-+    qemu_put_be64s(f, &s->next_pm_time);
-+    qemu_put_timer(f, s->pm_timer);
-+}
-+
-+static int pmtimer_load(QEMUFile *f, void *opaque, int version_id)
-+{
-+    PMTState *s = opaque;
-+
-+    if (version_id != 1)
-+        return -EINVAL;
-+    qemu_get_be32s(f, &s->count);
-+    qemu_get_be32s(f, &s->irq);
-+    qemu_get_be64s(f, &s->next_pm_time);
-+    qemu_get_timer(f, s->pm_timer);
-+    return 0;
-+}
  
- static inline void acpi_set_irq(PCIAcpiState *s)
+-static inline void acpi_set_irq(PCIAcpiState *s)
+-{
+-/* no real SCI event need for now, so comment the following line out */
+-/*  pic_set_irq(s->irq, 1); */
+-    printf("acpi_set_irq: s->irq %x \n",s->irq);
+-}
+-
+ static void acpi_reset(PCIAcpiState *s)
  {
- /* no real SCI event need for now, so comment the following line out */
- /*  pic_set_irq(s->irq, 1); */
-     printf("acpi_set_irq: s->irq %x \n",s->irq);
-+}
-+
-+static void pm_timer_update(void *opaque)
-+{
-+    PMTState *s = opaque;
-+    s->next_pm_time = qemu_get_clock(vm_clock) +
-+        muldiv64(1, ticks_per_sec,FREQUENCE_PMTIMER);
-+    qemu_mod_timer(s->pm_timer, s->next_pm_time);
-+    acpi_state->pm1_timer ++;
-+
-+    /* If pm timer is zero then reset it to zero. */
-+    if (acpi_state->pm1_timer >= 0x1000000) {
-+/*      printf("pm_timerupdate: timer overflow: %x \n", 
acpi_state->pm1_timer); */
-+
-+        acpi_state->pm1_timer = 0;
-+        acpi_state->pm1_status =   acpi_state->pm1_status | TMROF_STS;
-+        /* If TMROF_EN is set then send the irq. */
-+        if ((acpi_state->pm1_enable & TMROF_EN) == TMROF_EN) {
-+            acpi_set_irq(acpi_state);
-+            acpi_state->pm1_enable = 0x00; /* only need one time...*/
-+        }
-+    }
-+    s->count = acpi_state->pm1_timer;
-+}
-+
-+static PMTState *pmtimer_init(void)
-+{
-+    PMTState *s;
-+
-+    s = qemu_mallocz(sizeof(PMTState));
-+    if (!s)
-+        return NULL;
-+
-+    /* s->irq = irq;    */
-+
-+    s->pm_timer = qemu_new_timer(vm_clock, pm_timer_update, s);
-+
-+    s->count = 0;
-+    s->next_pm_time = qemu_get_clock(vm_clock) + muldiv64(1, 
ticks_per_sec,FREQUENCE_PMTIMER) + 1;
-+    qemu_mod_timer(s->pm_timer, s->next_pm_time);
-+
-+    register_savevm("pm timer", 1, 1, pmtimer_save, pmtimer_load, s);
-+    return s;
+     uint8_t *pci_conf;
+@@ -84,6 +77,7 @@
+     s->pm1_enable = 0x00;    /* TMROF_EN should cleared */
+     s->pm1_control = SCI_EN; /* SCI_EN */
+     s->pm1_timer = 0;
++    s->old_vmck_ticks = qemu_get_clock(vm_clock);
  }
  
- static void acpi_reset(PCIAcpiState *s)
-@@ -288,13 +362,15 @@ static void acpiPm1Event_writel(void *op
+ /*byte access  */
+@@ -95,8 +89,8 @@
+         s->pm1_status = s->pm1_status&!TMROF_STS;
+ 
+     if ((val&GBL_STS)==GBL_STS)
+-        s->pm1_status = s->pm1_status&!GBL_STS;     
+-    
++        s->pm1_status = s->pm1_status&!GBL_STS;
++
+ /*     printf("acpiPm1Status_writeb \n addr %x val:%x pm1_status:%x \n", 
addr, val,s->pm1_status); */
+ }
+ 
+@@ -115,7 +109,7 @@
+ {
+     PCIAcpiState *s = opaque;
+ 
+-     s->pm1_status = (val<<8)||(s->pm1_status);
++    s->pm1_status = (val<<8)||(s->pm1_status);
+ /*     printf("acpiPm1StatusP1_writeb \n addr %x val:%x\n", addr, val); */
+ }
+ 
+@@ -220,7 +214,7 @@
+         s->pm1_status = s->pm1_status&!TMROF_STS;
+ 
+     if ((val&GBL_STS)==GBL_STS)
+-        s->pm1_status = s->pm1_status&!GBL_STS;     
++        s->pm1_status = s->pm1_status&!GBL_STS;
+ 
+ /*    printf("acpiPm1Status_writew \n addr %x val:%x pm1_status:%x \n", addr, 
val,s->pm1_status); */
+ }
+@@ -288,13 +282,15 @@
  
  }
  
 -static void acpiPm1Event_readl(void *opaque, uint32_t addr)
--{
--    PCIAcpiState *s = opaque;
--    uint32_t val;
--
++static uint32_t acpiPm1Event_readl(void *opaque, uint32_t addr)
+ {
+     PCIAcpiState *s = opaque;
+     uint32_t val;
+ 
 -    val=s->pm1_status|(s->pm1_enable<<16);
-+static uint32_t acpiPm1Event_readl(void *opaque, uint32_t addr)
-+{
-+    PCIAcpiState *s = opaque;
-+    uint32_t val;
-+    
 +    val = s->pm1_status|(s->pm1_enable<<16);
  /*    printf("acpiPm1Event_readl \n addr %x val:%x\n", addr, val);    */
 +
@@ -118,11 +120,76 @@ diff -r 45c8b171d210 hw/piix4acpi.c
  }
  
  static void acpiPm1Timer_writel(void *opaque, uint32_t addr, uint32_t val)
-@@ -384,5 +460,7 @@ void pci_piix4_acpi_init(PCIBus *bus)
+@@ -302,17 +298,21 @@
+     PCIAcpiState *s = opaque;
+ 
+     s->pm1_timer = val;
+-/*    printf("acpiPm1Timer_writel \n addr %x val:%x\n", addr, val); */
++    s->old_vmck_ticks = qemu_get_clock(vm_clock) +
++        muldiv64(val, FREQUENCE_PMTIMER, ticks_per_sec);
+ }
+ 
+ static uint32_t acpiPm1Timer_readl(void *opaque, uint32_t addr)
+ {
+     PCIAcpiState *s = opaque;
+-    uint32_t val;
++    int64_t current_vmck_ticks = qemu_get_clock(vm_clock);
++    int64_t vmck_ticks_delta = current_vmck_ticks - s->old_vmck_ticks;
+ 
+-    val = s->pm1_timer;
+-/*    printf("acpiPm1Timer_readl \n addr %x val:%x\n", addr, val); */
+-    return val;
++    if (s->old_vmck_ticks)
++        s->pm1_timer += muldiv64(vmck_ticks_delta, FREQUENCE_PMTIMER,
++                                 ticks_per_sec);
++    s->old_vmck_ticks = current_vmck_ticks;
++    return s->pm1_timer;
+ }
+ 
+ static void acpi_map(PCIDevice *pci_dev, int region_num,
+@@ -320,7 +320,7 @@
+ {
+     PCIAcpiState *d = (PCIAcpiState *)pci_dev;
+ 
+-    printf("register acpi io \n");
++    printf("register acpi io\n");
+ 
+     /* Byte access */
+     register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d);
+@@ -336,14 +336,14 @@
+     register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
+     register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
+     register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
+-    register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);       
++    register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
+ 
+     /* Word access */
+     register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d);
+     register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d);
+ 
+     register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d);
+-    register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d); 
++    register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d);
+ 
+     register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
+     register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
+@@ -351,11 +351,10 @@
+     /* DWord access */
+     register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d);
+     register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d);
+-              
++
+     register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d);
+     register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d);
+ }
+-                                                                              
                        
+ 
+ /* PIIX4 acpi pci configuration space, func 3 */
+ void pci_piix4_acpi_init(PCIBus *bus)
+@@ -384,5 +383,5 @@
      pci_register_io_region((PCIDevice *)d, 4, 0x10,
                             PCI_ADDRESS_SPACE_IO, acpi_map);
  
-+    pmtimer_state = pmtimer_init();
-+
-     acpi_reset (d);
+-    acpi_reset (d);
++    acpi_reset(d);
  }

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