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[Xen-changelog] Update microcode.c to linux-2.6.16-rc5 codebase.

To: xen-changelog@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-changelog] Update microcode.c to linux-2.6.16-rc5 codebase.
From: Xen patchbot -unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>
Date: Mon, 06 Mar 2006 16:32:14 +0000
Delivery-date: Mon, 06 Mar 2006 16:33:03 +0000
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# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID e8fb817c4c1530b9f763b8a726aa00d805173a56
# Parent  941897e985917b61de194bf4334aa531156e796f
Update microcode.c to linux-2.6.16-rc5 codebase.

Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>

diff -r 941897e98591 -r e8fb817c4c15 xen/arch/x86/microcode.c
--- a/xen/arch/x86/microcode.c  Mon Mar  6 14:30:12 2006
+++ b/xen/arch/x86/microcode.c  Mon Mar  6 14:39:48 2006
@@ -116,7 +116,7 @@
 #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
 
 /* serialize access to the physical write to MSR 0x79 */
-static spinlock_t microcode_update_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(microcode_update_lock);
 
 /* no concurrent ->write()s are allowed on /dev/cpu/microcode */
 static DECLARE_MUTEX(microcode_sem);
@@ -166,7 +166,8 @@
        }
 
        wrmsr(MSR_IA32_UCODE_REV, 0, 0);
-       __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
+       /* see notes above for revision 1.07.  Apparent chip bug */
+       sync_core();
        /* get the current revision from MSR 0x8B */
        rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev);
        pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
@@ -366,7 +367,7 @@
        struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
 
        if (uci->mc == NULL) {
-               printk(KERN_INFO "microcode: No suitable data for CPU%d\n", 
cpu_num);
+               printk(KERN_INFO "microcode: No new microcode data for 
CPU%d\n", cpu_num);
                return;
        }
 
@@ -379,7 +380,9 @@
                (unsigned long) uci->mc->bits >> 16 >> 16);
        wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 
-       __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
+       /* see notes above for revision 1.07.  Apparent chip bug */
+       sync_core();
+
        /* get the current revision from MSR 0x8B */
        rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
 
diff -r 941897e98591 -r e8fb817c4c15 xen/include/asm-x86/processor.h
--- a/xen/include/asm-x86/processor.h   Mon Mar  6 14:30:12 2006
+++ b/xen/include/asm-x86/processor.h   Mon Mar  6 14:39:48 2006
@@ -352,6 +352,13 @@
        outb((reg), 0x22); \
        outb((data), 0x23); \
 } while (0)
+
+/* Stop speculative execution */
+static inline void sync_core(void)
+{
+    int tmp;
+    asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
+}
 
 static always_inline void __monitor(const void *eax, unsigned long ecx,
                unsigned long edx)

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