ChangeSet 1.1709.1.2, 2005/06/13 14:50:16-06:00, djm@xxxxxxxxxxxxxxx
Finish reserved VA bit assignment, handle uncached address
range with lower half (0xe8...0-0xefff...f) of reserved
range in region 7
Signed-off by: Dan Magenheimer <dan.magenheimer@xxxxxx>
ivt.S | 31 +++++++++++++++++++++++--------
patch/linux-2.6.11/io.h | 1 -
2 files changed, 23 insertions(+), 9 deletions(-)
diff -Nru a/xen/arch/ia64/ivt.S b/xen/arch/ia64/ivt.S
--- a/xen/arch/ia64/ivt.S 2005-06-19 14:03:33 -04:00
+++ b/xen/arch/ia64/ivt.S 2005-06-19 14:03:33 -04:00
@@ -367,9 +367,15 @@
#endif
extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
+#ifdef XEN
+ shr.u r18=r16,55 // move address bit 59 to bit 4
+ ;;
+ and r18=0x10,r18 // bit 4=address-bit(59)
+#else
shr.u r18=r16,57 // move address bit 61 to bit 4
;;
andcm r18=0x10,r18 // bit 4=~address-bit(61)
+#endif
cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
or r19=r17,r19 // insert PTE control bits into r19
;;
@@ -414,24 +420,33 @@
extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
+#ifdef XEN
+ shr.u r18=r16,55 // move address bit 59 to bit 4
+ and r19=r19,r16 // clear ed, reserved bits, and
PTE control bits
+ tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
+ ;;
+ and r18=0x10,r18 // bit 4=address-bit(59)
+#else
shr.u r18=r16,57 // move address bit 61 to bit 4
and r19=r19,r16 // clear ed, reserved bits, and
PTE control bits
tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
;;
andcm r18=0x10,r18 // bit 4=~address-bit(61)
+#endif
cmp.ne p8,p0=r0,r23
(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
(p8) br.cond.spnt page_fault
#ifdef XEN
;;
- // FIXME: inadequate test, this is where we test for Xen address
- // note that 0xf000 (cached) and 0xd000 (uncached) addresses
- // should be OK. (Though no I/O is done in Xen, EFI needs uncached
- // addresses and some domain EFI calls are passed through)
- tbit.nz p0,p8=r16,60
-(p8) br.cond.spnt page_fault
-//(p8) br.cond.spnt 0
- ;;
+ // Test for Xen address, if not handle via page_fault
+ // note that 0xf000 (cached) and 0xe800 (uncached) addresses
+ // should be OK.
+ extr.u r22=r16,59,5;;
+ cmp.eq p8,p0=0x1e,r22
+(p8) br.cond.spnt 1f;;
+ cmp.ne p8,p0=0x1d,r22
+(p8) br.cond.sptk page_fault ;;
+1:
#endif
dep r21=-1,r21,IA64_PSR_ED_BIT,1
diff -Nru a/xen/arch/ia64/patch/linux-2.6.11/io.h
b/xen/arch/ia64/patch/linux-2.6.11/io.h
--- a/xen/arch/ia64/patch/linux-2.6.11/io.h 2005-06-19 14:03:33 -04:00
+++ b/xen/arch/ia64/patch/linux-2.6.11/io.h 2005-06-19 14:03:33 -04:00
@@ -5,7 +5,7 @@
#define SLOW_DOWN_IO do { } while (0)
+#ifdef XEN
-+#define __IA64_UNCACHED_OFFSET 0xd000000000000000UL /* region 6 */
++#define __IA64_UNCACHED_OFFSET 0xe800000000000000UL
+#else
#define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */
+#endif
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