ChangeSet 1.1699, 2005/06/08 15:05:21+01:00, kaf24@xxxxxxxxxxxxxxxxxxxx
First phase of removing IRQ numbers from Xen (transitioning to
IRQ addressing by 'legacy ISA IRQ', 'interrupt vector', and
'I/O APIC address + pin' as appropriate). Overall plan is to move
I/O APIC parsing and setup out of Xen (so we start DOM0 in virtual wire
mode).
Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>
arch/ia64/irq.c | 22 ------------
arch/x86/i8259.c | 47 ++++++++-------------------
arch/x86/io_apic.c | 40 +++++++++--------------
arch/x86/irq.c | 79 +++++++++++++++++-----------------------------
arch/x86/physdev.c | 3 -
arch/x86/smpboot.c | 6 ---
include/asm-x86/hardirq.h | 4 +-
include/asm-x86/irq.h | 19 ++++-------
include/xen/irq.h | 1
9 files changed, 72 insertions(+), 149 deletions(-)
diff -Nru a/xen/arch/ia64/irq.c b/xen/arch/ia64/irq.c
--- a/xen/arch/ia64/irq.c 2005-06-08 11:01:31 -04:00
+++ b/xen/arch/ia64/irq.c 2005-06-08 11:01:31 -04:00
@@ -1471,28 +1471,6 @@
return 0;
}
-int pirq_guest_bindable(int irq, int will_share)
-{
- irq_desc_t *desc = &irq_desc[irq];
- irq_guest_action_t *action;
- unsigned long flags;
- int okay;
-
- spin_lock_irqsave(&desc->lock, flags);
-
- action = (irq_guest_action_t *)desc->action;
-
- /*
- * To be bindable the IRQ must either be not currently bound (1), or
- * it must be shareable (2) and not at its share limit (3).
- */
- okay = ((!(desc->status & IRQ_GUEST) && (action == NULL)) || /* 1 */
- (action->shareable && will_share && /* 2 */
- (action->nr_guests != IRQ_MAX_GUESTS))); /* 3 */
-
- spin_unlock_irqrestore(&desc->lock, flags);
- return okay;
-}
#endif
#ifdef XEN
diff -Nru a/xen/arch/x86/i8259.c b/xen/arch/x86/i8259.c
--- a/xen/arch/x86/i8259.c 2005-06-08 11:01:31 -04:00
+++ b/xen/arch/x86/i8259.c 2005-06-08 11:01:31 -04:00
@@ -43,28 +43,10 @@
BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
BI(x,c) BI(x,d) BI(x,e) BI(x,f)
-/*
- * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
- * (these are usually mapped to vectors 0x20-0x2f)
- */
-BUILD_16_IRQS(0x0)
-
-#ifdef CONFIG_X86_IO_APIC
-/*
- * The IO-APIC gives us many more interrupt sources. Most of these
- * are unused but an SMP system is supposed to have enough memory ...
- * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
- * across the spectrum, so we really want to be prepared to get all
- * of these. Plus, more powerful systems might have more than 64
- * IO-APIC registers.
- *
- * (these are usually mapped into the 0x20-0xff vector range)
- */
-BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
+BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
-BUILD_16_IRQS(0xc)
-#endif
+BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
#undef BUILD_16_IRQS
#undef BI
@@ -101,15 +83,11 @@
IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
- void (*interrupt[NR_IRQS])(void) = {
- IRQLIST_16(0x0),
-
-#ifdef CONFIG_X86_IO_APIC
- IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
+ static void (*interrupt[])(void) = {
+ IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
- IRQLIST_16(0xc)
-#endif
+ IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
};
#undef IRQ
@@ -128,7 +106,7 @@
static void end_8259A_irq (unsigned int irq)
{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ if (!(irq_desc[irq_to_vector(irq)].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_8259A_irq(irq);
}
@@ -225,7 +203,7 @@
{
disable_irq_nosync(irq);
io_apic_irqs &= ~(1<<irq);
- irq_desc[irq].handler = &i8259A_irq_type;
+ irq_desc[irq_to_vector(irq)].handler = &i8259A_irq_type;
enable_irq(irq);
}
@@ -384,11 +362,17 @@
for ( i = 0; i < NR_IRQS; i++ )
{
irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].handler = (i<16) ? &i8259A_irq_type : &no_irq_type;
+ irq_desc[i].handler = &no_irq_type;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
spin_lock_init(&irq_desc[i].lock);
- set_intr_gate(FIRST_EXTERNAL_VECTOR+i, interrupt[i]);
+ set_intr_gate(i, interrupt[i]);
+ }
+
+ for ( i = 0; i < 16; i++ )
+ {
+ vector_irq[LEGACY_VECTOR(i)] = i;
+ irq_desc[LEGACY_VECTOR(i)].handler = &i8259A_irq_type;
}
/*
@@ -397,7 +381,6 @@
*/
irq_vector[0] = FIRST_DEVICE_VECTOR;
vector_irq[FIRST_DEVICE_VECTOR] = 0;
- set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
/* Various IPI functions. */
set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
diff -Nru a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
--- a/xen/arch/x86/io_apic.c 2005-06-08 11:01:31 -04:00
+++ b/xen/arch/x86/io_apic.c 2005-06-08 11:01:31 -04:00
@@ -65,12 +65,14 @@
} irq_2_pin[PIN_MAP_SIZE];
int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
+#if 0
#ifdef CONFIG_PCI_MSI
#define vector_to_irq(vector) \
(platform_legacy_irq(vector) ? vector : vector_irq[vector])
#else
#define vector_to_irq(vector) (vector)
#endif
+#endif
/*
* The common case is 1:1 IRQ<->pin mappings. Sometimes there are
@@ -657,21 +659,11 @@
static inline void ioapic_register_intr(int irq, int vector, unsigned long
trigger)
{
- if (use_pci_vector() && !platform_legacy_irq(irq)) {
- if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
- trigger == IOAPIC_LEVEL)
- irq_desc[vector].handler = &ioapic_level_type;
- else
- irq_desc[vector].handler = &ioapic_edge_type;
- set_intr_gate(vector, interrupt[vector]);
- } else {
- if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
- trigger == IOAPIC_LEVEL)
- irq_desc[irq].handler = &ioapic_level_type;
- else
- irq_desc[irq].handler = &ioapic_edge_type;
- set_intr_gate(vector, interrupt[irq]);
- }
+ if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
+ trigger == IOAPIC_LEVEL)
+ irq_desc[vector].handler = &ioapic_level_type;
+ else
+ irq_desc[vector].handler = &ioapic_edge_type;
}
void __init setup_IO_APIC_irqs(void)
@@ -781,7 +773,7 @@
* The timer IRQ doesn't have to know that behind the
* scene we have a 8259A-master in AEOI mode ...
*/
- irq_desc[0].handler = &ioapic_edge_type;
+ irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
/*
* Add it to the IO-APIC irq-routing table:
@@ -1176,7 +1168,7 @@
*/
static void ack_edge_ioapic_irq(unsigned int irq)
{
- if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
+ if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING |
IRQ_DISABLED))
== (IRQ_PENDING | IRQ_DISABLED))
mask_IO_APIC_irq(irq);
ack_APIC_irq();
@@ -1354,11 +1346,13 @@
*/
for (irq = 0; irq < NR_IRQS ; irq++) {
int tmp = irq;
+#if 0
if (use_pci_vector()) {
if (!platform_legacy_irq(tmp))
if ((tmp = vector_to_irq(tmp)) == -1)
continue;
}
+#endif
if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
/*
* Hmm.. We don't have an entry for this,
@@ -1367,9 +1361,6 @@
*/
if (irq < 16)
make_8259A_irq(irq);
- else
- /* Strange. Oh, well.. */
- irq_desc[irq].handler = &no_irq_type;
}
}
}
@@ -1485,7 +1476,10 @@
*/
disable_8259A_irq(0);
vector = assign_irq_vector(0);
- set_intr_gate(vector, interrupt[0]);
+
+ irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
+ irq_desc[IO_APIC_VECTOR(0)].depth = 0;
+ irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
/*
* Subtle, code in do_timer_interrupt() expects an AEOI
@@ -1546,7 +1540,7 @@
printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
disable_8259A_irq(0);
- irq_desc[0].handler = &lapic_irq_type;
+ irq_desc[vector].handler = &lapic_irq_type;
apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
enable_8259A_irq(0);
@@ -1834,7 +1828,7 @@
return 0;
/* Set the correct irq-handling type. */
- irq_desc[irq].handler = rte.trigger ?
+ irq_desc[IO_APIC_VECTOR(irq)].handler = rte.trigger ?
&ioapic_level_type: &ioapic_edge_type;
/* Record the pin<->irq mapping. */
diff -Nru a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
--- a/xen/arch/x86/irq.c 2005-06-08 11:01:31 -04:00
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